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2015-02-05southbridge/amd/pi: Update Kconfig and makefiles for boltonDave Frodin
Change-Id: I208c931bdaee572c9df11b35c1e6e9f27609ea6c Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8287 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-16Drop GX1, CS5330 and related boardsStefan Reinauer
There is no Cache As Ram for these boards, let's get rid of them. Change-Id: Ib41f8cd64fc9a440838aea86076d6514aacb301c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7117 Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-20AMD: Isolate AGESA and PI build environments for southbridgeKyösti Mälkki
To backport features introduced with recent Chromebooks and/or Intel boards in general, heavy work on the AMD AGESA platform infrastructure is required. With the AGESA PI available in binary form only, community members have little means to verify, debug and develop for the said platforms. Thus it makes sense to fork the existing agesawrapper interfaces, to give AMD PI platforms a clean and independent sandbox. New directory layout reflects the separation already taken place under 3rdparty/ and vendorcode/. Change-Id: Ia730f0e45e7c1bdfc0c91e95eb6729a77773e2b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7388 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Tested-by: build bot (Jenkins)
2014-08-30AMD Steppe Eagle: New integrated southbridge (Avalon)Bruce Griffith
00730F01 contains the Avalon southbridge and a Platform Security Processor (PSP). Supporting the PSP requires specific binaries to be included in the ROM. The fletcher utility is used to sign PSP binaries. The IMC access routines are not accessible for newer AMD parts that use pre-compiled AGESA. Change the Hudson code such that the IMC code is not compiled if IMC is not selected in Kconfig. Disable compilation of resume.c if HAVE_ACPI_RESUME is disabled. The newer AMD mainboards will initially be released without ACPI resume support (S3) due to the use of AGESA internals in the existing Hudson routines. The Makefile change allows newer mainboards to avoid the API issues. Change Kconfig such that the FWM flag is always set for PSP-enabled parts. This has the side effect of forcing the generation of the FWM directory in the absence of GEC, IMC, and xHCI. Change-Id: I6d056f54b60a64300841599490b9fafd561c4a7d Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6677 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2014-07-02AMD/agesa: Add functions for AMD PCI IRQ routingDave Frodin
Port the changes that were made in amd/cimx to amd/agesa as were done in: commit c93a75a5ab067f86104028b74d92fc54cb939cd5 Author: Mike Loptien <mike.loptien@se-eng.com> Date: Fri Jun 6 15:16:29 2014 -0600 AMD/CIMx: Add functions for AMD PCI IRQ routing This change also moves the PCI INT functions to southbridge/amd so that they can be used by CIMX and AGESA. The amd/persimmon board is updated for this change. Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Change-Id: I525be90f9cf8e825e162d53a7ecd1e69c6e27637 Reviewed-on: http://review.coreboot.org/6065 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-25AGESA: Move config parameters for non-volatile S3 dataKyösti Mälkki
These parameters are not specific to the southbridge device, but the implementation of S3 storage defined by CPU code. Change-Id: Ic341cc2b7669cf8e3e920c48473826ec03fc7d8d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6081 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-05AMD Kabini: Modify Hudson southbridge to support new AMD processorSiyuan Wang
Yangtze uses Hudson AGESA wrapper code but has some changes. The changes are necessary and have no effects on Hudson. Change-Id: Iada90d34fdc2025bd14f566488ee12810a28ac0d Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3783 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-02-21AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE'Zheng Bao
Currently the size of the volatile storage for S3 reserved in the image is hardcoded to 32768 bytes. Make that configurable by introducing the Kconfig 'S3_DATA_SIZE'. As the storage space is needed for storing non-volatile, volatile and MTRR data, add a check if the size is big enough. Change-Id: I9152797cf0045c8da48109a9d760e417717686db Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2383 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-19AMD S3: Change S3_VOLATILE_POS to S3_DATA_POSZheng Bao
S3_DATA_POS defines address where the whole S3 data is stored. Change-Id: I4155a0821e74a3653caaead890e5fec5677637aa Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2438 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-14AMD S3: Rename generated s3.rom for make cleanZheng Bao
Add prefix coreboot_ to let make clean find it and delete it. Change-Id: Ieba9c0e7ca3d2afec311d64159b22746ba5825c4 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2029 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-08-30AMD S3: The offset of the nv storage depends on config.hZheng Bao
Change-Id: Ic8410fb706dce677c7218d19030d84b64cda7b7f Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1485 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-05AMD S3: Remove the hardcoded volatile positionzbao
Change-Id: I4bcf3f3435f0ba487955d14ed1b010fd94b9f625 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1408 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-07-14AGESA F15 wrapper for Hudson.zbao
Hudson code has been integrated from CIMx to AGESA. This patch is about the wrapper. Change-Id: I63d951982140b82a3a77a97eb3d55fc75fc0caa3 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1157 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-03Fix AMD S3 block generator on CygwinPatrick Georgi
awk on Cygwin created the UTF-8 value for the 0xff code point, which makes it two bytes wide. This broke the build. Change-Id: I4937ae7ce1136ba7a76d05b42f9dd2771203175d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1164 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-04-19Do not produce temp s3.rom if the board doesn't need it.zbao
S3.rom is useless for all the other boards which don't use flash to save sleep/wakeup settings. AGESA-based boards other than persimmon haven't been validated the S3 resume. They don't need S3.rom yet. Change-Id: I12693e9556ca6f8e0d80b2ab2dca5c85bdb97685 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/902 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-17More portable s3 scratch space creationPatrick Georgi
echo -n isn't portable. echo -e isn't portable. that bash loop isn't portable. So let's try something else. Change-Id: Ie73aa1c09d90c11a5c4952a332d4c2058390b5db Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/889 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-12Add Southbridge support for S3.zbao
1. Add some CIMX call for S3. 2. Detect sleep type. Change-Id: I62888e8d8a03987ca88f5c935fa660f6b49a4fe9 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/621 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-29AMD southbridge: remove sp5100Kyösti Mälkki
Southbridge SP5100 support was compiled with SB700 code, but static device info structure would use sp5100/chip.h. To solve this drop support for separate chip sp5100 and adjust the relevant Kconfig options. Removes chip directory: src/southbridge/amd/sp5100/ Rename Kconfig option from: SOUTHBRIDGE_AMD_SP5100 to: SOUTHBRIDGE_AMD_SUBTYPE_SP5100 Change-Id: I873c6ad3624ee69165da6ab7287dfb7e006ee8e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/679 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapperKerry Sheh
Change-Id: If924b7eb176e7d3d82fa394929b653b1ced3a743 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/561 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-12-06Fix AMD 8132 and 8151 southbridge buildsKyösti Mälkki
Untested, changes ramstage build for boards: supermicro/h8qme_fam10 amd/serengeti_cheetah amd/serengeti_cheetah_fam10 AMD 8132 was not built for any mainboard due to a typo. AMD Serengeti Cheetah: Chip 8151 is referenced in devicetree.cb but was not built. AMD Serengeti Cheetah Family10: There are indications the board has 8151, but it is not listed in the devicetree.cb. The 8151 chip is not added in the build. Change-Id: I03acdfcc3f3440bd32e81a9a696159903bbbcb50 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/471 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-07AMD F14 southbridge updateKerry She
This change adds the southbridge related code to support the update of the AMD Family14 cpus to the rec C0 level. Some of the changes reside in mainboard folders but they reference changed files in the southbridge folder so they are included herein. Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/135 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-28Addition of Family12/SB900 wrapper codeefdesign98
This change adds the wrapper code for the AMD Family12 cpus and the AMD Hudson-2 (SB900) southbridge to the cpu, northbridge and southbridge folders respectively. Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/53 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-22Rename {CPU|NB|SB}/amd/*_wrapper foldersefdesign98
This change renames the cpu/amd/agesa_wrapper, northbridge/ amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and simplify the folder names. There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to append "ull" to a trio of 64-bit hexadecimal constants to allow abuild to run successfully. Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/51 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-03-28Add the SR5650 & SP5100 to the Kconfig and Makefile.incZheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14 This code provides southbridge initialization for SB800 south bridges. It ↵Frank Vibrans
is dependent on the AMD CIMx/SB800 code. Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-20This sb800 code is derived from sb700.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-18remove the code which is not ready to release.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01Add AMD SB800 southbridge support via cimx_wrapper.Kerry She
Signed-off-by: Kerry She <Kerry.she@amd.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16Add entries of RS780, SB700, Mahogany, Mahogany_fam10 into theZheng Bao
Makefile and Kconfig. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5222 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25Various Kconfig and Makefile.inc fixes and cosmetics.Uwe Hermann
- Whitespace fixes, remove trailing whitespace, use TABs for identation (except in Kconfig "help" lines, which start with one TAB and two spaces as per Linux kernel style) - Kconfig: Standardize on 'bool' (not 'boolean'). - s/lar/cbfs/ in one Kconfig help string. - Reword various Kconfig menu entries for a more usable and consistent menu. - Fix incorrect comment of NO_RUN in devices/Kconfig. - superio/serverengines/Kconfig: Incorrect config name. - superio/Makefile.inc: s/serverengine/serverengines/. - superio/intel/Kconfig: s/SUPERIO_FINTEK_I3100/SUPERIO_INTEL_I3100/. - mainboard/via/vt8454c/Kconfig: Fix copy-paste error in help string. - mainboard/via/epia-n/Kconfig: Fix "bool" menu text. - console/Kconfig: Don't mention defaults in the menu string, kconfig already displays them anyway. - Kill "Drivers" menu for now, it only confuses users as long as it's emtpy. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12This now builds. Ronald G. Minnich
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12Kconfig!Patrick Georgi
Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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