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2024-01-31device/device.h: Rename busses for clarityArthur Heymans
This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-31include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard
Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-30soc/intel: Unify the definition of TCO registersMarek Maslanka
Move the definition of the TCO registers used in most boards to a separate file and use it consistently. Do not unify TCO for older incompatible platforms. BUG=b:314260167 TEST=none Change-Id: Id64a635d106cea879ab08aa7beca101de14b1ee6 Signed-off-by: Marek Maslanka <mmaslanka@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-01-29device/device.h: Drop multiple linksArthur Heymans
Multiple links are unused throughout the tree and make the code more confusing as an iteration over all busses is needed to get downstream devices. This also not done consistently e.g. the allocator does not care about multiple links on busses. A better way of dealing multiple links below a device is to feature dummy devices with each their respective bus. This drops the sconfig capability to declare the same device multiple times which was previously used to declare multiple links. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b Reviewed-on: https://review.coreboot.org/c/coreboot/+/78328 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jincheng Li <jincheng.li@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-29soc/intel/xeon_sp/spr: Create CXL ACPI resources only forShuo Liu
CXL IIO stacks When an IIO stack is connected with CXL cards, its bus range will be divided by a PCI host bridge object and a CXL host bridge object, otherwise, all its range will be owned by the PCI host bridge object. Accordingly, CXL ACPI resources should be only created when the IIO stack is connected with a CXL card. TEST=intel/archercity CRB Change-Id: I6c1b1343991bc73d90a433d959f6618bbf59532f Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80087 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-29soc/amd/stoney: Match ACPI with resource allocationNico Huber
Currently resource allocation starts top down from the default value 0xfe000000. This does not match what ACPI reports, so adapt CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT to reflect that. Change-Id: I32d08ffd5bbd856b17f7ca2775c5923957d92c85 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-29device: Add a helper function to add a downstream busArthur Heymans
Adding downstream busses at runtime is a common pattern so add a helper function. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic898189b92997b93304fcbf47c73e2bb5ec09023 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-28soc/amd/*/acpi: drop CRAT TODOFelix Held
The CRAT (Component Resource Attribute Table) isn't used on the APUs from Renoir on and has also been marked as deprecated in version 6.5 of the ACPI specification. So remove the 'TODO: look into adding CRAT' comment from all SoCs from Renoir/Cezanne on. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3ea1e3678608b0ace2a1ff7fc104594e90c91476 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80227 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27soc/amd: move acpi_add_fsp_tables implementation to common FSP codeFelix Held
Since the acpi_add_fsp_tables implementation is identical for all SoCs, factor it out and move it to the common AMD FSP code. Also guard the acpi_add_fsp_tables call in soc_acpi_write_tables with if (CONFIG(PLATFORM_USES_FSP2_0)) to properly handle the FSP dependency. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8917a346f586e77b3b3278c73aed8cf61f3c9e6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80225 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27soc/amd: factor out acpi_add_fsp_tablesFelix Held
Factor out acpi_add_fsp_tables from the soc_acpi_write_tables function and move the remaining parts of the soc_acpi_write_tables function to the SoC's acpi.c. This aligns the other family 17h/19h SoCs more with Genoa and only leaves the FSP-specific code in agesa_acpi.c which will be made common in a following patch. I decided against also renaming agesa_acpi.c to acpi_fsp.c, since that would have made the diff less readable and the files get deleted in a following patch anyway. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia87ac0e77c5e673e694703b85a4bab85a34b980e Reviewed-on: https://review.coreboot.org/c/coreboot/+/80224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-27soc/amd/picasso: factor out CRAT table generationFelix Held
Factor out the code to add the CRAT ACPI table into a separate file and add the acpi_add_crat_table function that can then be called from soc_acpi_write_tables to better isolate all code specific to the CRAT table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4a7853748512811d3d4e124224fcd459e527522c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80223 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27soc/amd: use common ACPI_SCI_IRQ definitionFelix Held
ACPI_SCI_IRQ is defined as 9 for all AMD SoCs, so move the definition to the common amdblocks/acpi.h. Since all but Stoneyridge's soc/acpi.h are now empty, delete those files too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8210c98dc4cf2c6001d5273d132053278ff7fea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80222 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27soc/amd/*/acpi: use common soc_acpi_write_tables prototypeFelix Held
Since the definition is the same for all SoCs, move it to the common amdblock/acpi.h header. Since the Stoneyridge northbridge.c file also includes this prototype, remove the static attribute of the function there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib9aa215f2b4ba58f43fed2c751d989f1719e0a17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80221 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27soc/amd/common/include/acpi: add missing device/device.h includeFelix Held
The southbridge_write_acpi_tables function uses a struct device type parameter, but device/device.h that provides the definition wasn't included. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5245fa132ec9b84bbc483a31788bcd6fac0736e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-27soc/amd/common/fsp: use expected types for add_agesa_fsp_acpi_tableFelix Held
add_agesa_fsp_acpi_table should use the same type for the 'current' parameter and return value as the calling soc_acpi_write_tables does. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie9f770b1d847ea28e4dbd96298a723d794b91a02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-27soc/amd: use expected function signature for soc_acpi_write_tablesFelix Held
A pointer to soc_acpi_write_tables gets assigned to the write_acpi_tables element of the device_operations struct, so make sure that the function has the expected function signature which in this case means using unsigned long as type for both the 'current' parameter and the return value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iee45badb904fa20c6db146edbc00c40ca09361d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80218 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27soc/amd: rename agesa_write_acpi_tables to soc_acpi_write_tablesFelix Held
It's not the AGESA code that generates most of the ACPI tables, so rename the function. This also aligns the other SoCs more with Genoa. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b2e6c4cb7139c8bde01b4440ab2e923a1086827 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80217 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-26soc/intel/common: Add lunarlake device IDsAppukuttan V K
Added Lunar Lake device IDs the device specific functions Reference: Lunar Lake External Design Specification Volume 1 (734362) Change-Id: Id31d567287b9921d60909b1eb617c7cfaf6672c9 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2024-01-26vc/amd: move verstage on PSP files to new psp_verstage folderFelix Held
Move the verstage on PSP files in vendorcode from the fsp subdirectory to a new psp_verstage subdirectory, since those files aren't specific to the case of the FSP being used for the silicon initialization. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic47f8b18bc515600add7838f4c7afcb4fff7c004 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80209 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-01-26soc/amd: factor out common acpi_add_ivrs_table implementationFelix Held
Instead of open-coding this functionality in all AMD SoCs, factor it out into a common implementation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb65c398b747e70ec67107e0a1d4bd6551501347 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80208 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-01-26soc/intel/commonlake: Re-add SATA to soc_api_name() listMatt DeVillier
Now that we've added an ACPI device for SATA, add the name back to the soc_acpi_name() list so the PEPD LPI constraint list generates a valid reference to the SATA device. TEST=build/boot Win11 on google/puff (kaisa). Change-Id: I134058f5ef78f419dc5538452614125ad44bf29d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80059 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-26soc/intel/common/block/sata: Add ACPI stub for SATA deviceMatt DeVillier
Add an ACPI stub containing the SATA device in proper scope, along with the device status, so that there exists a device to be referenced from the PEPD LPI constraint list. Fixes a Windows BSOD INTERNAL_POWER_ERROR on devices with enabled SATA ports. TEST=build/boot Win11 on google/puff (kaisa). Change-Id: I951c62d09609ed73079fe97ea9ce49fdee333272 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-26Revert "soc/intel/cannonlake: Add missing min sleep state for thermal device"Matt DeVillier
This reverts commit d64b66ba267a217d0b6716309019c36c8cfdf8c2: "soc/intel/cannonlake: Add missing min sleep state for thermal device." Reverting because commit e00523aae2ea ("soc/intel/cannonlake: Drop entries from soc_acpi_name()") removed the ACPI device name for the PCH thermal device, since there is no ACPI device defined for it. Removing the name without removing the minimum sleep state caused an invalid LPI entry to be created, which caused a Windows BSOD: INTERNAL_POWER_ERROR. TEST=build/boot Win11 on google/puff (wyvern). Change-Id: I2dfe76d5f72cde7742cee338fa24eaafb84c4604 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80057 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-25soc/amd/genoa_poc: rely less on boot state hooksFelix Held
Call setup_opensil, opensil_entry, and fch_init in the right order from the init method of the SoC's chip operations. This brings this SoC both more in line with the other SoCs and avoids using boot state hooks for this which also makes the sequence in which those functions are called easier to understand. Previously the boot states were used so that setup_opensil was run before configure_mpio which was run before opensil_entry(SIL_TP1), but since configure_mpio is called from setup_opensil, this is no longer necessary. TEST=Onyx still boots to the payload and the MPIO configuration reported from the openSIL code is still the same. The FCH init code now runs before the resource allocation like on the AMD SoCs that rely on FSP. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic752635da5eaa9e333cfb927836f0d260d2ac049 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79985 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-25soc/amd/common: Fix typoVarshit Pandya
Change-Id: Ida6e87908ae6996529057c8df12dbe046ee54b98 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-24soc/*: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6f502b97864fd7782e514ee2daa902d2081633a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80074 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-24soc/intel: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib479b93b7d0b2e790d0495b6a6b4b4298a515d9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80073 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24soc/amd/*: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie449267fe4fdd75110f577e1b9f748cd06140950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-24soc/intel/xeon_sp/chip_common: Improve the domain IDPatrick Rudolph
Use a union to access the PCI domain ID. This will become handy in the following commits to gather meta-data from the domain ID. Change-Id: I5c371961768410167a571358f6f366847a259eb6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80099 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24soc/intel/cannonlake: Report correct latencies for C statesNico Huber
The C_STATE_LATENCY_FROM_LAT_REG() macro uses values that we also write into the respective MSRs in configure_c_states(). Match the indices to those used there. Change-Id: Ie01a53d6f06bc02a53d95e390e16e9963f4c65ee Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-01-22soc/intel/xeon_sp: Add IIO resources via SSDTArthur Heymans
There is no need to inject this code in DSDT. Just generating a _CRS Name in SSDT containing a resource template works well and reduces the need to sync up on names being used to return _CRS names in DSDT. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I691d7497dceb89619652e5523a29ea30a7b0fab8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-22soc/intel/xeon_sp: Scan and allocate resources on all stacksArthur Heymans
The code can now deal with stacks that have no resources so just hook them all up. Intel XEON-SP FSP reports all report the state of its stacks, which comprise of PCI root bridges and their respective resources, like PCI busses, IO and MEM resources, via HOB. Parsing all of those into native coreboot structures makes it possible to handle those in a more native fashion like use PCI drivers, native helper functions, ... As opposed parsing those structures again out of the HOB each time. This makes code reuse across the tree more feasible. An additional advantage is that Linux does not need to redo resource allocation since the one done by coreboot will be valid, which potentially decreases boot time. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: Id72c6e4499e99df3b7ca821ab2893cbcc869dbcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/78332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-22soc/intel/xeon_sp: Fix devicetree walking upPatrick Rudolph
Connect the PCI domain to the bus to allow walking the devicetree up. This is required to figure out which PCI domain a device belongs to. Change-Id: I8cc50cabf7ad540c52498e1ffe7f9246550ed87b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-01-22soc/intel/cmn/block/pmc: Fix prev_sleep_state string name mappingAnil Kumar
commit d078ef2152052b5ce8686249dcd05ebd50010889 ("soc/intel/cmn/block/pmc: Add previous sleep state strings in log") used SLP_TYP numbers to map ACPI sleep state value. This incorrectly printed wrong string for prev_sleep_state during S5. ex: after a cold reset the previous sleep state printed was [DEBUG] prev_sleep_state 5 (S3) This patch corrects this by using ACPI sleep state numbers for mapping the prev_sleep_state values. TEST=test the logs on google/rex board after cold reset [DEBUG] prev_sleep_state 5 (S5) Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I9bcdacc4d01a8d827a6abdf9af2b9e5d686ed847 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80144 Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-22soc/intel/meteorlake: Fix system hang by enabling SMI handlingKane Chen
Issue: System hang occurred due to unhandled SPI synchronous SMI, triggered by LOCK_ENABLE bit and WPD assertion. Solution: Enabled SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE configuration to allow the system to handle and clear SPI synchronous SMI. BUG=b:306267652 TEST=Cold reboot test on 20 google/screebo by ODM, all passed w/o hang. Change-Id: Ie1f096f8eda4adcf1627e44afa517b02adddad76 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-20soc/amd/*/chip: factor out FSP-S callFelix Held
Move the call into the FSP code to a file in the common AMD FSP code to isolate the FSP-specific parts of the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic8236db7ac80275a65020b7e7a9acce8314c831c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-20soc/amd: factor out non-CAR romstage to common codeFelix Held
Since the romstage code is very similar between all AMD non-CAR SoCs, factor out a common romstage implementation. All SoCs that select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE call fill_chipset_state, so this Kconfig option can be used to determine whether to make that call. In the FSP case, amd_fsp_early_init gets called, while in the case of an implementation that doesn't rely on an FSP to do the initialization, cbmem_initialize_empty gets called to set up CBMEM which otherwise would be done inside the FSP driver code. Since only some SoCs call fch_disable_legacy_dma_io again in romstage right after amd_fsp_early_init, introduce the new SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP Kconfig option, so that the SoCs can specify if this call is needed or not. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4a0695714ba08b13a58b12a490da50cb7f5a1ca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80083 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-01-20soc/amd/*/romstage: factor out FSP-M callFelix Held
Move the call into the FSP code to a file in the common AMD FSP code to isolate the FSP-specific parts of the code and a preparation to make the romstage of all non-CAR AMD SoCs common. Without isolating the call into the FSP-M code, building the common romstage would fail for genoa_poc due to fsp/api.h not being in the include path. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I30cf1bee2ec1a507dc8e61eaf44067663e2505ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/80002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-20soc/amd/phoenix/Makefile: conditionally add fsp_[m,s]_params.cFelix Held
fsp_m_params.c and fsp_s_params.c only contain FSP-specific code, so only add those to the build if the SOC_AMD_PHOENIX_FSP Kconfig option is selected. Other files have FSP-specific parts too, but those will be reworked in future patches. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ife38ca6a548d7c3c2e765d9c9f30e0a4057bb373 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79984 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-20soc/amd/phoenix/Kconfig: factor out FSP-specific optionsFelix Held
Split the SOC_AMD_PHOENIX Kconfig option into SOC_AMD_PHOENIX_BASE that selects the non-FSP-specific options and SOC_AMD_PHOENIX_FSP that selects both SOC_AMD_PHOENIX_BASE and the FSP-specific options. This will help to separate the FSP-specific from the FSP-agnostic code. The mainboards using this SoC now select SOC_AMD_PHOENIX_FSP instead of SOC_AMD_PHOENIX. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5e95fbfd9d16930ba3e6cc497557d61adba5a6fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/79983 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-19device/Kconfig: Move Intel/ACPI/USB4 specific Kconfig optionsArthur Heymans
This options should not be visible on !Intel, !ACPI and !USB4. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ia515d52baead9e151533278c33fda9436ee56168 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79669 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-18soc/intel/braswell: Use {read,write}32p()Elyes Haouas
Change-Id: I00894565efc405a47348236ad7df50071a843487 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77972 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-17soc/intel/elkhartlake: Drop redundant PcieRpEnableNico Huber
The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infracture instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: I11c3c45eae0e1451d5c54c17b7e60300dedda8fa Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-17tree: More use accessor functions for struct region fieldsNico Huber
Always use the high-level API region_offset() and region_sz() functions. This excludes the internal `region.c` code as well as unit tests. FIT payload support was also skipped, as it seems it never tried to use the API and would need a bigger overhaul. Change-Id: I18f1e37a06783aecde9024c15876b67bfeed70ee Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-01-17soc/mediatek/mt8188: Enable EARLY_MMU_INITYidi Lin
The boot time is improved by 65ms. (762ms -> 697ms) BUG=b:320381143 TEST=check timestamps in cbmem Change-Id: I74191ab8cbefa08b7e296312645ea40b46fabf77 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79991 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-17soc/mediatek: Add EARLY_MMU_INIT kconfig optionYidi Lin
Accessing RAM before mmu initialized is time consuming. During mmu initialization, `mmu_init()` and `mmu_config_range()` write logs to the console buffer and contribue the extra boot time. This patch adds a kconfig option to move `mtk_mmu_init()` to `bootblock_soc_early_init()`. When `EARLY_MMU_INIT` is enabled, mmu is initialized before `console_init()` ready. So `mmu_init()` and `mmu_config_range()` won't write logs to the console buffer and save the boot time. It saves about 65ms on Geralt with EARLY_MMU_INIT enabled. Before: 0:1st timestamp 239,841 (0) 11:start of bootblock 239,920 (79) 12:end of bootblock 323,191 (83,271) After: 0:1st timestamp 239,804 (0) 11:start of bootblock 239,884 (80) 12:end of bootblock 258,846 (18,962) BUG=b:320381143 TEST=check timestamps in cbmem Change-Id: I7f4c3c6c836f7276119698c6de362794cf4222a6 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-01-17Reland "Kconfig: Bring HEAP_SIZE to a common, large value"Patrick Georgi
This reverts commit acbc4912375085a099c2427def464d6e481f2a90. Reason for revert: CB:79525 fixes the issue that led to the revert by not maintaining the heap in the SMM-stored copy of ramstage at all. Change-Id: I3c8ef785486d275c9341859d34fce12253bd2bb9 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80023 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-16soc/intel/apollolake: Fix PCI memory resource allocReto Buerki
There is a mismatch in how PCI memory resources are allocated on Apollo Lake with the current configuration. While the ACPI code expects resources to be below PCR_BASE_ADDRESS (i.e. PMAX), the coreboot C code allocates them above, leading to the following error messages on Linux: pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] pci_bus 0000:00: root bus resource [mem 0x80000000-0xd0000000 window] pci_bus 0000:00: root bus resource [mem 0x280000000-0x7fffffffff window] pci 0000:00:13.1: can't claim BAR 14 [mem 0xdeb00000-0xdebfffff]: no compatible bridge window pci 0000:00:13.1: can't claim BAR 15 [mem 0xdec00000-0xdecfffff 64bit pref]: no compatible bridge window pci 0000:00:13.1: BAR 14: assigned [mem 0x80000000-0x800fffff] pci 0000:00:13.1: BAR 15: assigned [mem 0x281300000-0x2813fffff 64bit pref] Tested on up/squared with Linux kernel version 6.1.0. Fix this by setting the DOMAIN_RESOURCE_32BIT_LIMIT to PCR_BASE_ADDRESS, and by moving the UART base address into the expected range. Thanks to Nico Huber for the help in writing this patch. Change-Id: I3a805beb47ab4d19cf8dfce0942485e7982861b1 Signed-off-by: Reto Buerki <reet@codelabs.ch> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79957 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-16device: Add support for multiple PCI segment groupsFelix Held
Add initial support for multiple PCI segment groups. Instead of modifying secondary in the bus struct introduce a new segment_group struct element and keep existing common code. Since all platforms currently only use 1 segment this is not a functional change. On platforms that support more than 1 segment the segment has to be set when creating the PCI domain. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-01-15soc/cavium/cn81xx/Kconfig: specify ECAM_MMCONF_BUS_NUMBERFelix Held
The Cavium CN81xx SoC selects ECAM_MMCONF_SUPPORT, but doesn't set a value for ECAM_MMCONF_BUS_NUMBER which results in it defaulting to 0 which is wrong. Both the Cavium CN8100 SFF EVB and the OpenCellular Elgon (GBCv2) mainboard specify 32 PCI buses in their Linux devicetree files, so set the SoC's ECAM_MMCONF_BUS_NUMBER Kconfig option to 32 to match this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: Ic98381e2cc597cf23af249c71911545692e40f64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79931 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-15soc/intel/xeon_sp: Redesign resource allocationArthur Heymans
The xeon_sp code worked around the coreboot allocator rather than using it. Now the allocator is able to deal with the multiple IIOs so this is not necessary anymore. Instead do the following: - Parse the FSP HOB information about IIO into coreboot PCI domains - Use existing scan_bus and read_resource - Handle IOAT stacks with multiple domains in soc-specific code TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-15src/soc/amd/glinda: Update the PCIE MMCONFIG base address and sizeAnand Vaikar
The PCIE MMCONFIG base address value and size is updated correctly to access the PCIE config space registers. TEST=Verified that PCIE enumeration takes place in boot log and config space registers are accessible. Change-Id: Ifa8377df7a2973a88d414c217b5ed114c8ae5cc3 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79832 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-15soc/amd/glinda/include/data_fabric: update IOHUBS0 fabric id Anand Vaikar
The IOHUBS0 is a data fabric component which has a fabric id value specific to SOC. Updated the fabric id for glinda SOC. TEST=Verified that fabric ID is programmed correctly in boot logs. Change-Id: I91ea7d7e7d9b247cf479471df287ba8c96b83d75 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79830 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-13soc/amd/common/data_fabric/domain: write _SEG method in SSDTFelix Held
As a preparation for the multi PCI segment group support, use acpigen_write_BBN to generate the _SEG method that returns the segment group number of the PCI root. Until the multi PCI segment group support is enabled in coreboot, it will always return 0. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2a812dcc564c5319385e9ad482d29b2984a71b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79924 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-12soc/intel/xeon_sp: Allocate resources above 4GArthur Heymans
This makes sure that prefetchable mem64 memory gets allocated above 4G which allows non prefetchable resources to be allocated in the tight window below 4G. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I27d4f9ce91c12ed4ab3b2f18f2a92b742115d275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79058 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-11soc/amd/stoneyridge/acpi: use common AMD MADT codeFelix Held
Now that Stoneyridge also reports the GNB IOAPIC on the domain and with the IOMMU_IOAPIC_IDX resource index the common AMD MADT code expects, we ca switch over to using this common code on Stoneyridge too. TEST=The resulting MADT doesn't change on Careena Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If4ce71a47827e144c4d4991152101650904901f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-11soc/amd/stoneyridge/northbridge: report GNB IOAPIC in domainFelix Held
Move the GNB IOAPIC resource from being reported in the GNB PCI device to the domain and use IOMMU_IOAPIC_IDX as resource index, so that the common AMD MADT code will be able to find the resource. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If6e9aaf4a3fa2c5b0266fd9fb8254285f8555317 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-11soc/amd/stoneyridge/acpi: drop wrong comment in MADT codeFelix Held
The IOAPIC structure that this function created is for the IOAPIC in the GNB and not the one in the FCH which is called Kern in this SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6eec02578f2b2e8b8c10dad7eeecff961ef45e76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79883 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-11soc/amd: move IOMMU_IOAPIC_IDX define to amdblocks/ioapic.hFelix Held
Move the IOMMU_IOAPIC_IDX define from amdblocks/data_fabric.h to amdblocks/ioapic.h which is both a more logical place for it to be and this is also a preparation to use the common AMD MADT code for the Stoneyridge SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaa20e802cf5ed93f0d05842abb1aea0d43b1cac4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-11soc/intel/meteorlake: Enable FSP logo support by defaultSubrata Banik
Enables FSP logo support for Meteor Lake SoC config, covering both Intel Meteor Lake RVP and ChromeOS devices. Applies HAVE_FSP_LOGO_SUPPORT configuration only for platforms with native FSP support. Ensures successful builds and boots for google/rex and intel/mtlrvp. BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/rex and intel/mtlrvp Change-Id: Ic99bfdc2d33db48bdb015525981c1ef76df8203b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79859 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-01-11soc/amd/common/acpi: factor out common MADT codeFelix Held
The acpi_fill_madt implementation from the Genoa PoC also works for the other AMD SoCs that select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN, so factor out this function to the common AMD ACPI code and change those other SoCs to use the new common functionality instead of having their own implementations. The old code on the single-domain SoCs used the GNB_IO_APIC_ADDR base address to create the MADT entry for the additional IOAPIC in the root complex. The new code iterates over all domains and looks for a resource with the IOMMU_IOAPIC_IDX index in each domain and if it finds it, it creates an MADT entry for that IOAPIC. This resource is created earlier in the boot process when the non-PCI resources are read from the IOHC registers and reported to the allocator. TEST=The resulting MADT doesn't change on Mandolin Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4cc0d3f30b4e6ba29542dcfde84ccac90820d258 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79861 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-10soc/amd: use apm_get_apmc() in APMC SMI handlerFelix Held
Instead of open-coding this functionality, call the apm_get_apmc() helper function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iac6b614d900e51d91a0c155116a5edc29775ea99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-10mb/google/cherry: Use common mtk_display_init()Yidi Lin
TEST=check FW screen on dojo Change-Id: Ie870899226588ac2a2e80f77e434455f4913d387 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-01-10mb/google/corsola: Use common mtk_display_init()Yidi Lin
TEST=check FW screen on Steelix, Tentacruel and Starmie Change-Id: I429218d59389a6ab86b522dd597c07fa5b8ea821 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79777 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-10soc/mediatek: Add common implementation to configure displayYidi Lin
The sequences of configure_display() are similar on MediaTek platforms. The sequences usually involve following steps: 1. Setup mtcmos for display hardware block. - mtcmos_display_power_on() - mtcmos_protect_display_bus() 2. Configure backlight pins 3. Power on the panel - It also powers on the bridge in MIPI DSI to eDP case. 4. General initialization for DDP(display data path) 5. Initialize eDP/MIPI DSI accordingly, - For eDP path, it calls mtk_edp_init() to get edid from the panel and initializes eDP driver. - For MIPI DSI path, the edid is retrieved either from the bridge or from CBFS (the serializable data), and then initializes DSI driver. 6. Set framebuffer bits per pixel 7. Setup DDP mode 8. Setup panel orientation This patch extracts geralt/display.c to mediatek/common/display.c and refactors `struct panel_description` to generalize the display init sequences. configure_display() is also renamed to mtk_display_init(). TEST=check FW screen on geralt. Change-Id: I403bba8a826de5f3fb2ea96a5403725ff194164f Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79776 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-10soc/amd/glinda: Increase maximum CPU threads to 24Anand Vaikar
glinda SOC has 24 maximum CPU threads as per PPR documentation(#57254). TEST=Boot logs print the CPU initialization happens for 24 threads. Change-Id: Id48a5c62d6156c046daffd2648aeebeee380bd88 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-09soc/nvidia: Put static keyword at the beginning of declarationsFelix Singer
In order to comply with the more recent style of declarations, put the static keyword at the beginning. Fixes following GCC error when the related flag is set: error: 'static' is not at beginning of declaration [-Werror=old-style-declaration] Change-Id: Ida683319f7a0c428a9e4808821075abdd9fcb504 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79856 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-01-09soc/intel/mtl: Override the `SOC_PHYSICAL_ADDRESS_WIDTH` as integerSubrata Banik
This patch enforces consistent override handling for integer `SOC_PHYSICAL_ADDRESS_WIDTH` config Change-Id: Ib5bdfdb8c2689803c9d3c2bfd353609edae91ab3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-01-08arch/x86: introduce HAVE_CONFIGURABLE_APMC_SMI_PORTFelix Held
Introduce the HAVE_CONFIGURABLE_APMC_SMI_PORT Kconfig option that when not selected will result in a default implementation of pm_acpi_smi_cmd_port to be included in the build that returns APM_CNT. SoCs that provide their own pm_acpi_smi_cmd_port implementation, need to select this Kconfig option. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaceb61b0f2a630d7afe2e0780b6a2a9806ea62f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-06soc/rockchip/rk3399/mipi: Remove space before semicolonElyes Haouas
Change-Id: I7e02173c296689ef3143a1079658006ec91c4dc2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77156 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-05soc/amd/picasso/Kconfig: select SOC_AMD_COMMON_BLOCK_EMMC_SKIP_POWEROFFFelix Held
Commit 850b6c6254ab ("soc/amd/picasso: add eMMC MMIO device to devicetree") broke both S3 resume on Morphius SKUs that use an NVMe SSD instead of an eMMC and boot on the currently out-of-tree ASRock X370 Killer SLI board. In the latter case, commenting out the power_off_aoac_device call inside the emmc_enable function fixed things. TEST=This fixes S3 resume on Morphius with NVMe SSD and an equivalent change discussed in the patch mentioned above that caused the regression also fixed boot on the ASRock board. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Change-Id: Id976734c64efe7e0c3d8b073c8009849be291241 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-05soc/amd/common/emmc: add Kconfig option to skip powering off eMMCFelix Held
Add a Kconfig option to skip powering off the eMMC controller via the AOAC block in the case where the eMMC controller is disabled in the devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0dbe819222972d9bf0789671b031ad83648e8917 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79825 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-04soc/amd/picasso/acpi: move SoC-common code from dsdt.asl to soc.aslFelix Held
To avoid code duplication and to also bring the mainboards using the Picasso SoC more in line with Cezanne and newer, factor out the SoC- specific code from the mainboard's dsdt.asl files to the SoC's soc.asl. TEST=Timeless builds result in identical images for Bilby, Mandolin, and Zork/Morphius Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id4ed3a3d3cb55c8b3b474c66a7c1700e24fe908e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-02soc/intel/meteorlake: Enable SSE2 accelerated RSA sign. verificationJeremy Compostella
Enabling SSE2 accelerated RSA signature verification saves 4.7 ms of boot time. | modpow() function call | original | SSE2 Algorithm 2 | |----------------------------+----------+------------------| | coreboot/verstage - step 1 | 6.644 | 3.042 | | coreboot/verstage - step 2 | 1.891 | 0.757 | |----------------------------+----------+------------------| | Total (ms) | 8.535 | 3.799 | BUG=b:312709384 TEST=modular exponentiation is more than twice faster on rex0 Change-Id: I382e62a765dbf2027c4ac54d6eb19a9542a8c302 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79291 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26Update vboot submodule to upstream mainJulius Werner
Updating from commit id c0cb4bfa: 2023-12-08 signer: sign_android_image.sh should die when image repacking fails to commit id 7c3b60bb: 2023-10-13 firmware/2lib: Use SSE2 to speed-up Montgomery multiplication This brings in 3 new commits: 7c3b60bb firmware/2lib: Use SSE2 to speed-up Montgomery multiplication 8bb2f369 firmware: 2load_kernel: Set data_key allow_hwcrypto flag 2b183b58 vboot_reference: open drive rdonly when getting details 6ee22049 sign_official_build: switch from dgst to pkeyutl da69cf46 Makefile: Add support for make 4.3 Also update the implementations of the vb2ex_hwcrypto_modexp() callback to match the API changes made in vboot. Change-Id: Ia6e535f4e49045e24ab005ccd7dcbbcf250f96ac Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-26soc/amd/stoneyridge/BiosCallOuts: add missing curly bracesFelix Held
When an if block has curly braces, the corresponding else block should also have curly braces. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie1979873142469b1482097f9b4db487541a1b7a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-12-26soc/amd/common/pi/agesawrapper: use is_dev_enabled(DEV_PTR())Felix Held
Since we have chipset devicetrees for all SoCs that include this code in the build, we can use the DEV_PTR macro instead of using pcidev_path_on_root to get the device struct pointer. We can also use the is_dev_enabled function instead of checking the value of the enabled element of the device struct directly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5dcd92399e2d3f304352f2170dd3ef8761e86541 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79672 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26soc/amd/stoneyridge: use is_dev_enabled(DEV_PTR())Felix Held
Since we have chipset devicetrees for both SoCs supported by the Stoneyridge code, we can use the DEV_PTR macro instead of using pcidev_path_on_root to get the device struct pointer. We can also use the is_dev_enabled function instead of checking the value of the enabled element of the device struct directly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifb787750ebc6aa2fef9d3be0e84e6afcffdc2ac1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79671 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26soc/amd/picasso/fsp_s_params: use is_dev_enabledFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5b692aaa2e3f768cc03bca71eff3ceb1a8733ad3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79670 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26soc/intel/alderlake: Make C1e configurableSean Rhodes
Make it possible to enable C1e from the devicetree by adding `c1e_enable`. C1e was disabled by ea2a38be323173075db3b13729a4006ea1fef72d for all RPL SOCs to reduce noise. This will ensure that boards that disabled it based on CPUID are unchanged. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I758621393cb39345c2ba7b19a32872e84e1c5a19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77088 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26soc/intel/xeon/spr: Enforce POR frequency settingNaresh Solanki
For RMT build, add kconfig option to enforce Plan Of Record restriction on DDR5 frequency & voltage settings. Change-Id: Ibfcaaf47fec3bd5d8a858309918b3af2f8d976e9 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-12-22soc/intel/cmn/block/smm: Clear SPI SYNC_SS before disabling WPDSubrata Banik
This patch follows the BWG recommendation (doc 729123) by clearing the SPI SYNC_SS bit before disabling the WPD bit in SPI_BIOS_CONTROL. This prevents boot hangs due to a 3-strike error. Unable to follow this guideline would result into boot hang (3-strike error). BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/rex. Change-Id: I18dbbc92554d803eea38ceb0b936a9da9191cb11 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-22soc/intel/cmn/block/pmc: Add previous sleep state strings in logMarx Wang
Previous sleep state showing in serial log is a magic number. In order to let users understand its meanings directly, add the strings to describe the modes. TEST=build, boot the device and check the logs: without this change, the log is like: [DEBUG] prev_sleep_state 0 with this change: [DEBUG] prev_sleep_state 0 (S0) Change-Id: Iabe63610d3416b3b6e823746e3ccc5116fabb17d Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78999 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-22soc/intel/meteorlake: Fix SOC_PHYSICAL_ADDRESS_WIDTH to 42Jeremy Compostella
Meteor Lake CPUs physical address size is 46 if TME is disabled, 42 if TME is enabled but Meteor Lake SoC physical address size is always 42. BUG=b:314886709 TEST=MTRR are aligned between coreboot and FSP Change-Id: Ic63c93cb15d2998e13d49a872f32d425237f528a Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79666 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-22x86: Separate CPU and SoC physical address sizeJeremy Compostella
The physical address size of the System-on-Chip (SoC) can be different from the CPU physical address size. These two different physical address sizes should be used for settings of their respective field. For instance, the physical address size related to the CPU should be used for MTRR programming while the physical address size of the SoC should be used for MMIO resource allocation. Typically, on Meteor Lake, the CPUs physical address size is 46 if TME is disabled and 42 if TME is enabled but Meteor Lake SoC physical address size is always 42. As a result, MTRRs should reflect the TME status while coreboot MMIO resource allocator should always use 42 bits. This commit introduces `SOC_PHYSICAL_ADDRESS_WIDTH' Kconfig to set the physical address size of the SoC for those SoCs. BUG=b:314886709 TEST=MTRR are aligned between coreboot and FSP Change-Id: Icb76242718581357e5c62c2465690cf489cb1375 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79665 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-22Revert "soc/intel/meteorlake: Set build time physical address reserved bits"Jeremy Compostella
This reverts commit 533efb23083afd721d4c268ce0ee8e863e13689a. BUG=b:314886709 Change-Id: Ic63c93cb15d2998e13d49a872f32d425237f528c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79664 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-20soc/amd/genoa_poc: select DEFAULT_X2APICVarshit Pandya
Allow SoC code to set LAPIC access mode to X2APIC Change-Id: I208cca35c328e1566a57aaaa8ee7809e0760261c Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-12-20soc/intel/common,mtl: Refactor BERT generation flow for crashlogPratikkumar Prajapati
With earlier flow, a chunk of CBMEM region was allocated for each SRAM e.g., PUNIT SRAM, SOC PMC SRAM and IOE PMC SRAM. Then entire SRAM content was copied to dedicated CBMEM region. Later in acpi_bert.c, the BERT table was getting created for each chunk of CBMEM. This flow was not considering creating separate entries for each region of crashlog records. It resulted in only the first entry getting decoded from each SRAM. New flow aims to fix this issue. With new flow, a simple singly linked list is created to store each region of crashlog records from all SRAMs. The crashlog data is not copied to CBMEM. The nodes are allocated dynamically and then copied to ACPI BERT table and then freed. This flow also makes the overall crashlog code much simpler. BUG=b:298234592 TEST=With this change decoding crashlog show comprehensive details, tested on REX. Change-Id: I43bb61485b77d786647900ca284b7f492f412aee Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78257 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20soc/intel/meteorlake: Add Acoustic Noise Mitigation UPDsSubrata Banik
This patch allows to override acoustic noise mitigation FSP UPDs: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRate BUG=b:312405633 TEST=Able to override the acoustic noise UPDs. Change-Id: I5295e6571121c92f363e6fd4bcb3c8335c4fedee Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79302 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-20treewide: Use show_notices target for warningsMartin Roth
This updates all warnings currently being printed under the files_added and build_complete targets to the show_notices target. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia14d790dd377f2892f047059b6d24e5b5c5ea823 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79423 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-18soc/intel/mtl: Adaptively disable 3-strike error for QS siliconSubrata Banik
This patch provides a way to mask the 3-strike error on Intel Meteor Lake SoC platform across pre-prod and prod SoC. This patch decouples MSR selection for 3-strike error disablement, ensuring compatibility across SoC types. Without the correct MSR been programmed the SoC platform is unable to disable 3-strike error. BUG=b:314883362 TEST=Disable the 3-strike on google/screebo with QS silicon. Change-Id: I5363102deea67c44c9433a3f66c92badb0d0f182 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79473 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-16vc/amd/opensil: add _POC suffix to SOC_AMD_OPENSIL_GENOAFelix Held
The openSIL code for the Genoa SoC is only a proof of concept, so change the name of the Kconfig option to include this code in the build from SOC_AMD_OPENSIL_GENOA to SOC_AMD_OPENSIL_GENOA_POC to clarify that this is code that isn't intended or ready to be productized. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If91cdaa7c324426964bba2de2109b6c38482fab8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79574 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-16soc/amd/genoa: rename to genoa_pocFelix Held
Even though this SoC is called 'Genoa', the openSIL implementation and the corresponding coreboot integration is only a proof of concept that isn't fully featured, has known limitations and bugs, and is not meant for or ready to being productized. Adding the proof of concept suffix to the name should point this out clearly enough so that no potential customer could infer that this might be a fully functional and supported implementation which it is not. Change-Id: Ia459b1e007dcfd8e8710c12e252b2f9a4ae19b72 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77894 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-16soc/amd/genoa/fch: add fch_init_acpi_portsFelix Held
Make sure that the APMC SMI command IO port is configured to what coreboot expects and enable the SMI generation for the APMC SMI command port. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie4fc259dea125a16556a01b80a3d5e6fb476044a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79531 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-15soc/amd/stoney/northbridge: Remove dead codeArthur Heymans
All the resource on the host bridge are fixed resources and therefore have the IORESOURCE_STORED flag set, so the body of this function which configures IO or MEM ranges is never reached. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I1839f030a4a365e5bc1cdaa3cf37cdf9ca382ff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79385 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-15soc/intel/cmn/cpu: Introduce API to disable signaling 3-strike eventSubrata Banik
This patch introduces a new API to disable signaling the 3-strike event on Intel Meteor Lake C0 (QS) stepping and subsequent SoCs. This is necessary because the existing event handling mechanism is incompatible with the new hardware design. Disabling the 3-strike event registration prevents the 3-strike count from increasing, which addresses bug b:314883362. This issue can potentially lead to system instability. BUG=b:314883362 TEST=disabling the 3-strike event on a Google Screebo system with QS silicon. Change-Id: I15bd5a93da34d7f2a127c21c4cd8b5952926bccf Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79472 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-15soc/amd: drop fill_fadt_extended_pm_regsFelix Held
Call fill_fadt_extended_pm_io directly from the SoC's acpi_fill_fadt functions instead of calling fill_fadt_extended_pm_regs that only calls fill_fadt_extended_pm_io. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I442bc2801cf74c1d836d3b0d88f281bceb5122b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79529 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-15soc/amd/genoa: Hook up BERTArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ie21bf8d436de19c23ae2176bf8d061564cd5b9cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/76535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-15soc/amd/genoa: Hook up IVRS generationFelix Held
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I0a6eaf43ab6da4bb4a0cc0bbefb5b75c206348f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-12-15soc/amd/genoa: configure FCH IRQ mappingFelix Held
Add the code to configure the FCH IRQ mapping registers and provide the IRQ name strings for each FCH IRQ mapping configuration register. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I282ae35ebc4d7754121ce4544b782e3cbe7e2256 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>