summaryrefslogtreecommitdiff
path: root/src/soc
AgeCommit message (Collapse)Author
2016-03-10soc/intel/apollolake: Add chip initializationAndrey Petrov
Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-10soc/apollolake: Enable all CPU cores using the parallel MP libRavi Sarawadi
This is the minimal setup needed to get all CPU cores enabled. That includes sending an IPI to APs and setting up MTRRs. Microcode updates are not performed for two reasons: * CSE (Converged Security Engine) upgrades the microcode before releasing reset * Microcode update files are not available at this point in time Change-Id: Ia1115983696b0906fb4cefcbe1bbe4fc100751ca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13910 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-03-09drivers/intel/fsp2_0: remove struct resource usageAaron Durbin
There's no need to use a struct resource type for fsp_find_reserved_memory(). struct resource is mainly associated with a device and that memory is added to cbmem after memory init. Other uses ins FSP 2.0 just use struct range_entry. Use that instead for consistency. Change-Id: Id7d39da1c2e23f97cdaafd7f5d281cefa6fee543 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13960 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-09soc/intel/apollolake: correct comment to reference top of CARAaron Durbin
The memory provided to MemoryInit() for its own usage is at the top of the CAR region. Change-Id: I8685b5ab138182e24123b14cac6f7b32e5e784d2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13957 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-08x86 chipsets: utilize x86_setup_mtrrs_with_detect()Aaron Durbin
For all the chipsets which were performing the following sequence: x86_setup_fixed_mtrrs(); x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); Replace that with x86_setup_mtrrs_with_detect() since it is equivalent. Change-Id: I9f362dbf38942d675f615d22b9e5770ce65e5a08 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13936 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-08nyan: Fix timestamps and CBFS SPI integrationJulius Werner
Nyan is an old board that was committed before several core code modernizations to timestamp and CBFS code. Not all of those later patches were correctly integrated with old boards like this, and the core code has evolved to a point where it doesn't actually boot anymore. This patch fixes that issue and brings the Nyan boards more in line with how later ARM platforms look. BRANCH=None BUG=None TEST=My Blaze boots again. Change-Id: I3277a2f59ad8ed47063f7f6b556685313b1446f8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 6a1679e342a7adc2b2371b6e3f69a898a7a5c717 Original-Change-Id: I2a0a2abbd79b4b5f756125dcbb6cbd9441016d4e Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/328543 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/13832 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-03-08skylake: Add and fill out CID1 NVS fieldDuncan Laurie
Add a country identifier field to NVS and populate it with the call to wifi_regulatory_domain() which will (by default) do a lookup for the 'region' identifier in VPD on a Chrome OS device. BUG=chrome-os-partner:50516 BRANCH=glados TEST=build and boot on chell Change-Id: Ie7531848e620095732772c22156a85b7f8a6df5c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: dafdb3760a0302e3effdc0e83977c1bfd5c9d3b2 Original-Change-Id: Ic83ab008045a469d0e0756f7e4d42f1b3894c529 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329295 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13839 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-08soc/intel/quark: Set the UPD values for MemoryInitLee Leahy
Set the UPD values for MemoryInit. * Update the FspUpdVpd.h file which specifies the parameters for MemoryInit. * Add the necessary values to chip.h to enable values to come from the mainboard's devicetree.cb file * Add the parameters to the mainboard's devicetree.cb file * Locate the platform configuration database file (pdat.bin) * Copy the data values from the chip_info structure into the UPDs * Display the UPD values Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful when the UPD data is displayed before the call to MemoryInit Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13896 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-03-08soc/intel/apollolake: Add cbmem_top() implementationAndrey Petrov
On Apollolake CPU memory mapping is similar to previous SoC, and we place CBMEM right under TSEG. Change-Id: I606f690449ba98af6e9fc3074d677c7287892164 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13883 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08soc/intel/quark: Add the UPD support for SiliconInitLee Leahy
Add the routines to handle the UPDs for SiliconInit. Currently no support is required. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful if coreboot calls SiliconInit Change-Id: I5176ab4b1ea7681c3095f102a86f4b614366c0fc Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-08soc/intel/apollolake: Enable using FSP 2.0 driverAndrey Petrov
Change-Id: I5d50fecca51e89aed597e1cfafbcd4515d4d4388 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08soc/intel/apollolake: Add romstage that calls FSP2.0 driverAndrey Petrov
This romstage is minimalistic. Its goal is to set up some BARs that FSP expects to be set and then invoke FSP driver to train memory. Change-Id: I3fa56aafe99cf6cf062a46dece3a0febeafdbfad Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13805 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08soc/intel/apollolake: Add support for memory-mapped boot mediaAndrey Petrov
On Apollo Lake SPI flash is memory mapped. The mapping is different to previous platforms. Only "BIOS" region is mapped in contrast to whole flash. Also, the 128 KiB right below 4 GiB are being decoded by readonly SRAM. Fail accesses to those regions, rather than returning false data. Change-Id: Iac3fa74cd221a5a46ceb34c2a79470290bcc2d84 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13706 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-07intel/fsp_baytrail: use 20K PU/PD for GPIOBen Gardner
The E3800 datasheet only lists 2K and 20K Pull Strength for the GPIOs. The 10K and 40K values map to 'reserved'. This brings the code closer to the non-FSP baytrail. Change-Id: I77078bdbbccc00976525dc43fb98f5b2e79eae03 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/13907 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-07soc/intel/quark: Split out MTRR supportLee Leahy
Split out the MTRR support into a new module: mtrr.c. TEST=Build and run on Galileo Change-Id: Ib9ec479d171dbbc062509e14fbe246f6d90e903a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-01Skylake: Support Intel Speed Shift Technology based on configSubrata Banik
Intel Speed Shift Technology is a new mechanism that replaces Legacy P-state. ISST allows OS hints about energy/performance preference. H/W performs the actual P-state control (autonomous) 1. Optimization frequency seclection for low residency workloads, no longer a static knee point. 2. Optimized frequency selection for best energy to performance trade offs. 3. Kick down frequency (from idle) fpr best responsiveness while taking energy consumption init account. Coreboot's responsiblity is to configure MSR 0x1AA ISST_EN bits which will reflect in CPUID.06h:EAX[Bit 7] that driver checkes and enable HWP accordingly. BUG=chrome-os-partner:47517 BRANCH=None TEST=Booted kunimitsu and verify HWP getting enabled/disabled using Intel P-state driver. Change-Id: I91722aa1077f4ef6c8620b103be3e29cfcd974e5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: aa7d004cb2e19047e4434e3e2544cf69393ce28f Original-Change-Id: Ie617da337babde7f196a7af712263e37f7eed56f Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313107 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: https://review.coreboot.org/13835 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-29skylake: Increase IGD stolen size to 64MBDuncan Laurie
The FBC hardware for skylake does not have access to the bios_reserved range so it always assumes 8MB is used and so the kernel will therefore need to avoid using the last 8MB of the stolen window. With the default stolen size of 32MB(-8MB) there is not enough space for FBC to work with a high resolution panel. Kernel reference: http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=a9da512b3ed73045253afd778e40d4298f42905b BUG=chrome-os-partner:50396 BRANCH=glados TEST=build and boot on chell DVT Change-Id: I3049d7d9e7c551aad5b8fd1630d5fbd88ccb2692 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: fff1f4b35e23e77cdc72c5bcc290f199494cdbbb Original-Change-Id: If468cca5759a320f3cd2d7eb09f4bcc0117b24cb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/328813 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13833 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-29soc/intel/quark: Reserve non-MMIO spaceLee Leahy
Adjust the memory map to allocate MMIO from non-memory addresses. TEST=None Change-Id: Icb6863665c466e8609af73eb9338165c7d6f46bf Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13856 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-29soc/intel/quark: Initialize some of the FADT base registersLee Leahy
Initialize the base addresses for: * Power management control * Power management status * Reset * Power management timer * General-Purpose Event 0 Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_PAYLOAD_ELF=y * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" * Testing successful when: * Register address are properly displayed by the payload * "reset -c" performs a reset and reboots the system * "reset -w" performs a reset and reboots the system * "reset -s" performs a reset and turns off the power Change-Id: I9d043f4906a067b2477650140210cfae4a7f8b79 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13764 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-26tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"Denis 'GNUtoo' Carikli
Change-Id: Ib73abb0ada7dfdfab3487c005719e19f51ef1812 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/13779 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-26soc/intel/apollolake: implement bootblock_soc_early_init()Aaron Durbin
Provide a bootblock_soc_early_init() to that takes care of initializing the UART on behalf of the mainboard when serial console is enabled. Change-Id: I2d3875110b6f58a9e0b4c113084b85817aa05a87 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13793 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-26soc/intel/apollolake: provide function to set up uart pads and controllerAaron Durbin
Instead of pushing the same code into each mainboard for configuring the the UART pads and initializing the host contoller provide a function to perform all the actions on behalf of the mainboard. The set of pads configured is dictated by the CONFIG_UART_FOR_CONSOLE Kconfig option. Change-Id: I06c499c7ee056b970468e0386d4bb1bc26537247 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13792 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-26soc/intel/appollolake: fix comment in gpio_defs.hAaron Durbin
GPIO_187 is the beginning of the Northwest community pads. Change-Id: I5565ecf534530144e80c65d886db11b53f38f935 Signed-off-by Aaron Durbin <adurbin@chormium.org> Reviewed-on: https://review.coreboot.org/13789 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-02-26soc/intel/apollolake: group serial console options into one KconfigAaron Durbin
Add SOC_UART_DEBUG which does all the appropriate selection of the dependent Kconfig options for seral console. Also provide a default option of it being turned off instead of always selected. Change-Id: I1a6dba9c0072a17859c8f389709afe6fe3b04fac Signed-off-by: Aaron Durbin <adurbin@chormium.org> Reviewed-on: https://review.coreboot.org/13790 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-25fsp_baytrail: Fix a possible hanging DisplayPortWerner Zeh
On some devices it can happen that DisplayPort TX lanes do not work properly if the power gate setup is omitted. If that happens, DisplayPort training will fail and therefore DisplayPort channel will not work. Both ports are affected. It seems that not every CPU shows this effect and those that are affected tend to fail more often in a cold environment. With this fix a board that originally shows this failure was running for over 1000 power cycles without issues. Change-Id: Ia266674490a1bee63a85b38d1dc949dcdf683cbc Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/13743 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-22urara: Increase bootblock sizeJulius Werner
The urara bootblock is less than a kilobyte from its limit (20K). There's more than enough space available so increase it to avoid impeding changes to core code. Also add some more automated checks to better model the platform's multiple windows into the same memory region and guard against accidental overlaps by a seemingly benign change to one window. Change-Id: I2e535b56d5d1748830ea1e70fd12fd9e87009bce Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13733 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-22soc/intel/quark: Add the initial pieces required for ACPI tablesLee Leahy
Enable ACPI tables TEST=None Change-Id: I38b90f54cd9b00b063557c08980e71851bf3059b Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13758 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-22fsp_baytrail: Add full support for iosf access in reg_scriptWerner Zeh
Add all needed functions to fsp_baytrail so that reg_script can do full iosf access. To keep it simple, this patch synchronises iosf access between baytrail and fsp_baytrail. Change-Id: Ic7f52d7d90c0fe3560fa5a5d96f7fc15062d66d1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/13742 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-21soc/*: fix uart's regwidth specification in cbtablesPatrick Georgi
coreboot passes information about the serial port implementation to payloads through a cbtables entry. We set the register width to 1 on most SoCs because that looked as good a default as any, but checking the uart structs they use, it's 4 for all of them. Change-Id: I9848f79737106dc32f864ca901c0bc48f489e6b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13746 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-02-19soc/intel/quark: Use single ID value for HSUART1Lee Leahy
Use single ID value for HSUART1. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing successful if: * Debug serial output stays enabled after BS_DEV_RESOURCES state Change-Id: I38eca247f151e67c2b243a8a3bb21d9d1f4603de Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13734 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-18soc/intel/quark: Enable HSUART1Lee Leahy
Enable HSUART1 for debug serial output. Specify the fixed resources in the UART driver. This keeps debug serial output flowing during the rest of the device initialization. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing successful if: * Debug serial output stays enabled after BS_DEV_RESOURCES state Change-Id: Ica02e5fece156b21d4a3889284ca467d55c7880d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13730 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-18soc/intel/quark: Establish the Memory MapLee Leahy
Add ramstage.h to define some of the common header files used by the drivers in ramstage. Add northcluster.c, the driver for the memory controller, which defines the memory map. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing successful if: * Memory map successfully displayed in BS_WRITE_TABLES state Change-Id: I8dc91119eaad0b7abc2e484d13ee708ba1253438 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13721 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-18soc/intel/quark: Enumerate the PCI devicesLee Leahy
Add the chip and domain support which enables the display of the vendor and device IDs for the PCI devices. Testing on Galileo: * Edit src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The PCI vendor and device IDs are displayed. Change-Id: I517dcafd83c7dd850bc3471f939d6804a05020c3 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13719 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-16soc/intel/apollolake: bootblock: implement platform_prog_run()Andrey Petrov
Once bootblock copied romstage into CAR it may not jump into it right away. This is because we are in NEM mode, there is no backing store and a miss in L1 may cause L1D line snoop that gets written back. The solution is to flush L1D to L2 so snoop guaranteed to hit L2. Change-Id: I2ffe46dbfdfe7f0ccd38b34ff203ff76b6d5755b Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13703 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-15skylake: Finalize SMM in corebootDuncan Laurie
Once we lock down the SPI BAR we need to tell SMM to re-init its SPI driver or it will be unable to write ELOG events via SMI. This SMI is also sent at the end of depthcharge so there was just a window where SMI events could get lost. BUG=chrome-os-partner:50076 BRANCH=glados TEST=enable DEBUG_SMI, boot to dev screen, press power button and see elog events get added without without transaction errors. Change-Id: I1f14717b5e7f29c158dde8fd308bdbfb67eba41a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 60ca24c760c70e2ebe5f3e68f95d3ffdba0fef9e Original-Change-Id: I4e323249f00954e290a6a30f515e34632681bfdd Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/326861 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13697 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-15skylake: Check for power failure when WAK_STS is not setDuncan Laurie
The PCH does not set PM1_STS[WAK_STS] bit when waking from a G3 state, which is triggered by hibernate now on chell when we do a PMIC shutdown. This means the checks for S5 wake are not done and instead it is logged as a wake from S0. BUG=chrome-os-partner:50076 BRANCH=glados TEST=pass firmware_EventLog test on chell Change-Id: I3ca05a4824df3401150a63d4b6555f759de40087 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: de6c9bac447edd06568193f990f1f4e278576783 Original-Change-Id: I4472498468d620fe69f2b68710e818a4ad287382 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/326888 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13696 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-15skylake: Enable DDI-A 4-lane support if GOP does not executeDuncan Laurie
This change will allow the kernel to use 4-lane eDP connections if the GOP driver does not execute and set this bit. If GOP has executed (everyone but Chrome OS verified mode) the link will already be up and this will do nothing. BUG=chrome-os-partner:50197 BRANCH=glados TEST=boot on chell and ensure 4 Change-Id: I9e2328b00db84f26b9bd03220b8ac0bd5f64cfbf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cff83e18ce9936c8d507f93c8443b7056c62e844 Original-Change-Id: I3f1e5d78b91eb0e4a23fcc196aff0edadc252a0c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/327251 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13690 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-15skylake: acpi: Make GRXS method serializedDuncan Laurie
This method creates a named object and should be serialized to avoid a compiler warning from recent iasl releases. BUG=chrome-os-partner:40635 BRANCH=glados TEST=emerge-chell coreboot with no iasl warnings Change-Id: If54df4eca8849a8d278816712164b30a775a41ca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9aa8c5627276be08bf0dc3d0f4b9b7bd3f40c227 Original-Change-Id: Ieb05525503bf61c9922677484aba5479856a3f35 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/326843 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13689 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-13soc/intel/apollolake: add assert for pad constraintsAaron Durbin
Ensure the pads passed into the gpio functions are within range. Change-Id: Ic523cbfaf60a46709080347af3a36d6330f9a07c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13694 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-13soc/intel/apollolake: pre-evaluate gpio number valuesAaron Durbin
To allow sharing macros in ASL as well as C the macros can't have complex expression because the ASL compiler does not evaluate those expressions. To that end, just pre-calculate the values. Lastly, add N_OFFSET and utilize it for symmetry. Change-Id: I546d71008e776b27ce8bcd24d2cbd2ee1b2d8020 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13693 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-13soc/intel/apollolake: limit bootblock size to 32KiBAaron Durbin
The CSE places the bootblock (IBBL in Intel parlance) below 4GiB at top of the address space. However, it's size is limited to 32KiB. For now, just limit all of bootblock to 32KiB. Change-Id: I8f84138fb81027eae1712b7af3943942c35cf0ea Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13692 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12tegra132/pistachio: Increase romstage size in memlayout.ldJulius Werner
These SoCs have come within a kilobyte of their romstage limit, so let's expand that a little to make room for future core code contributions. (In the Tegra case just by copying the layout from Tegra210, because why not? Keeps things simple.) BRANCH=None BUG=None TEST=Ran abuild with and without --chromeos for Foster, Rush, Ryu, Smaug and Urara. Change-Id: If8c1ea81cf9827412c78d67a09d54e7a2dc044ac Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13668 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-12tegra132/210: Remove memlayout_vboot2.ldJulius Werner
Having two separate memlayouts is an unnecessary complication. Contributors need to make sure that their code fits into the vboot one (with smaller stage sizes) either way, and the Tegras have plenty of SRAM anyway. Let's just make the vboot layout the default (as it was done on other SoCs) to keep things easier to maintain. The empty SRAM holes on non-vboot systems where the verstage and work buffer would've been won't hurt them. BRANCH=None BUG=None TEST=Ran abuild with and without --chromeos on Foster, Rush, Ryu and Smaug. Change-Id: If37228facb4de1459cc720dca10bf03e04eb9930 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13667 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-12timestamp: Remove HAS_PRECBMEM_TIMESTAMP_REGION KconfigJulius Werner
This patch generalizes the approach previously used for ARM32 TTB_SUBTABLES to "auto-detect" whether a certain region was defined in memlayout.ld. This allows us to get rid of the explicit Kconfig for the TIMESTAMP region, reducing configuration redundancy and avoiding confusion when setting up future boards. (Removing armv4/bootblock_simple.c because it references this Kconfig and it is a dead file that I just forgot to remove in CL:12076.) BRANCH=None BUG=None TEST=Booted Oak and confirmed that all pre-RAM timestamps are still there. Built Nyan and Falco. Change-Id: I557a4b263018511d17baa4177963130a97ea310a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13652 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11arches: lib: add main_decl.h for main() declarationAaron Durbin
It is silly to have a single header to declare the main() symbol, however some of the arches provided it while lib/bootblock.c relied on the arch headers to declare it. Just move the declaration into its own header file and utilize it. Change-Id: I743b4c286956ae047c17fe46241b699feca73628 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13681 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-02-11soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLEAndrey Petrov
Early UART driver is for bootblock and romstage. It is supposed to be used when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits in bootblock requiered for serial to be set up. Change-Id: I15520d566f107797e68d618885d4379e73d0fa45 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13677 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11soc/apollolake: Add minimal GPIO driverAndrey Petrov
This adds the minimal functionality needed to configure SoC pads. Change-Id: I2e2268eee2b8c822b42a48a95604b0fab86c9833 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13676 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-02-11soc/apollolake: Add initial cache-as-ram setup for bootblockAlexandru Gagniuc
This is the minimum setup needed to both get cache-as-ram setup and a C environment working. On apollolake, we only get 32 KiB of data loaded into an SRAM that is readonly to the main CPU. Due to this restriction we have to set CAR and a C environment very early on. Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13301 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-11util/marvell: Add Marvell doimage utility and dependency in relevant MakefileRuilin Hao
- Add the doimage sources in util/marvell - Add dependency in root makefile - Add dependency in makefile for armada38x soc BUG=chrome-os-partner:47462 TEST=emerge-cyclone coreboot BRANCH=tot Change-Id: I81b30e0865cbd619a41659c3f2819ad3bafc5f24 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4b2a990150580e0b879a346ed8b71b3765b66bab Original-Change-Id: I7e89b5e96206fde97ce69c296850122fd6c858f9 Original-Signed-off-by: Kefei Yao <kfyao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/318046 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org> Reviewed-on: https://review.coreboot.org/13137 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-10Kconfig: Move defaults for CBFS_SIZEMartin Roth
We want the question for CBFS size to be next to the rom size in the mainboard directory, but that doesn't seem to work for how people want to set the defaults. Instead of having the list of exceptions to the size, just set the defaults at the end of kconfig. - Move the defaults for chipsets not setting HAVE_INTEL_FIRMWARE into the chipset Kconfigs (gm45, nehalem, sandybridge, x4x) - Override the default for HAVE_INTEL_FIRMWARE on skylake. - Move the HAVE_INTEL_FIRMWARE default setting into the firmware Kconfig file - Move the location of the default CBFS_SIZE=ROM_SIZE to the end of the top level kconfig file, while leaving the question where it is. Test=rebuild Kconfig files before and after the change, verify that they are how they were intended to be. Note: the Skylake boards actually changed value, because they were picking up the 0x100000 from HAVE_INTEL_FIRMWARE instead of the 0x200000 desired. This was due to the SOC_INTEL_SKYLAKE being after the HAVE_INTEL_FIRMWARE default. Affected boards were: Google chell, glados, & lars and Intel kunimitsu. Change-Id: I2963a7a7eab037955558d401f5573533674a664f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-10soc/intel/quark: Report CPU infoLee Leahy
Decode the CPU variants and display the CPU info. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Successful if Quark X1000 is displayed Change-Id: I7234a6d81a48cdd02708b80663147e2b09ba979e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13605 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-10soc/intel/quark: Call FSP SiliconInitLee Leahy
Optionally relocate FSP into DRAM and then call FSP SiliconInit. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select DISPLAY_FSP_ENTRY_POINTS" * Add "select DISPLAY_HOBS" * Optionally add "select RELOCATE_FSP_INTO_DRAM" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * FSP entry points are displayed and * The message "FspSiliconInit returned 0x00000000" is displayed and * The HOBs are displayed correctly and * The message "ERROR - Missing one or more required FSP HOBs!" is not displayed Change-Id: I91e660ea373a8bb00fc97fe8b760347cbfa96b1e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13631 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-10soc/intel/quark: MTRR supportLee Leahy
Add the SoC specific routines to access the MTRR registers. These registers exist in the host bridge and are not accessible via the rdmsr/wrmsr instructions. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select DISPLAY_MTRRS" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The message "FSP TempRamInit successful" is displayed Change-Id: I7c124145429ae1d1365a6222a68853edbef4ff69 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13530 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-10soc/fsp_baytrail: Add support for FSP MR 005Ben Gardner
Baytrail FSP MR 005 adds two new fields: AutoSelfRefreshEnable APTaskTimeoutCnt Add the device tree definitions. Change-Id: I12e2a8b0b5cbeb6b7289cf91f65b25e73007a8de Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12973 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com>
2016-02-10soc/intel/quark: FSP MemoryInit SupportLee Leahy
Add a dummy fill_power_state routine so that execution is able to reach FSP MemoryInit. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select DISPLAY_HOBS" * Add "select DISPLAY_UPD_DATA" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * MemoryInit returns 0 (success) and * The the message "ERROR - Coreboot's requirements not met by FSP binary!" is not displayed Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13447 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09rockchip/rk3288: UART uses 32bit wide registersPatrick Georgi
Change-Id: I084eb4694a2aa8f66afc1f3148480608ac3ff02b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13635 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-09intel/skylake: Add gpio macro for unused GPIO pinsdavid
Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and GPIO TX/RX will be disabled. BUG=none BRANCH=none TEST=Build and boot lars Change-Id: I3a6fcd2f3462e8e0d1273aa80b1599b76b160825 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 889bfd66dbc918e9fb0ba1b95b63fd7a3bf180d9 Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319964 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/13628 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09soc/intel/quark: Enable Serial PortLee Leahy
Add the code to enable debug serial output using HSUART1: * Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1 * Note that the BIST value is always zero as validated in esram_init.inc * The initial TSC value is currently not saved! Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if serial output is present on HSUART1 at 115200 baud, 8-bit, no parity Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13445 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-09nhlt: add api to override oem_id and oem_table_id of acpi_header_tFang, Yang A
This patch added nhlt_soc_serialize_oem_overrides and nhlt_serilalize_oem_overrides to be able to override oem_id and oem_table_id.board file can pass specific string by calling nhlt_soc_serialize_oem_overrides kernel use these two fields to construct a topology binary name if the designate file is not found a default dfw_sst.bin will be used it is optional. BUG=chrome-os-partner:49570 BRANCH=glados TEST=Build & Booted kunimitsu board. Verified that kernel can read new strings. Change-Id: I00b64fb8bb63de601d3116e0b8941057c1efa230 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 374ce08b2d8a2f4e5dd7f51eacb505dbb77fd171 Original-Change-Id: I03623c8ac81efb5a5ea3ec9c6cd604d2e9294022 Original-Signed-off-by: Fang, Yang A <yang.a.fang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/322860 Original-Commit-Ready: Yang Fang <yang.a.fang@intel.com> Original-Tested-by: Yang Fang <yang.a.fang@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13602 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09chromeos: Remove CONFIG_VBNV_SIZE variableDuncan Laurie
The VBNV region size is determined by vboot and is not really configurable. Only the CMOS implementation defined this config variable so switch it to use VBNV_BLOCK_SIZE defined by vboot in vbnv_layout.h instead. This requires updating the broadwell/skylake cmos reset functions to use the right constant. BUG=chrome-os-partner:47915 BRANCH=glados TEST=manually tested on chell Change-Id: I45e3efc2a22efcb1470bbbefbdae4eda33fc6c96 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e2b803ff3ac30ab22d65d1e62aca623730999a1d Original-Change-Id: I4896a1a5b7889d77ad00c4c8f285d184c4218e17 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324520 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13598 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-08soc/intel/quark: Add TempRamInit supportLee Leahy
Successfully invoke TempRamInit from the FSP binary: * Don't relocate the FSP binary image * Copy the FSP binary into ESRAM * Specify Kconfig values to easily debug ESRAM and TempRamInit code * Specify the FSP binary file location * Specify the FSP binary image ID * Specify where in the flash image the FSP image must reside * Specify the FSP data file location * Specify where to place the FSP data file in the flash image * Specify where in the ESRAM the FSP image must reside Test 1 on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select ENABLE_DEBUG_LED_FINDFSP" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if the SD LED is on indicating that the FSP.bin file was properly located, The test fails if the SD LED is flashing. Test 2 on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Remove "select ENABLE_DEBUG_LED_FINDFSP" * Add "select ENABLE_DEBUG_LED_TEMPRAMINIT" * Testing is successful if the SD LED is on indicating that the FSP.bin file was properly located, The test fails if the SD LED is flashing. Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13443 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-08soc/intel/quark: Enable ESRAMLee Leahy
The Quark SoC uses ESRAM instead of cache-as-RAM. This code requires that utils/xcompile/xcompile change the machine architecture from i686 to i586 to ensure that the Quark does not attempt to execute unsupported instructions: * Adjust Makefile.inc to add the RMU to the coreboot image * Add code to enable the ESRAM Directly use the QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h file from the EDK2 tree (https://github.com/tianocore/edk2.git) to enable easy differences and correct issues in coreboot that were found in EDK2. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_RMU_FILE" * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Remove power from the board * Apply power to the board * Testing is successful if the SD LED is on indicating that the end of esram_init.inc was reached Change-Id: I91d919da144bb72a5d4c4a8050ffab256632a395 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13440 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-04intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdownArchana Patni
Keeping ACPI PM timer alive prevents XTAL OSC shutdown in S0ix which has a power impact. Based on a DT variable, this patch disables the ACPI PM timer late in the boot sequence - disabling earlier will lead to a hang since the FSP boot flow needs this timer. This also hides the ACPI PM timer from the OS by removing from FADT table. Once the ACPI PM timer is disabled, TCO gets switched off as well. BRANCH=none BUG=chrome-os-partner:48646 TEST=Build for skylake board with the PmTimerDisabled policy in devicetree set to 1. iotools mmio_read32 0xfe0000fc should return 0x2. cat /sys/devices/system/clocksource/clocksource0/available_clocksource should list only "tsc hpet". acpi_pm should be removed from this list. Change-Id: Icfdc51bc33b5190a55196d67e18afdaaa2f9b310 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 18bcb8a434b029295e1f1cc925e2b47e79254583 Original-Change-Id: Ifebe8bb5a7978339e07e4e12e174b9b978135467 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319361 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13588 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04intel/skylake: unconditionally set SPI controller BARAaron Durbin
The setting of the SPI controller BAR was conditional on the nominal frequency being set. Therefore, that doesn't mean the SPI BAR is set on all boots. Move the setting of the BAR in the southbridge_bootblock_init() which is called prioer to cpu_bootblock_init(). BUG=chrome-os-partner:44827 BRANCH=None TEST=Confirmed spibar is always set on glados. Change-Id: Ia58447d70f5e39a4336d4d08593f143332de833a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 56fff7c25c2eb0ccd90e08f71c064b83c66640f8 Original-Change-Id: I1e0cff783f4b072b80589a3a84703a262b86be3a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/319461 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13587 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04intel/skylake: implement vboot_platform_prepare_reboot()Aaron Durbin
In order to not reboot loop in the face of failed vboot verification on resume set the PM1 control register to indicate S5. After the subsequent cold reset the PM1 control register will indicate S5 as it should. BUG=chrome-os-partner:46049 BRANCH=glados TEST=On chell injected failed vboot verification. Ensured a reboot loop doesn't ensue. Change-Id: Ie5e9e3f6441a217a5e02b4d78aaf21f8249b8a43 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a63b57d7bc59bcaf5518f7cc4afccd3d5da6df1c Original-Change-Id: I5e467854bf065a138bd46e476a7e7088f51454ca Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323504 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13579 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04intel/skylake: implement vboot_platform_is_resuming()Aaron Durbin
To allow skylake platforms to run with verified memory init code the chipset needs to implement vboot_platform_is_resuming() so that the vboot code can make proper decisions. BUG=chrome-os-partner:46049 BRANCH=glados TEST=Suspended and resumed on chell. Also, tested with an EC build which returns a bad hash to ensure that is properly caught. Change-Id: I508a339c07dcc9e7c56a0df4201660827b3ae07a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a3e11789339bcd8fc8fc99b704c6a1110acf5302 Original-Change-Id: I40264019eb28e85795258112c720056a6a3fc523 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323503 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13578 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04intel/skylake: Display ME firmware status before os bootDhaval Sharma
Display ME firmware status before os boot. Specifically this patch reads out the ME hfsts1 and hfsts2 status registers that provide information about overall ME health before device gets disabled. This change reused most of the code from bdw me_status implementation. BUG=chrome-os-partner:47384 BRANCH=glados TEST=Builds and Boots on FAB4 SKU2/3. Can observe me status table Change-Id: Ia511c4f336d33a6f3b49a344bfbaea6ed227ffeb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a9d0fb411c3921654f0fdcea2a3d4ee601987af2 Original-Change-Id: Ied7e2dcd9a1298a38dfe1eda9296b9ca8eccf6b1 Original-Credits-to: Duncan Laurie <dlaurie@chromium.org> Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/323260 Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma@intel.com> Original-Tested-by: dhaval v sharma <dhaval.v.sharma@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13573 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04soc/intel/quark: Add minimal Quark SoC X1000 filesLee Leahy
Add the files for minimal Quark X1000 SoC support: * Declare pei_data structure * Declare sleep states and chipset_power_state structure * Specify top of memory * Empty FspUpdVpd.h file TEST=None Change-Id: If741f84904394780e1f29bd6ddbd81514c3e21c9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13439 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04soc/marvell/armada38x: Add i2c driver for armada38xRuilin Hao
Port i2c driver from uboot to coreboot BUG=chrome-os-partner:47462 TEST=emerge-cyclone coreboot BRANCH=tot Change-Id: I8ce2a965acaed68ad0f0518648490ec471c6810b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c2e9592662787ebed1d0aa8cafaa00fd12c2e9c Original-Change-Id: If791228edf29405fa4b2f959a21510bd7da9865b Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313342 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/13113 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04soc/marvell/armada38x: Add gpio driver for armada38xRuilin Hao
Port gpio driver from uboot to coreboot BUG=chrome-os-partner:47462 TEST=None BRANCH=tot Change-Id: Ib6cfbb6e44cb642c7af937778076a51d405ff4a2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5cf94502faad96147d4a4adb42eb13edb64a6439 Original-Change-Id: Ia2e081a85347e2fc8bb365ca527ee2ee32af86f1 Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313341 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org> Reviewed-on: https://review.coreboot.org/13112 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04soc/marvell/armada38x: Add spi driver for armada38xRuilin Hao
Port spi driver from uboot to coreboot BUG=chrome-os-partner:47462 TEST=None BRANCH=tot Change-Id: I747be7001f4cfb8eec33e8e5bdef3fe5bb0eb2ca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9fbc5c2feb6ffacb54ed94e5c7b94b38be2b2ded Original-Change-Id: Ibea9a050ac8bdab6ce4eeb07accde53aeadade5f Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313340 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org> Reviewed-on: https://review.coreboot.org/13111 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04soc/marvell/armada38x: Add generic support for armada38xRuilin Hao
Skeleton for soc armada38x BUG=chrome-os-partner:47462 TEST=None BRANCH=tot Change-Id: I76f631ee6cdfc90c44727cb20aa960796bc785a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e91cc19468325f005c6ac920bbe27a174c409727 Original-Change-Id: Iac5fc34df1ba18b4515029aa2fcff8f78a5df191 Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313179 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Kan Yan <kyan@google.com> Reviewed-on: https://review.coreboot.org/13110 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-02soc/intel/common: Use SoC specific routine to read/write MTRRsLee Leahy
The registers associated with the MTRRs for Quark are referenced through a port on the host bridge. Support the standard configurations by providing a weak routines which just do a rdmsr/wrmsr. Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select DISPLAY_MTRRS" * Add "select HAVE_FSP_PDAT_FILE" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The MTRRs are displayed and * The message "FspTempRamExit returned successfully" is displayed TEST=Build and run on Galileo Change-Id: If2fea66d4b054be4555f5f172ea5945620648325 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13529 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-02Kconfig: indent with tabs, not spaces.Martin Roth
Change-Id: I8996f8ab739a07014a4189738b5624485d752d9d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13540 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-31drivers/intel/fsp1_1: Fix spelling error in API and copyrightLee Leahy
Change granluarity to granularity. Change wacbmem_entryanty to warranty. Update copyright dates. TEST=None Change-Id: Ib7775cb33616751760919a5850777dc6f77a6be9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13528 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-30soc/intel: Add skeleton infrastructure for Apollolake SOCAlexandru Gagniuc
This is the very very minimum needed to compile the code. Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13297 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-29soc/braswell: Fix Global NVS base addressHannah Williams
TEST=Boot to OS Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I9b43eb4f6f7af62a8a0bbe7bfa08feee1eaca24e Reviewed-on: https://review.coreboot.org/13506 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29src/: Chmod 644 all .c, .h, .asl, .inc, .cb, .hex, & Kconfig filesMartin Roth
Some trivial cleanup. Change-Id: I866efc4939b5e036ef02d1acb7b8bb8335671914 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13427 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-29intel/skylake: Implement native Cache-as-RAM (CAR)Subrata Banik
Now coreboot should do BIOS CAR setup along with NEM mode setup. This patch also provides a mechanism to use 16MB code caching benefit although LLC still limited to 1M/1.5M based on SOC LLC limit. Here with unlimited cache line gets replaced. Now we could use unlimited cache size along with well defined data size [pg: updated to current upstream #defines] BUG=chrome-os-partner:48412 BRANCH=glados TEST=Builds and Boots on FAB4 SKU2/3. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: pchandri <preetham.chandrian@intel.com> Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com> Change-Id: I96a9cf3a6e41cae9619c683dca28ad31dcaa2536 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2ec51f15c874ad2f1f4fad52fa8deced7b27a24b Original-Change-Id: Id62c15799d98bc27b5e558adfa7c7b3468aa153a Original-Reviewed-on: https://chromium-review.googlesource.com/320855 Original-Commit-Ready: Subrata Banik <subrata.banik@intel.com> Original-Tested-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13138 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Add interface to program USB2_COMPBG registershkim
Add interface to program USB2_COMPBG register to set HS_DISC_BG and HS_SQ reference voltage for each project. TEST=Get build success and do EFT test Original-Reviewed-on: https://chromium-review.googlesource.com/300846 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Original-Tested-by: shkim <sh_.kim@samsung.com> Change-Id: If2201829e1a16b4f9916547f08c24e9291358325 Signed-off-by: Kenji Chen <kenji.chen@intel.com> Signed-off-by: shkim <sh_.kim@samsung.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12739 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell/acpi/DPTF: Write TCHG state on AC connect.Jenny TC
DPTF should update the charger cooling device state during boot time and every 3 seconds after boot. But 3 seconds polling doesn't seems to be working with current version of DPTF. This impacts charging since DPTF writes states 4 when charger is not connected at boot time. On connecting the charger, DPTF doesn't write 0 to enable charging. This issue is addressed by calling the PPPC function to read cooling device state and passing the value to SPPC to set cooling device state. This doesn't compromise safety since DPTF can override this value later based on the platform thermal condition. Also this provides additional safety measure in the unlikely event that DPTF crashes and is not re-spawned by OS. With this patch even after DPTF crashes, if the power adapter is plugged it would still allow the system to charge correctly. Original-Reviewed-on: https://chromium-review.googlesource.com/288460 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Jenny Tc <jenny.tc@intel.com> Change-Id: I50c7666b86e45d5ab537a9d4149e6c71eba04e50 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12729 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell/acpi: Fix CID1 offset in commentHannah Williams
Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I9fd2ebba985362fe8068c10390bb014cf9015ac5 Reviewed-on: https://review.coreboot.org/13483 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Fix issues found during static code analysisRavi Sarawadi
TEST=Build, boot to OS Original-Reviewed-on: https://chromium-review.googlesource.com/299483 Original-Reviewed-by: Aaron Durbin <adurbin@google.com> Change-Id: I738003b8dfff6a5255085d39e378e18d6ad36bcf Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/12738 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28Braswell: Separate L1 Sub State init procedure for boards.Kenji Chen
Original-Reviewed-on: https://chromium-review.googlesource.com/312743 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: Ib0a891f229477cf359bff6cd02f305606468f07f Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: https://review.coreboot.org/12750 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28Strago: Enable CA MirrorShobhit Srivastava
Configuring UPD PcdCaMirrorEn. This is a board specific parameter. CA mirror is the Command Address mirroring option that is enabled on this board CQ-DEPEND=CL:13038 Original-Reviewed-on: https://chromium-review.googlesource.com/309190 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I05174e18d650332d838e5036c713e91c4840ee75 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12749 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Disable SD card detect simulation in FSPDivya Sasidharan
CQ-DEPEND=CL:13038 Debounce for SD card detect takes a long time and thus affects boot time. Disabling SD card detect simulation in FSP through UPD Original-Reviewed-on: https://chromium-review.googlesource.com/311850 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Iab0794ec058460df94f6bbed5c9b0911e57e3a71 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://review.coreboot.org/12742 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Set max frequency to be turbo frequencyHannah Williams
In set_max_freq, instead of using ratio from IA_CORE_RATIOS, using ratio from MSR_IACORE_TURBO_RATIOS Also, punit_init needs to be called before enabling this frequency. Original-Reviewed-on: https://chromium-review.googlesource.com/295268 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Iabdab9ec45f8eef0a105a5a05dbcdb997b6764b0 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12736 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Fix DSP clockfdurairx
The codec clock frequency was incorrectly set to 25MHz. The only available frequency is 19.2MHz through external clock and PLL. Original-Reviewed-on: https://chromium-review.googlesource.com/295768 Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5 Signed-off-by: Felix Durairaj <felixx.durairaj@intel.com> Reviewed-on: https://review.coreboot.org/12732 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28drivers/intel/fsp1_1: Remove extra include referencesLee Leahy
Remove include references to the soc include directory which are not required to build the FSP driver. Remove "duplicate" include file definitions from file that include fsp/romstage.h. Move the definition of fill_power_state into soc/pm.h to ensure it is still available. TEST=Build and run on Galileo Change-Id: Ie519b3a8da8c36b47da512d3811796eab62ce208 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13436 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-27soc/braswell: Fix leakage on V1P8S railShobhit Srivastava
Tristate MMC1_RCLK pin to fix leakage on V1P8S rail. Original-Reviewed-on: https://chromium-review.googlesource.com/292043 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Change-Id: I76cc9211ba93b2596d3c0d772d99f8934656e01c Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com> Reviewed-on: https://review.coreboot.org/12730 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-27soc/braswell: Add macro NATIVE_INT_PU20KHannah Williams
Change-Id: I04db02d37a76f0643a73ae4d67b839e5cd61f7e3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13054 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-26Braswell: Implement Gpio library functions to read RAMIDSubrata Banik
Added GPIO library code to allow all BSW board specific code to use memory configuration GPIOs in GPIO Input mode and read them to determine which memory type is on the board. Also added other GPIO related APIs to support GPIO access in BSW. Original-Reviewed-on: https://chromium-review.googlesource.com/294893 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Idd65136c0449f0cdebfae12a510985e29889fa2b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12735 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: revise cbmem_topCC Ma
Support memory range querying to above/below 4GiB. Enable PRERAM_CBMEM_CONSOLE. BRANCH=none BUG=none TEST=build and verified pass on oak board Change-Id: If12ab2e9b8a129e2c82dd97b0493d9abdd6985a9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 139a3163ca867ec5676c6cb81fdec724c99a4a99 Original-Change-Id: Ie190f86f49ae88671f0738e2d6ceafdad58a93cc Original-Signed-off-by: CC Ma <cc.ma@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292559 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13098 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22mediatek/mt8173: move rtc_boot() to romstageYidi Lin
BRANCH=none BUG=none TEST=boot to kernel Change-Id: I0630d7c172e97f81abb1722afe028542e9e7f106 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 608c66df0543c76be7e811b06718464776631b55 Original-Change-Id: I03426085121bfa44c99c351d63db28f567d0ee1d Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313969 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13097 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22mediatek/mt8173: Add usb phy driverChunfeng Yun
BRANCH=none BUG=none TEST=build pass and test it ok on oak Change-Id: Ib3d3f420dd576a63d7504dd0949040a3d430c675 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b17b03ed40b562a520185fa243bc4458daed6f23 Original-Change-Id: Ib9346f7913433ca82e8123feaf34fd0d6c071047 Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292687 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13095 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: pll: Add API for enabling USB 3.0 phy reference clockChunfeng Yun
BRANCH=none BUG=none TEST=test it ok on oak-rev3 Change-Id: I05233c5b9aa237dce1e6667ed09fe6d56f8e6350 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eb3efe8d0d1199ab836af01dc012cc97257b4fd4 Original-Change-Id: Ie1ab9421052dbd6aea8fbd762143cec0ce0d88f5 Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297942 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13094 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: configure audioKoro Chen
BRANCH=none BUG=none TEST=build and verified pass on oak board Change-Id: I2680f6b87614362dffb27490bdeedf7125006c3f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc2bb9f5b461ec848df8aba07940b895401004f8 Original-Change-Id: I848468cec04a36659fbb4b898dff9368305d72ac Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292683 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13091 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: add APLL clock settingKoro Chen
Add a new function mt_pll_set_aud_div() to set APLL for audio I2S. The function is called by mainboard's configure_audio(). BRANCH=chromeos-2015.07 BUG=chrome-os-partner:41507 TEST=build and verified pass on oak board Change-Id: Ia3c2f250627028422a7427b93d78d49545eb7a75 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bb18943f5e74af7723bd4e01d4da96c0b153a0f6 Original-Change-Id: I7996a8048f2e54ab09093cca3c8bc7447b61170f Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297225 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13090 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: Add mtcmos power-on control for audio and displayCC Ma
BRANCH=none BUG=none TEST=none Change-Id: Ic046c66c8e314bd61f96c2edbc5d832260590afe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 84de3a6f1a726938e2318814d6faaf6a7dd29ac0 Original-Change-Id: If29f28a092617532dd73e71e0dbe24fd930c3bf8 Original-Signed-off-by: CC Ma <cc.ma@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292677 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12617 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-01-22mediatek/mt8173: Add RTC driverTianping Fang
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I03740ce1afeb8607891fff61110a40dd98b80bdc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9b0cc22cb9e2010e28e854d9984c11149a71ae0b Original-Change-Id: I6d6482a75cc40ed6183ee115d5d866257afa24af Original-Signed-off-by: Tianping Fang <tianping.fang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292676 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12616 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 18:49:18 +0000