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The pixel clock for some panel (ex: CMN N116BGE-EA2: 76420000) cannot be matched
by our PLLD params finding algorithm, after VCO/CF limitations are applied.
To support these panels, we want to allow "best matched" params.
BRANCH=nyan
BUG=none
TEST=emerge-nyan_big coreboot chromeos-bootimage;
emerge-nyan coreboot chromeos-bootimage;
# Successfully brings up display on Nyan_Big EVT2 and Nyan Norrin.
Original-Change-Id: If8143c2062abd2f843c07698ea55cab47bf1e41a
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/195327
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 8aa66e659e3c60296f05e59b4343496a850ea019)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I623db44de35fecee5539e4d72f93f28b5fa0b59c
Reviewed-on: http://review.coreboot.org/7771
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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We found that without enabling DC in tegra_dc_sor_enable_dc, kernel would have
problem showing the text console before graphics interface is initialized, for
example "chromeos factory install shim (text only)" or the "splash screen".
BRANCH=none
BUG=chrome-os-partner:28082
TEST=emerge-nyan coreboot chromeos-bootimage
Boots factory install shim and see text console.
Original-Change-Id: I6fce963ceddd125dd52789d2ec843cc2ee05f1f5
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/195388
(cherry picked from commit 375a86be9b23650cd96e46b07c7a0b5c10970797)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ib75e3ffac9b216c7486845cb8459dd8952d51fe6
Reviewed-on: http://review.coreboot.org/7770
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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Dump all SOR registers for debug purpose. By default, this function
is not being built in.
BRANCH=none
BUG=chrome-os-partner:27413
TEST=build nyan and nyan_big.
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Change-Id: I7f44709b8572b9eac33c2193b92a65bf2b22aa76
Original-Reviewed-on: https://chromium-review.googlesource.com/194738
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: Tom Warren <twarren@nvidia.com>
Original-Tested-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit d08c0f7c5e8ac094987b09fae96e8133ed9c08c5)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1341bbbd0ea6277e5a1b286d6f088f2961070416
Reviewed-on: http://review.coreboot.org/7769
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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This patch adds some documentation to the additional PLL divisor
constraints on the intermediary VCO and CF values that we just found out
about. PLLC divisors for some oscillators had to be adjusted
accordingly.
It also adds a new clock_get_pll_input_khz() function to replace
clock_get_osc_khz() in cases where you want to factor in the built-in
predivider for 38.4 and 48 MHz oscillators.
BUG=None
TEST=Still boots.
Original-Change-Id: Ib6e026dbab9fcc50d6d81a884774ad07c7b0dbc3
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/194474
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 3f1f565baf100edcd486055e4317c675c882396f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I091f42bf952a4b58ef2c30586baa5bf7496fa599
Reviewed-on: http://review.coreboot.org/7768
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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This register needs to be set properly during display init.
BRANCH=none
BUG=chrome-os-partner:27413
TEST=build nyan and nyan_big. nyan display works fine.
nyan_big display works as well. However, the mode setting
needs to be based on either devicetree or EDID.
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Change-Id: I93c69d8042a3f3c19f4e24801423b73246e37031
Original-Reviewed-on: https://chromium-review.googlesource.com/194739
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Original-Tested-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit ee9a3c472c5621edebefcc8882582c6fc01255e2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie642a008eaf6c4ab68ede1dde98ff4268f51fc9c
Reviewed-on: http://review.coreboot.org/7767
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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BRANCH=none
BUG=chrome-os-partner:27413
TEST=build nyan and nyan_big. nyan display works fine.
nyan_big display still does't work until all related
patches are built in. (CL:194739)
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Change-Id: Ic5d977f695be127693f1ecc3ba52d478f524d20f
Original-Reviewed-on: https://chromium-review.googlesource.com/194737
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Original-Tested-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit ef3208d8ff3c3dcfaeda9c0146bf1ae920682dea)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ide1cd28ecc0ae1cd4d8603a52975592daee4bce8
Reviewed-on: http://review.coreboot.org/7766
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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Correct SOR attaching sequence.
https://chromium-review.googlesource.com/190300
BRANCH=none
BUG=chrome-os-partner:27413
TEST=build nyan and nyan_big. nyan display works fine.
nyan_big display still doesn't work until all related
patches are built in. (CL:194737 and CL:194739)
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Change-Id: I8aaf65db90e5e45bd9097c9d38b231bd7d41d997
Original-Reviewed-on: https://chromium-review.googlesource.com/194403
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Original-Tested-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit fea9d288b98dcc6fc32dc93212fa7c4185603646)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I6646816809e29c63de65caa7e7146cd3d02902cf
Reviewed-on: http://review.coreboot.org/7765
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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Tegra124 family products may want to use many different display panels with
various timing settings. To support them, we should initialize display panel by
EDID instead of hard-coded values.
BUG=none
TEST=emerge-nyan coreboot chromeos-bootimage
BRANCH=none
Original-Change-Id: Ib125a7f9cb1e6c8cf2d79e0baab525acfd1b7a6e
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/192730
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 43ecd473419aa0fbdd22487416b0b6cfea6a20d1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I6af47db113035e9440e663a769318776c7b6b70b
Reviewed-on: http://review.coreboot.org/7764
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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There is no need to call cbmemc_reinit() exclusively in romstage,
that is done as part of the CAR migration of cbmem_recovery().
CBMEM console for romstage remains disabled for boards flagged with
BROKEN_CAR_MIGRATE, but with this change it is possible to have it for
ramstage.
Change-Id: I48c4afcd847d0d5f8864d23c0786935341e3f752
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7592
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <gaumless@gmail.com>
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Flag the boards with BROKEN_CAR_MIGRATE, as testing for EARLY_CBMEM_INIT
is not enough to disable CBMEM console for romstage on these platforms.
To have CBMEM early in ramstage, define get_top_of_ram() on sandy/ivy.
Change-Id: Ieefc12099a0e043eb1a7e14bdc7c6e3d209b3d8f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7468
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
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The new API is in use in depthcharge and is based around the "i2c_transfer"
function instead of i2c_read and i2c_write. The new function takes an array of
i2c_seg structures which represent each portion of the transfer after a start
bit and before the stop bit. If there's more than one segment, they're
seperated by repeated starts.
Some wrapper functions have also been added which make certain common
operations easy. These include reading or writing a byte from a register or
reading or writing a blob of raw data. The i2c device drivers generally use
these wrappers but can call the i2c_transfer function directly if the need
something different.
The tegra i2c driver was very similar to the one in depthcharge and was simple
to convert. The Exynos 5250 and 5420 drivers were ported from depthcharge and
replace the ones in coreboot. The Exynos 5420 driver was ported from the high
speed portion of the one in coreboot and was straightforward to port back. The
low speed portion and the Exynos 5250 drivers had been transplanted from U-Boot
and were replaced with the depthcharge implementation.
BUG=None
TEST=Built and booted on nyan with and without EFS. Built and booted on, pit
and daisy.
BRANCH=None
Original-Change-Id: I1e98c3fa2560be25444ab3d0394bb214b9d56e93
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193561
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 00c423fb2c06c69d580ee3ec0a3892ebf164a5fe)
This cherry-pick required additional changes to the following:
src/cpu/allwinner/a10/twi.c
src/drivers/xpowers/axp209/axp209.c
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I691959c66308eeeec219b1bec463b8b365a246d7
Reviewed-on: http://review.coreboot.org/7751
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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According to DP version 1.2a, The MOT (Middle-of-Transaction) bit
must be set when the I2C transaction does not stop with the current
AUX transaction.
Thus the correct steps for an I2C read shall be:
1. I2C command write with MOT set to 1
2. I2C command read to the same address with MOT set to 0
BUG=chrome-os-partner:27679
TEST=EDID data read from LP140WH8 panel is correct while it's a
repeated pattern of the first 16 bytes without this CL
BRANCH=none
Original-Change-Id: I0526beffb8852fbbe0eb5bb80e370261617a59b8
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/194915
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 466ab0e00744f79ae3720474140d95e5f0828de9)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic8ad38b4b08989dd7178d59151e1e276b8a58439
Reviewed-on: http://review.coreboot.org/7763
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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PLLD, the clock for display, was previously hard-coded to 306MHz. To support
more different panels, we should calcualte PLLD by panel pixel clock
configuration.
Note existing pixel clock configurations for nyan* boards won't work (they used
to rely on hard-coded approximated values) so the device trees are also
modified.
BRANCH=none
BUG=chrome-os-partner:25933
TEST=emerge-nyan_big coreboot chromeos-bootimage
See panel correctly initialized and got DEV screen.
Original-Change-Id: I8d592f0cc044e7c4e4803c45955642e791210ad3
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/193565
(cherry picked from commit 4f9b793633ebb2d104b0544e3b72fa0d105951c4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ib2cabbad60af010e872505e888eab485ba8c2916
Reviewed-on: http://review.coreboot.org/7762
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This adds a missing dma_release() at the end of DMA transfers. It
probably doesn't matter since we don't do many DMA transfers, though
I wouldn't want to hit some corner case with EFS and eventlog.
BUG=none
BRANCH=none
TEST=tested on nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I79b30455babe75a13aac827caac88bf7053ec9e4
Original-Reviewed-on: https://chromium-review.googlesource.com/194479
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit dc7dc1d25bd88873b4c1198a6f3723d27c914ddc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8c5da4e104328fd8bce71942e6eda458a37bfe06
Reviewed-on: http://review.coreboot.org/7761
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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It worked earlier since the APB and AHB bus widths occupy the same bits
in their respective registers.
BUG=none
BRANCH=none
TEST=tested on Nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I9b18c648c60dcc4ad62ca1f514d253f8cccaeee7
Original-Reviewed-on: https://chromium-review.googlesource.com/194478
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 1d912302e9dcc9c6ba69e15434bb1841e1196208)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I2ea7ac83d3501876df52018aed467ec33074817e
Reviewed-on: http://review.coreboot.org/7760
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This change takes about 8K of space away from the cbfs cache and repurposes
it for the cbmem console buffer. This is a little more than twice the space
we currently need for the bootblock and ROM stage to give us some room to grow
and for extra debug output if needed.
BUG=None
TEST=Built and booted on nyan. Checked the cbmem output.
BRANCH=None
Original-Change-Id: I6543bf5efddcf2377528a273f846b8090cd8be55
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193169
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 32e9ea6f9ecaa9b5441c91acab96514222f3af2c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ia9e5cc7a4b561bd89137cdc8b594584b272d9fab
Reviewed-on: http://review.coreboot.org/7757
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Consolidate the register setting clrsetbits_le32 call to simplify the macros.
Add a check for bits of the divisor being dropped. The clock source registers
will throw away bits that aren't supported, so we can check for divisor
overflow by checking for dropped bits.
BUG=None
TEST=Purposefully tried to set a clock to a rate which overflows its divisor.
Verified that the check triggered. Booted on nyan. Verified the TPM i2c bus
frequency was still correct.
BRANCH=None
Original-Change-Id: I3b1b6ba57f6b7729f303d15a16b685a48751d41f
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193348
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 9cd79dd974d8a3c31398f8fbd62750b194867891)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id4d8ecfeff52737cdd68999028b37cbdedb0d116
Reviewed-on: http://review.coreboot.org/7738
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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To ensure that the command1 write which sets the "go" bit completes before
other reads to the device. Otherwise, there's a race condition where those
register values might still have their values from the last transfer. With
different SPI clock frequencies, that could lead to spi_delay being told there
were negative bytes still to send. Its expected delay would wrap to a negative
value, that was passed to udelay, and the system would sit there for 4 seconds
not doing anything.
BUG=None
TEST=Built and booted on nyan. Set the SPI bus frequency to a value which was
causing the 4+ second delay and verified that it no longer happened.
BRANCH=None
Original-Change-Id: I8b4090efc69f34d0413e3f63c59c1825dd151cec
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193347
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit d7ea9febdf2c5942f81607ee6ded786c9a8954bb)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I095bfc745eda37b8e666475ceb41684152f3709a
Reviewed-on: http://review.coreboot.org/7737
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This fixes two problems with the clock configuration on tegra124. First, the
macro which set up the i2c clocks tried to account for the fact that the i2c
divisor's lsb represents 1.0 where it normally represents 0.5 by multiplying
the target frequency by 2. That doesn't work, unfortunately, because the
divisor is actually n + 1, and what n + 1 means depends on where the one's
place is in the divisor.
Also, when calculating the divisor, the standard C division operator uses
truncation to deal any remainder which tends to make the divisor smaller. That
has the effect of making the output frequency higher than what was requested.
Since it's usually safer to undershoot a frequency than overshoot it, this
change makes those divisions round up instead.
Finally, the hand tuned temporary UART clock configuration was adjusted so
that it still ends up with the same divisor. Without that, very early output
from the bootblock is garbled, specifically the coreboot welcome banner,
build timestamp, etc.
BUG=chrome-os-partner:27220
TEST=Built and booted on nyan. Used a logic analyzer to verify that the TPM
i2c bus ran at 400KHz instead of 660KHz, and that the divisor was the expected
value. Measured boot time with and without EFS and verified that there was no
change. Spot checked the output for errors and verified that none of the
bootblock output was garbled.
BRANCH=None
Had to add the stdlib.h from 89ed6c that hadn't been merged correctly.
Original-Change-Id: I7e948c361ed4bf58c608627d32f2e3424faea1fb
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193362
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 164f7010a47d3bbdbc8bb572106140ae186f3807)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I317b66eda929c0e5a5832adca267b8b54c6aae34
Reviewed-on: http://review.coreboot.org/7736
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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To read EDID, we need to access I2C via DP AUX channel.
BRANCH=none
BUG=chrome-os-partner:25933
TEST=emerge-nyan coreboot chromeos-bootimage
Original-Change-Id: I2666b5d46843485b79265a537f19bd8eab5e1a26
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/188858
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 8f8e98ff5038b57f89332aee75573095c3933dd2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5b1b6ab2940c8265483059fd94a2c4db2a41144a
Reviewed-on: http://review.coreboot.org/7735
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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If EFS is enabled and vboot didn't tell us it's going to use the display, we
can skip initializing it and save some boot time.
BUG=chrome-os-partner:27094
TEST=Built and booted on nyan without EFS in recovery mode and normal mode.
Built and booted on nyan with EFS in recovery mode and normal mode. Verified
that in normal mode with EFS the display initialization was skipped and boot
time was essentially the same as when display initialization was simply
commented out.
BRANCH=None
Original-Change-Id: I1e2842b57a38061f40514407c8fab1e38b75be80
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/192544
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit a672d18c3570e6991a1c1c0089697112a4cd71d0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I95e8bd7a447876174305f755cc632365ed6f5a30
Reviewed-on: http://review.coreboot.org/7734
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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They were only used internal to the SPI drivers and, according to the comment
next to their prototypes, were for when the SPI controller doesn't control the
chip select line directly and needs some help.
BUG=None
TEST=Built for link, falco, and rambi. Built and booted on peach_pit and nyan.
BRANCH=None
Original-Change-Id: If4622819a4437490797d305786e2436e2e70c42b
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/192048
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 1e2deecd9d8c6fd690c54f24e902cc7d2bab0521)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ida08cbc2be5ad09b929ca16e483c36c49ac12627
Reviewed-on: http://review.coreboot.org/7708
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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spi_set_speed was never implemented, and spi_cs_is_valid was only implemented
as a stub and never called.
BUG=None
TEST=Built for rambi, falco, and peach_pit.
BRANCH=None
Original-Change-Id: If30c2339f5e0360a5099eb540fab73fb23582905
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/192045
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 98c1f6014c512e75e989df36b48622a7b56d0582)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Iebdb2704ee81aee432c83ab182246d31ef52a6b6
Reviewed-on: http://review.coreboot.org/7707
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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The SPI drivers for tegra and exynos5420 have code in them which waits for a
frame header and leaves filler data out. The SPI driver shouldn't have support
for frame headers directly. If a device uses them, it should support them
itself. That makes the SPI drivers simpler and easier to write.
When moving the frame handling logic into the EC support code, EC communication
continued to work on tegra but no longer worked on exynos5420. That suggested
the SPI driver on the 5420 wasn't working correctly, so I replaced that with
the implementation in depthcharge. Unfortunately that implementation doesn't
support waiting for a frame header for the EC, so these changes are combined
into one.
BUG=None
TEST=Built and booted on pit. Built and booted on nyan. In both cases,
verified that there were no error messages from the SPI drivers or the EC
code.
BRANCH=None
Original-Change-Id: I62a68820c632f154acece94f54276ddcd1442c09
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/191192
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 4fcfed280ad70f14a013d5353aa0bee0af540630)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id8824523abc7afcbc214845901628833e135d142
Reviewed-on: http://review.coreboot.org/7706
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
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Change-Id: Iaaf68fd19f7b9a5b6849fffde3a9c68cb7862367
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7619
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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- In '-ffreestanding' main() is just as any other function and so
it needs a type-signature. Fixes a clang warning.
- Bay Trail and Rangeley have the updated romstage.c with the code
moved into the chipset, put the prototype in romstage.c.
- The sandybridge code has not been updated, so the prototype
for it goes into chipset_fsp_util.h, next to the prototype for
romstage_main_continue.
- Correct the return value of baytrail main() from void * to void
and remove the unnecessary asmlinkage tag. I'm surprised that this
didn't generate a warning...
Change-Id: I85ac0797d1e55d2b7ffdca039a52820d7827e704
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7724
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Change-Id: Ideb58634a029d55746421ad1ea4b80811bca403c
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7705
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: Ica9e3a91718a7e490ff80e5029fc29650355eb47
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7704
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: I966645c83ae78943a7dbb9dc05af4fded6f4e5b5
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7703
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: I2f970c6970b4996fcefbde89332210f5a1afe836
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7702
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: I72c9c1f5811fafaeec9572b05726d5677e2c28b1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7669
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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- The EDS has the function disable bit for eMMC incorrectly listed
as 8. Changing it back to the correct bit 11.
- The FSP will disable functions that it is told are disabled, so
coreboot code that disables the functions is redundant. Removing it.
Change-Id: I95c31d92d3af5182ddf7fd47f651bbb61cdedb82
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7653
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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The documentation for the FSP gives the name as BAYTRAIL_FSP.fd instead
of the old FvFsp.bin.
Change-Id: I69c7c5ff49afd6552612cf50c9ca9b30cfb003e2
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7648
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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New microcode for Bay Trail I B2/B3 and D0 parts was released in the
Gold 3 Bay Trail FSP release.
Change the microcode size to an area instead of the exact size of the
patches. This will hopefully reduce updates to the microcode size.
Change-Id: I58b4c57a4bb0e478ffd28bd74a5de6bb61540dfe
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7647
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Move the Kconfig variable into a .h file - this does not need to be
in Kconfig.
Change-Id: I1db20790ddb32e0eb082503c6c60cbbefa818bb9
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7646
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Include clock.c in the appropriate coreboot stages, modify the code to
build cleanly. Use proper pointer cast in .h files.
BUG=chrome-os-partner:27784
TEST='emerge-storm coreboot' still succeeds
Original-Change-Id: I227c871b17e571f6a1db3ada3821dbb1ee884e59
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196407
(cherry picked from commit 75decceccd97298974891bb98b796eccfe11f46c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I7d44464d4ca8153e84407fc05a25e2e79e74901e
Reviewed-on: http://review.coreboot.org/7271
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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These driver needs to be in src/lib, and the include file needs to be
renamed to avoid collision with the top level uart.h.
BUG=chrome-os-partner:27784
TEST=emerge-storm coreboot still works
Original-Change-Id: Ie12f44e055bbef0eb8b1a3ffc8d6742e7a446942
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196393
(cherry picked from commit c5618fd418642f5b009582f5f6bc51f7c9d54bec)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5e25ae350ac5e71b47a0daef078b03cc5ac35401
Reviewed-on: http://review.coreboot.org/7270
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Set the UPD entry based on the Kconfig value instead of having two
separate places that the value needs to be set.
Change-Id: I3d32111b59152d0a8fc49e15320c7b5a140228a6
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7490
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
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Update the printk statements to use FSP_INFO_LEVEL instead of
BIOS_DEBUG. These values are currently identical, but by using the
second #define, it lets them all be changed as a unit. This can
be overridden for a particular platform by adding a #define in
chipset_fsp_util.c.
Change-Id: Idbf7e55090230ec940c7c8cd3ec8632461561428
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7520
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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- Update chipset_fsp_util.c to use the UPD_DEVICE_CHECK macro. This
makes the code more standardized and easier to read.
- Add some debug printing that was removed in the transition.
Change-Id: Iea24dd9ca53f39791bc6371291a3fa7a6fc5ed0f
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7498
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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- Update chipset_fsp_util.h to add the UPD_MEMDOWN_CHECK pointing into
the PcdMemoryParameters structure. This is baytrail FSP specific, so
it's put into the chipset code instead of the 'driver' code. Since some
of the values need to be decremented and some do not, a second parameter
was added to control this. This macro also does not print out the
values as they are printed out separately if memory down is enabled.
- Update chipset_fsp_util.c to use the UPD_MEMDOWN_CHECK macro. This
makes the code more standardized and easier to read.
Change-Id: I233e45db43af4726cab41f4880f1706cf8abb0b7
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7632
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Update chipset_fsp_util.c to use the UPD_SPD_CHECK macro. This
makes the code more standardized and easier to read.
Change-Id: I9944e1a4df82e64a205598e98ed0f3b840af1019
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7489
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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- Update chipset_fsp_util.c to use the UPD_DEFAULT_CHECK macro. This
makes the code more standardized and easier to read.
- Update chip.h to use standardized macros
Change-Id: Icbe5ec92b0aa31e21f3dd1593a96b246d83008f7
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7488
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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There were instances of unneeded arch/hlt.h includes,
various hlt() calls that weren't supposed to exit (but
might have) and various forms of endless loops around
hlt() calls.
All these are sorted out now: unnecessary includes are
dropped, hlt() is uniformly replaced with halt() (except
in assembly, obviously).
Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7608
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Works in the RISCV version of QEMU.
Note that the lzmadecode is so unclean that it needs a lot of work.
A cleanup is in progress.
We decided in Prague to do this as one thing, because it forms a nice case study
of the bare minimum you need to add to get a new architecture going in qemu.
Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/7584
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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No need to mark Makefiles, C files or devicetrees
executable.
Change-Id: Ide3a0efc5b14f2cbd7e2a65c541b52491575bb78
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7618
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7606
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM.
See commit a0b4a8d.
Change-Id: Iae82498ab729df5682d89e66bb9de96457e91619
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7465
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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According to spec IRQ1 isn't available for PIRQ assignment.
Has gone unnoticed probably because modern OS use MSI or
at least APIC and even with noapic don't use IRQ1 with PCI
IRQs.
Change-Id: Idc7db249007df629b27e8cae41cc80358d5306f6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7478
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
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Change-Id: I9e29ca10689cbbbaba593185868e54b8697aa9c4
Signed-off-by: Herve Elter <rvnvv74@gmail.com>
Reviewed-on: http://review.coreboot.org/7523
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins)
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Baytrail Gold3 FSP adds a couple of parameters in UPD_DATA_REGION
making platform more configurable via devicetree.cb
Update the UPD_DATA_REGION structure and pass settings to FSP
Add Baytrail Gold2 and earlier FSP backward compatible, as Gold3
FSP changes UPD_DATA_REGION struct
Change-Id: Ia2d2d0595328ac771762a84da40697a3b7e900c6
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/7334
Reviewed-by: Martin Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins)
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As build.h is an auto-generated file it was necessary to add it as
an explicit prerequisite in the Makefiles. When this was forgotten
abuild would sometimes fail with following error:
fatal error: build.h: No such file or directory
Fix this error by compiling version.c into all stages.
Change-Id: I342f341077cc7496aed279b00baaa957aa2af0db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7510
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: Icc4691f260521e7f3cc9388210c9b7631cf7ce18
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7363
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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The ACPI compiler is trying to be helpful in letting us know that we're
not using various fields in the MCRS 'ResourceTemplate' when we define
it inside of the _CRS method. Since we're not intending to use those
objects in the method, it shouldn't be an issue, but the warning is
annoying. Moving the creation of the MCRS object to outside of the
_CRS method and referencing it from there solves this problem.
Change-Id: I222642e9a93f3078b46ed74f57b83a5834657abf
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7499
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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The entries in chip.h are used to set the UPD values. These had
originally been shortened and did not match the names of the structure
entries in vendorcode/intel/fsp/baytrail/include/fspvpd.h
This patch aligns the names.
- Update names in chip.h.
- Update names in devictree registers for bayley bay and minnow max.
- Update names in chipset_fsp_util.c
Change-Id: I8d7e34195cec2e63802d7e07e5aed71735556936
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7486
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Configuring a link bandwidth configuration and then
complaining that it's invalid seems unreasonable.
Change-Id: I6423da6700d4f266222458758c885a4ea47e0df9
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7502
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
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Precedence rules make the compiler optimize
const | var ? val1 : val2; into val1. In our case this
means not writing 2 << NV_SOR_CSTM_ROTCLK_SHIFT to the
register and not caring about the content of is_lvds.
Change-Id: I0b02c74f9445f51bfab9eeae2e8eb9480d104708
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7501
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
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Change-Id: I59d42cd451997e141e02d99a62b84a7a2201eb31
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7500
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
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The non-x86 systems need the monotonic timer interface.
Add tegra124's timer implementation so vboot can link.
BUG=chrome-os-partner:27094
BRANCH=None
TEST=Built nyan with vboot verfication.
Original-Change-Id: I75b99b6e07eeab0324495f97472f14a36883161e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/190925
(cherry picked from commit 1e632e861f0e6d10cea0010561e410c1d6c2f317)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9ef177f7c7bb90ceacfe25162bb97047a7c8599d
Reviewed-on: http://review.coreboot.org/7463
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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This is the only way to clear the error bits in the controller. Without
clearing them, every future transaction will look like it failed.
BUG=chrome-os-partner:27220
TEST=Built and booted on nyan with the TPM frequency turned up to 400 KHz.
BRANCH=None
Original-Change-Id: Ib654e60ec3039ad9f5f96aa7288d3d877e5c843a
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/191811
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 7b19a095652f1561590dcca922b9f8c308d7de9d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I301b6694cc521601b618973de891e4ed44c6a97d
Reviewed-on: http://review.coreboot.org/7460
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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Currently we put the VPR write code just right before the AVP is going
to freeze. We have no idea does the write operation successful or not
before halting the AVP. And the power_on_main_cpu should be the last step
of that. So we make a fix to change the order.
BUG=none
BRANCH=none
TEST=LP0 suspend stress test and check the VPR is correct;
LP0 suspend stress test with video playback
Original-Change-Id: Ia62dde2a020910de39796d1cf62c1bf185cdb372
Original-Signed-off-by: Joseph Lo <josephl@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/192029
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Original-Commit-Queue: Tom Warren <twarren@nvidia.com>
Original-Tested-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit 51473811fa477cca9ad9cbafdaad4fd4a2309234)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ia28329e38fcf12994594b73c805d061804aa01c4
Reviewed-on: http://review.coreboot.org/7459
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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These make it possible to reset peripherals without having to dig into the
crc.
BUG=chrome-os-partner:27220
TEST=Built and booted on nyan with EFS and with the TPM bus turned up to
400KHz.
BRANCH=None
Original-Change-Id: I7e77b719e1ba30d2964cfbfda467f937d80b5b21
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/191810
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 18c6a48623ae6eff70ca05ea15a7901972a7bba3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8f46666bcf51215f332724ea871f14fec2b522f0
Reviewed-on: http://review.coreboot.org/7458
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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The existing display init functions were translated from a script. The new
code will play the same functions but are cleaner and readable and easier to
be ported to new panel.
BUG=none
TEST=build nyan and boot up kernel.
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Change-Id: Ic9983e57684a03e206efe3731968ec62905f4ee8
Original-Reviewed-on: https://chromium-review.googlesource.com/189518
Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 5998f991ea3069d603443b93c2ebdcdcd04af961)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Squashed to pass abuild
nyan: Fix the build for big and blaze.
The display code for the tegra124 was cleaned up recently, but only the nyan
device tree was updated to match the new code, not big's or blaze's. This
change copies nyan's device tree over to those other two boards which will get
them building again. The settings may not be correct, but they'll be no less
correct than they were before. I also updated the copyright date for nyan.
BUG=none
TEST=Built for nyan, nyan_big, nyan_blaze. Booted on nyan_big and verified the
panel wasn't damaged by the new display code or settings.
BRANCH=None
Original-Change-Id: I75055a01f9402b3a9de9a787a9d3e737d25bb515
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/191364
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit ea235f23df31b4ca8006dcdf3628eed096e062b9)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Icdad74bf2d013c3677e1a3373b8f89fad99f616e
Reviewed-on: http://review.coreboot.org/7454
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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readelf(1) may not know about the i386 flavor, or not
be present at all under this name.
Change-Id: I285df1f2098200b89918a4c4d3610e6427e86e01
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7448
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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This patch changes the ENTRY() macro in asm.h to create a new section
for every assembler function, thus providing dcache_clean/invalidate_all
and friends with the same --gc-sections goodness that our C functions
have. This requires a few minor changes of moving around data (to make
sure it ends up in the right section) and changing some libgcc functions
(which apparently need to have two names?), but nothing serious.
(You may note that some of our assembly functions have data, sometimes
even writable, within the same .text section. This has been this way
before and I'm not looking to change it for now, although it's not
totally clean. Since we don't enforce read-only sections through paging,
it doesn't really hurt.)
BUG=None
TEST=Nyan and Snow still boot. Confirm dcache_invalidate_all is not
output into any binary anymore since no one actually uses it.
Original-Change-Id: I247b29d6173ba516c8dff59126c93b66f7dc4b8d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/183891
(cherry picked from commit 4a3f2e45e06cc8592d56c3577f41ff879f10e9cc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ieaa4f2ea9d81c5b9e2b36a772ff9610bdf6446f9
Reviewed-on: http://review.coreboot.org/7451
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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Commment out nonessential timer services and modify the source code to
cleanly build in coeboot environment. Do not remove dead code just
yet, these functions might be necessary later.
Need to rename the soc timer.h to prevent collisions with timer.h in
the top level include directory.
Currently build timer code for ramstage only.
BUG=chrome-os-partner:27784
TEST='emerge-storm coreboot' still succeeds
Original-Change-Id: Ib10133ccb42697840708845a8ea6d75ceeaeb3d5
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/194067
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 987ce95220953c16216d1e1d70d5a941d05fc9bc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ia9cf175da11c70709354def5e51bf79df4fda2fe
Reviewed-on: http://review.coreboot.org/7269
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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The SBL3 currently seems to be preventing the bootblock from being
loaded into the IMEM. As a temporary measure, map bootblock into DRAM
(as it is available after SBL2 finished running) and specify the
correct stack space.
BUG=chrome-os-partner:27784
TEST=not much testing yet, just verify 'emerge-storm coreboot' still succeeds.
Original-Change-Id: Ibe9d4911ad22ada1bbd01af54a2ef80009df3a28
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196168
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 950323d6091c3b795034c24a08b6c176f56f0e0f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ib3ec21f2cb4058b3e3cc82864de89dadf3b6aa84
Reviewed-on: http://review.coreboot.org/7268
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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The sbl blobs could not yet be published, they have been moved to a
private location. Update coreboot to pick up the blobs at the correct
place.
BRANCH=None
CQ-DEPEND=CL:195003
BUG=chrome-os-partner:28059
TEST=manual
$ emerge-storm coreboot succeeds
Original-Change-Id: I8c4163bc978307e41c156ef9f7f2a211d57db7a8
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/194997
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 1a1848b00acfc2f58990559e824ea9c13c3c239c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: If597ebbfd348039d578c99cd7a8e3c4bcbf60c10
Reviewed-on: http://review.coreboot.org/7267
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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Basic support for ipq806x GPIO CFG and IO reg operations
Reference: IPQ806x PRM, u-boot arch-ipq806x/gpio.*
BUG=None
BRANCH=None
TEST=Compiled successfully
Original-Change-Id: Ia0a9f288de3ac7bdb1cd4acbf44ba46af4dcc4e2
Original-Reviewed-on: https://chromium-review.googlesource.com/194217
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 0b48e6655e63b467fe79d52149be01d23a2a3712)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I09e222f35b4b20c8eb901f33cf4451085c4c99cc
Reviewed-on: http://review.coreboot.org/7266
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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The divider for the I2C clocks works differently than for other IP blocks and
needs to be set up to reflect that. There's also a large internal divider which
means you have to do extra calculations to determine what the frequency of the
bus itself will be based on the I2C controller clock. The new macro takes the
desired frequency of the bus itself and figures everything else out.
BUG=chrome-os-partner:25467
TEST=Built and booted on nyan rev1 using this function to set up the i2c
busses.
BRANCH=None
Original-Change-Id: Ib62a5659bcc0d0e15de41887514ae8efb8c8129a
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/189014
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 24714399a9a89cf33ad20ee43da87e9b04ba394c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9a1eabb16fdb27fb813fe6bc56cdcc593eca166e
Reviewed-on: http://review.coreboot.org/7417
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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There were some missing parenthesis and some extra semicolons which this
change adds and removes, respectively.
BUG=chrome-os-partner:25467
TEST=Built and booted on nyan rev1. Verified that the same frequency calculated
differently results in the same settings. Before operator precedence would
pull apart the frequency calculation and use the pieces in the wrong order.
BRANCH=None
Original-Change-Id: I843d4ae9f7a2ae362926d94b6b77ef31d350a329
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/189013
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 462e61ad898a4d6a99c1d161d77bde245c5b1f5c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ifce3aac262cf5e2ec0496c5b3ad894bf6f0f9a46
Reviewed-on: http://review.coreboot.org/7416
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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PLLP is configured to 408MHz by hardware on T124. Init PLLP is needed only when
to configure it other than 408MHz.
BUG=none
TEST=build nyan and boot kernel.
Original-Change-Id: I8b1abf510ab886e7fddea8864a6d36f12529880e
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/188849
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit d32124cb7562cbce1bb929c3e5f238b13a27b752)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I617f77444a8dd97b20763b50066a1298d3b97724
Reviewed-on: http://review.coreboot.org/7415
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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A PLL (Phase-Locked Loop) clock must be locked before it is assigned
as clock source. Otherwise, this clock is unreliable.
Before:
c base(60006080): 48003201, misc(6000608c): 03000000
x base(600060e0): 40009e01, misc(600060e4): 00000000
p base(600060a0): 40002201, misc(600060ac): 00000200
u base(600060c0): 40005001, misc(600060cc): 00000300
d base(600060d0): 48011b0c, misc(600060dc): 40400800
dp base(60006590): 58305a01, misc(60006594): 40000000
After:
c base(60006080): 48003201, misc(6000608c): 03000000
x base(600060e0): 48009e01, misc(600060e4): 00040000
p base(600060a0): 5801980c, misc(600060ac): 00040800
u base(600060c0): 48005001, misc(600060cc): 00400300
d base(600060d0): 48011b0c, misc(600060dc): 40400800
dp base(60006590): 58305a01, misc(60006594): 40000000
BUG=None
TEST=build nyan and boot
Original-Change-Id: I7e5a2eeb5b17f761e0c462ec68a8b221f327fedc
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/188447
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 7e8e2854b2b7d1ed20d74891c3d19b6c3dd41c55)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ief9efa6937af26fe1a10a7b360fc2f5477416b97
Reviewed-on: http://review.coreboot.org/7414
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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Add a missing "~" so that we mask off just OSC_XOFS field and not the
rest of the register.
BUG=chrome-os-partner:26326
TEST=XHCI sometimes works after LP0.
BRANCH=none
Original-Change-Id: I2df2387dbad6920d36aa2ae5e6cd91e9ec42fa08
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/188897
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit bdbe9ead46fa883618a4acedd1feaf676e2eb29b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic853e737fc106527eb3bb15c25bf801a36bbff57
Reviewed-on: http://review.coreboot.org/7412
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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Fix the PLLU parameters to match the recommended values from the TRM,
and the values used by the kernel and LP0 blob. This includes adding
support for setting an LFCON value. It appears that changing the PLLU
parameters across suspend/resume causes XHCI stability issues after
resume.
BUG=chrome-os-partner:26326
TEST=XHCI works after LP0 suspend/resume on Nyan.
BRANCH=none
Original-Change-Id: Ia4af12fefeebe607803e7f2f03ee4802367b82c3
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/188752
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit bbc8d92eb462e165c2378bcb3055a3a74b47a19b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I687d1709befc2f5dec094ee423f2ff824412996e
Reviewed-on: http://review.coreboot.org/7411
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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The PLLX provides the clock for the main cores which can run at different max
frequencies depending on the specific model of Tegra124. This change makes it
possible to select a model which will, in turn, select a frequency for PLLX.
The default is 2GHz which is the lowest maximum frequency.
BUG=chrome-os-partner:25467
TEST=Booted on nyan rev1. Verified that the selected PLLX frequency was 2GHz.
With a change that selects the right model for nyan, verified that the
corresponding frequency was selected.
BRANCH=None
Original-Change-Id: Iee3a615083dee97ad659ff41cbf867af2a0c325d
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/188602
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 1282015048420a518e6c6959ce982be70378211a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I448a830f3184ad1afeadbd1c2974c7a27b03a923
Reviewed-on: http://review.coreboot.org/7409
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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Typecast address to void* to accomodate address being passed as integers
BUG=None
BRANCH=None
TEST=Compiled successfully
Original-Change-Id: Iceb51056c8a30a9a9dbd0594f75c23000faa6120
Original-Reviewed-on: https://chromium-review.googlesource.com/194365
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit abf9b1e77b8a078e6ed873cbf34246bd97c81e98)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1806e96e194e936975a43e95b9fd7d7458ef1653
Reviewed-on: http://review.coreboot.org/7265
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add an include/ folder to hold all the *.h files for ipq806x soc
BUG=None
BRANCH=None
TEST=Compiled successfully
Original-Change-Id: If07624f126c8d92e479b8f0d9fbc20ab3358a5e3
Original-Reviewed-on: https://chromium-review.googlesource.com/194218
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit c3c573b6a2d7af504e82b2a02a9869d1d057ce36)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I42165fca72b48f0d4f15b192d3bfb1574bc73d7c
Reviewed-on: http://review.coreboot.org/7264
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This patch brings in ipq806x source files from the vendor's u-boot
tree as it was published in the 'cs_banana' release.
The following files are being copied:
arch/arm/cpu/armv7/ipq/clock.c => src/soc/qualcomm/ipq806x/clock.c
arch/arm/cpu/armv7/ipq/gpio.c => src/soc/qualcomm/ipq806x/gpio.c
arch/arm/cpu/armv7/ipq/timer.c => src/soc/qualcomm/ipq806x/timer.c
arch/arm/include/asm/arch-ipq806x/clock.h => src/soc/qualcomm/ipq806x/clock.h
arch/arm/include/asm/arch-ipq806x/gpio.h => src/soc/qualcomm/ipq806x/gpio.h
arch/arm/include/asm/arch-ipq806x/gsbi.h => src/soc/qualcomm/ipq806x/gsbi.h
arch/arm/include/asm/arch-ipq806x/iomap.h => src/soc/qualcomm/ipq806x/iomap.h
arch/arm/include/asm/arch-ipq806x/timer.h src/soc/qualcomm/ipq806x/timer.h
arch/arm/include/asm/arch-ipq806x/uart.h => src/soc/qualcomm/ipq806x/uart.h
board/qcom/ipq806x_cdp/ipq806x_cdp.c => src/mainboard/google/storm/cdp.c
board/qcom/ipq806x_cdp/ipq806x_cdp.h => src/soc/qualcomm/ipq8064/cdp.h
drivers/serial/ipq806x_uart.c => src/console/ipq806x_console.c
Note that local timer.c gets overwritten with the original version. To
prevent a build breakage some shortly to be reverted modifications had
to be made to src/soc/qualcomm/ipq806x/Makefile.inc and
src/soc/qualcomm/ipq806x/cbfs.c.
BRANCH=none
BUG=chrome-os-partner:27784
TEST='emerge-storm coreboot' still succeeds
Original-Change-Id: I3f50bfbec2e18a3b5d2c640cff353a26f88c98c1
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/193722
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 3c9c2ede7e97e330cad2c2f3e557cc9bcdaecdcc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ia7bc66cecfc16f1dd4a9f3cb9840cbe91878adf4
Reviewed-on: http://review.coreboot.org/7263
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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We want the coreboot build produce an image which can be run on the
target, even if the remaining parts of the bootprom (recovery path,
read-write stages, gbb, etc.) are not available yet.
This is achieved by including the Qualcomm SBLs blob in the bootblock.
CQ-DEPEND=CL:193518
BRANCH=None
BUG=chrome-os-partner:27784
TEST=manual
. run the following commands inside chroot to confirm expected image
layout (no actual code is executed on the target yet):
$ emerge-storm coreboot
$ \od -Ax -t x1 -v /build/storm/firmware/coreboot.rom 2>/dev/null | head -1
000000 d1 dc 4b 84 34 10 d7 73 15 00 00 00 ff ff ff ff
$ \od -Ax -t x1 -v /build/storm/firmware/coreboot.rom | grep 220000
220000 05 00 00 00 03 00 00 00 00 00 00 00 00 00 01 2a
Original-Change-Id: I10e8b81c7bd90e4550a027573ad3a26c38c3808a
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/193540
(cherry picked from commit 64e193974ee448f78e0a5775a440094901590afb)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Idbdbeb9d229eff94a7a94af5dc4844a295458200
Reviewed-on: http://review.coreboot.org/7262
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Once SECURITY_MODE fuse is burned, JTAG is disabled by default.
To reenable JTAG, besides chip unique id and SecureJtagControl need
to be built into BCT, Jtag enable flag is also needed to be set.
BUG=None
TEST=Burn SECURITY_MODE fuse, build chip specific BCT, coreboot
comes up and jtag hooks up fine.
Original-Change-Id: Ic6b61be2c09b15541400f9766d486a4fcef192a8
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/186031
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit ff962b81f424c840ef171d4287a65ab79b018a28)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I14b496932dbc0ed184a2212a5b33d740e1f34a4e
Reviewed-on: http://review.coreboot.org/7403
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Repurpose config->pwm to mean the particular PWM device (we use PWM1 on
nyan), and add code to program the PWM device.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan, regenerate bootimage, and boot.
See that the backlight comes up in the bootloader, and brightness can be
adjusted via pwm_bl driver in the kernel.
Original-Change-Id: I2db047e5ef23c0e8fb66dd05ad6339d60918d493
Original-Signed-off-by: Andrew Chew <achew@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/185772
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
(cherry picked from commit 0dee98dd0c8510ecd630b5c6cb9ea49724dc8b55)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie53610f3afa30b2d8f484685fb0e8c0b12cd8241
Reviewed-on: http://review.coreboot.org/7402
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Add some defines and structs that describe what the PWM registers look like.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
Original-Change-Id: Ie10589e4cbf5292e543d205ac8a1c6b09a0f76d0
Original-Signed-off-by: Andrew Chew <achew@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/185771
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
(cherry picked from commit fbbd2a5e148c1142aee100dbcde17c865b06b2bd)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: If4dc40c1dcdf1723e05923e2fea42ccc47766699
Reviewed-on: http://review.coreboot.org/7401
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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It seems that someone just stuck the PM3 function for all of the potential
PWM pins. Fix this to be more specific to the particular PWM (of which
there are four).
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
Original-Change-Id: Ic61a7321fbe28953b22007a1d0b522c3ca8714ad
Original-Signed-off-by: Andrew Chew <achew@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/185739
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
(cherry picked from commit f19f897fe11a582cc240d98de88c5e2d4dc4e364)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie10173413a5f00e06f5b1803fd93d6cb322cee3d
Reviewed-on: http://review.coreboot.org/7399
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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The Tegra PWM base address was missing, so add it.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
Original-Change-Id: Iebf687c6644290e05ee72794cde697658ab6d7cb
Original-Signed-off-by: Andrew Chew <achew@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/185738
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
(cherry picked from commit b62843f6cfbf870451f658e6df1a3b48256fa4e1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ibb8578a130d5995345592caa610c57c1d7f28573
Reviewed-on: http://review.coreboot.org/7398
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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We'd been putting some data structures like the framebuffer and the cbmem at
the end of memory, but that may not actually be addressable as identity mapped
memory. This change clamps the addresses those structures are placed at so
they stay below 4GB.
BUG=None
TEST=Booted on nyan. Went into recovery mode and verified that there was a
recovery screen. Forced memory size to be 4GB and verified that the recovery
screen still shows up.
BRANCH=None
Original-Change-Id: I9e6b28212c113107d4f480b3dd846dd2349b3a91
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/185571
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 63ea1274a838dc739d302d7551f1db42034c5bd0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I970c1285270cb648bc67fa114d44c0841eab1615
Reviewed-on: http://review.coreboot.org/7397
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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This patch changes several cache-related pieces to be cleaner, faster or
more correct. The largest point is removing the old
arm_invalidate_caches() function and surrounding bootblock code to
initialize SCTLR and replace it with an all-assembly function that takes
care of cache and SCTLR initialization to bring the system to a known
state. It runs without stack and before coreboot makes any write
accesses to be as compatible as possible with whatever state the system
was left in by preceeding code. This also finally fixes the dreaded
icache bug that wasted hundreds of milliseconds during boot.
Old-Change-Id: I7bb4995af8184f6383f8e3b1b870b0662bde8bd4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183890
(cherry picked from commit 07a35925dc957919bf88dfc90515971a36e81b97)
nyan_big: apply cache-related changes from nyan
This applies the same changes from 07a3592 that were applied to nyan.
Old-Change-Id: Idcbe85436d7a2f65fcd751954012eb5f4bec0b6c
Reviewed-on: https://chromium-review.googlesource.com/184551
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 4af27f02614da41c611aee2c6d175b1b948428ea)
Squashed the followup patch for nyan_big into the original patch.
Change-Id: Id14aef7846355ea2da496e55da227b635aca409e
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
(cherry picked from commit 4cbf25f8eca3a12bbfec5b015953c0fc2b69c877)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/6993
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I3e9b7e0e5558a6942067dcea04b83fe3bccbbaf9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7362
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Ipq8064 SBLs initialize the hardware to prepare it to run an arbitrary
user provided bootloader. The only bootloader requirements imposed by
the SBLs are that it is concatenated with the SBL chunks in the
bootprm AND it uses MBN encapsulation (mostly to specify the size and
load address).
This patch adds configuration options to specify the location of the
SBL blobs and to require MBN encapsulation of the bootblock.
BRANCH=none
BUG=chrome-os-partner:27784
TEST=manual
- the below demonstrates added encapsulation, no code run attempts
have been made yet:
$ FEATURES=noclean emerge-storm coreboot
$ cd /build/storm/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999
$ \od -t x4 build/cbfs/fallback/bootblock.bin | head -3
0000000 00000005 00000003 00000000 2a010000
0000020 00000be0 00000be0 2a010be0 00000000
0000040 2a010be0 00000000 e32bf0df e59f0030
Original-Change-Id: Iae30ad08059e2b35c434ac25a410ac2017752957
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/193511
(cherry picked from commit bf16ea915c723ab124d817e3b0d950282e3cf1c1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I53c71d382ec1d826f530d7afb545f64ec4eaf96b
Reviewed-on: http://review.coreboot.org/7261
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This patch switches every last part of Coreboot on ARM over to Thumb
mode: libpayload, the internal libgcc, and assorted assembly files. In
combination with the respective depthcharge patch, this will switch to
Thumb mode right after the entry point of the bootblock and not switch
back to ARM until the final assembly stub that jumps to the kernel.
The required changes to make this work include some new headers and
Makefile flags to handle assembly files (using the unified syntax and
the same helper macros as Linux), modifying our custom-written libgcc
code for 64-bit division to support Thumb (removing some stale old files
that were never really used for clarity), and flipping the general
CFLAGS to Thumb (some more cleanup there as well while I'm at it).
BUG=None
TEST=Snow and Nyan still boot.
Original-Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/182212
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 5f65c17cbfae165a95354146ae79e06c512c2c5a)
Conflicts:
payloads/libpayload/include/arm/arch/asm.h
src/arch/arm/Makefile.inc
src/arch/arm/armv7/Makefile.inc
*** There is an issue with what to do with ramstage-S-ccopts, and
*** will need to be covered in additional ARM cleanup patches.
Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/6930
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I1cf87b3c73d8bf8846e5870b19b089f85c299567
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7241
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Bring code inline to be consistent with the rest of coreboot.
See standard - c99std (n1256) 6.3.2.1p4 - to paraphrase,
'expressions that refer to functions get converted to pointers to
those functions'
Change-Id: I63a7bed5efade37dd7076dbfc9c85d420cf6c92b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7290
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Iaf2b2873bd1c52d7f936bd9b483e194a0872a626
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7285
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
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We're no longer configuring hotplug + backlight settings from
devicetree, so remove these entries + fields.
BUG=chrome-os-partner:27304
TEST=Compile only.
BRANCH=rambi+squawks
Change-Id: I7e27fbc070a9ea774e7dcbe551d61b1b1682a47f
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193831
(cherry picked from commit 4ab13fd3aa2634673bb099bdfd714a21adc3caa0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7218
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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- The hotplug register doesn't work in the way we describe. Just leave
it at default.
- The backlight registers will be configured by the OS driver.
BUG=chrome-os-partner:27304
TEST=Manual on Rambi. Boot system in both dev and normal mode, verify
that display comes up. Also verify that display functions after warm
reboot and suspend / resume.
BRANCH=rambi+squawks
Change-Id: I5559c131f41c4a14e64e5cec66e18d3a4a46092c
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193830
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 3f287cc31e41fabef755c37361e2e65ca413c88c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7217
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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According to DPTF team _PPC in TCPU must return 0 always.
BUG=chromium:355964
TEST=Pass build.
BRANCH=rambi
Change-Id: I76f0da27757ba4717f0e392bcd80e890d925061a
Original-Change-Id: I8b9e17e5479e8a226cb11cd43ce888a3e4dead73
Signed-off-by: Kein Yuan <kein.yuan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/193069
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 6dbcc677ceebbaf832e41e6db1e6cf171e2e231f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7215
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Provide the option to embed MRC as an ELF file and not just
binary blob. This allows for MRC to be relocated.
BUG=chrome-os-partner:27654
BRANCH=rambi
TEST=Built and booted rambi.
Change-Id: I2e177c155a3074e4e1d450b1a73b7299aebd5286
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/192893
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 89c97d5e2023b8c5cc780e1b1d532d0a586512f9)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7214
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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Suggested settings to try for performace regression:
2-core systems:
- MSR_PMG_CST_CONFIG_CONTROL clear bit 11 (SINGLE_PCTL)
- MSR_POWER_MISC clear bit 2,3
- \_PR.CPUx._PSD coordination set to 0xFE (HW_ALL)
4-core systems:
- MSR_PMG_CST_CONFIG_CONTROL clear bit 11 (SINGLE_PCTL)
- MSR_POWER_MISC clear bit 2,3
- \_PR.CPUx._PSD coordination set to 0xFC (SW_ALL)
BUG=chrome-os-partner:26211
BRANCH=baytrail
TEST=emerge-rambi chromeos-coreboot-rambi
Change-Id: Ib68a86525204ae47a820c269257a7b8df9300a6a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/192573
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 8c8c0be0000043610eaa56926eff978f352819b8)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7213
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Moving the cache-as-ram base address to 0xfe000000 will
provide more breathing room in the physical address space.
It will also allow for larger SPI roms in the future.
BUG=chrome-os-partner:27045
BRANCH=baytrail
CQ-DEPEND=CL:*157278
TEST=Built and booted. Suspended and resumes. Vboot works, MRC
settings are being saved as well.
Change-Id: I618c069e504f545e02de5ac54e057566f0b5d6c9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190700
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 73c07a319d678f3e9be2fac64599c94f91c9ad9c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7212
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Implement vboot_get_sw_write_protect, which returns the FW SPI ROM SW WP
status.
BUG=chrome-os-partner:26777
TEST=Manual on Rambi with all patches in sequence:
`crossystem sw_wpsw_boot` prints 0
`flashrom --wp-enable` + reboot
`crossystem sw_wpsw_boot` prints 1
BRANCH=Rambi
Original-Change-Id: I5da35c1b2d25b8679bf0084af65d08de224387f8
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/190097
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 5bba447654417c42952c49542ed047b4867d04d1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I739cbb8fca5f02462cf78c81f9b364aabfd3fe86
Reviewed-on: http://review.coreboot.org/7211
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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