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This patch moves gpio_op.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify all methods present inside
common gpio_op.asl like GRXS, GTXS etc. are still there.
2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I248f5e66994d2f3d6b0bd398347e7cf9ae7f2cc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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TEST=Able to build and boot EVE platform.
1) Dump and disassemble DSDT, verify unified methods like GRXS,
GTXS etc. are there
2) Verify no ACPI error seen while running 'dmesg' from console
3) abuild --timeless to ensure there are no other functional changes.
Change-Id: I02df3ddf5ad33d42d97feefb0fa366ad8c856565
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45681
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=Able to build and boot ICLRVP platform.
1) Dump and disassemble DSDT to ensure GRXS function implementation
remain unchanged prior and after this CL.
2) Verify no ACPI error seen while running 'dmesg' from console.
3) abuild --timeless to ensure there are no other functional changes.
Change-Id: Iab4690341bc3da5d8eb249da4d407d84f7d4e706
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45680
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also drop gpio_common.h in favor of intelblocks/gpio_defs.h macros.
TEST=Able to build and boot CNL and CML platform.
1) Dump and disassemble DSDT, verify unified methods like GRXS,
GTXS etc. are there.
2) Verify no ACPI error seen while running 'dmesg' from console.
3) abuild --timeless to ensure there are no other functional changes.
Change-Id: I78d712eeba56b9c098dc6a6f11e4e51cb2529b10
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45654
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures that GRXS perform PAD_CFG0_RX_STATE mask first
and then right shift PAD_CFG0_RX_STATE_BIT to get correct GPIO number.
Change-Id: I96611936f70f79e9dc5ee9414ec68cef00d0d13a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45738
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The SOC has MAX_CPUS>1 so this is redundant.
Change-Id: Icb4c7551031f4e32e01198261ee9ae9b95f18142
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Nearly every x86 platform uses the same arch for all stages. The only
exception is Picasso. So, factor out redundant symbols from the rest.
Alder Lake is not yet complete, so it has been skipped for now.
Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add code to generate p-state and c-state SSDT objects to coreboot.
Publish objects generated in native coreboot, rather than the ones
created by FSP binary.
BUG=b:155307433
TEST=Boot morphius to shell and extract and compare objects created in
coreboot with tables generated by FSP. Confirm they are equivalent.
BRANCH=Zork
Change-Id: I5f4db3c0c2048ea1d6c6ce55f5e252cb15598514
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Fix typo GPD__SLP_SUSB -> GPD_SLP_SUSB
Change-Id: I2beddb5665dc2f6a28b9c02e240b12da137c1b17
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45685
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Migrate ASL helper function like GRXS, GTXS, STXS, CTXS to ASL 2.0
syntax across CNL, ICL, JSL, SKL.
TEST=Able to build and boot Hatch, EVE and ICLRVP platform.
Dump and disassemble DSDT to ensure GRXS,GTXS etc functions
implementation remain unchanged prior and after this CL.
Change-Id: I0ebf1f86031eae25337d2dbeabb8893d9f19a14b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45677
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also align GPMO ASL function with TGL.
Change-Id: Ia40af2cba9867838a1f99141481a5e78cffa0111
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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LPDDR4x has 6 CA PINs, but for some 8GB LPDDR4X DDR, the left margin
of some CA PIN window is too small than others. Need to enable the CA
perbit mechanism to avoid those risks.
BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: I58e29d0c91a469112b0b1292da80bcb802322d47
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41965
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This resolves a Kconfig warning regarding unmet dependencies.
Change-Id: I9e70a4d333afefcb27c097aa9ce84e5effc0d7c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Drop lpit.asl from CNL and switch to the common one in the three boards
currently using it.
The only difference between the two is the usage on macros in common
code instead of plain integer values.
Change-Id: Iefbd18db7f4c560dce16c4119fde4f4cfbeafb84
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This change adds configuration support for both of CnviBtCore and
CnviBtAudioOffload.
BUG=b:169045123
TEST=Built and boot up to kernel on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Id4bf41f07c4a53de17e9eb91a8ddfb1083cbf83e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45585
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Naveen M <naveen.m@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previously, SMBUS support was not required for Apollo Lake, since the
SPD was read inside FSP-M, during memory initialization. However, the
Kontron mAL-10 COMe module contains Nuvoton HWM chip that is connected
to the processor via SMBUS. This patch adds SMBUS common driver support
for Apollo Lake to initialize this HWM.
TEST = After loading the nct7802 module on the Kontron mAL-10 with Linux
OS, we can read the hwm registers, see temperature and fan speed:
coretemp-isa-0000
Adapter: ISA adapter
Package id 0: +52.0°C (high = +110.0°C, crit = +110.0°C)
Core 0: +52.0°C (high = +110.0°C, crit = +110.0°C)
Core 1: +52.0°C (high = +110.0°C, crit = +110.0°C)
Core 2: +53.0°C (high = +110.0°C, crit = +110.0°C)
Core 3: +53.0°C (high = +110.0°C, crit = +110.0°C)
nct7802-i2c-0-2e
Adapter: SMBus CMI adapter cmi
in0: +3.35 V (min = +0.00 V, max = +4.09 V)
in1: +1.92 V
in3: +1.21 V (min = +0.00 V, max = +2.05 V)
in4: +1.68 V (min = +0.00 V, max = +2.05 V)
fan1: 0 RPM (min = 0 RPM)
fan2: 1729 RPM (min = 0 RPM)
fan3: 0 RPM (min = 0 RPM)
temp1: +53.5°C (low = +0.0°C, high = +85.0°C)
(crit = +100.0°C) sensor = thermistor
temp4: +53.0°C (low = +0.0°C, high = +85.0°C)
(crit = +100.0°C)
temp6: +0.0°C
Change-Id: I408ef84ede27a45fb057e22b2757fa6e66277ddd
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44475
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Refer to commit 490546f (soc/intel: rename get_prmrr_size) for details.
Change-Id: I4a83feedcdb337ba9613a07215196bc223fb46d1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45651
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Parse the generated fmap_config.h file instead of the .fmd file supplied
by the board to determine the size and location of the APOB region.
Parsing the generated file allows to write .fmd files without having to
take into account that the shell script part in Picasso's Makefile.inc
can only parse a subset of the .fmd syntax.
BUG=b:157068645
TEST=Timeless build for amd/mandolin resulted in identical binary.
BRANCH=zork
Change-Id: I6ed1903a8157374d78d2865621baa15774d2a7d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45595
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure FSP UPDs for the chipset minimum assertion widths and
power cycle duration per mainboard variants.
* PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy
* PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy
* PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy
* PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy
* PchPmPwrCycDur: PCH PM Reset Power Cycle Duration
* Check to avoid violating the PCH EDS recommendation for the
PchPmPwrCycDur setting.
BUG=b:159108661
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I8180d95a2185c3786334e10613f47e77b7bc9d5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44557
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I76430f5cd4b661aff85e2d21722f41c03362b1bd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44598
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I01227e3c5b650f56e81c5c8e724e3768f06f4530
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44597
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable processor thermal control using PCI dev path function instead of
Device4Enable parameter in devicetree. This change removes the dependency
on Device4Enable in devicetree. We can enable and disable this thermal
control using on and off support with PCI device entry in devicetree.
BRANCH=None
BUG=None
TEST=Built and tested on dedede board
Change-Id: I0463236996ad001af506c9966840b27fe44d60d2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Verstage in PSP used stub for timestamps since we didn't know about
clock. Now we figured out clock source so we can enable timestamp
functions.
BRANCH=zork
BUG=b:154142138, b:159220781
TEST=build without CONFIG_PSP_VERSTAGE_FILE, flash and boot
Change-Id: I431a243878e265b68783f54ee9424bb1d4fe03c1
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This reverts commit 77cc3267fc970c710299a164ecbc471f9287d719.
Reason for revert: Breaks quark and also needs breaking down into multiple CLs as commented by Nico on CB:45541
Change-Id: Idf4ca74158df15483856754ee24cc4472a8e09b0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Change-Id: Ib262955a1d26681c796c4b10d2b336f2715824d0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: If8aa28a22625b7b2cf9b58958de87ee752f637f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: If76502ff91896959ef171c192b4fc138dff18fc6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I6932580a373608d3d2fa5d844efdc7ffbc577d1f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Ib2843c40de8e4607b8b9d665761a689227878bc0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Expand the scope of 'common/basecode' directory to keep common
non-IP code block (like acpi, power limit).
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I7a2778704016b501eb20382d4603295cec8375d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45522
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id93aab5630e928ee4d7e957801e15a4cc8739fae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44594
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes:
1. Rename do_global_reset() to force_global_reset()
2. Make force_global_reset() function static
3. Implement force_global_reset() into common/reset.c to avoid
dedicated SoC implementation
4. Remove redundant force_global_reset() implementation from
dedicated SoC
5. Make direct call to global_reset() from cse_lite.c
7. Drop CONFIG_HAVE_CF9_RESET_PREPARE Kconfig from APL SoC due
to common reset (soc/intel/common/reset.c) code migration
8. Remove unused function send_global_reset() from SKL me.c due
to common reset code migration
9. Delete heci.c from APL SoC as unused
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I1c5dc8d5606ef28ffaed4a64d90f470ae1ffc2a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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get_prmrr_size does not return the actual PRMRR size but a valid PRMRR
size with repect to the users choice in Kconfig. Thus, rename it from
`get_prmrr_size` to `get_valid_prmrr_size` to avoid confusion about what
it does.
Also fix the broken comment in cpulib.h.
Change-Id: Id243be50acb741f2c3118ddde082743d08983a53
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Since PRMRR size can only be set when SGX is enabled and since SGX
depends on PRMRR size >= 32MB, any lower setting (including "Disabled")
is invalid. Drop these settings.
Change-Id: If7a19c7223a0de2e03b7df9184cddf7c9fc87a68
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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PRMRR size shall only be set when SGX is enabled. Make PRMRR depend on
SGX enablement in Kconfig.
Change-Id: I551942fd9cb8e7123d00dbd752abffe24788148c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Defer cse_fw_sync to BS_DEV_RESOURCES boot state so that MRC training
data can be cached before CSE FW Sync and a second MRC training can be
avoided.
BUG=b:168850641
TEST=Build and boot the waddledoo board to OS. Ensure that the memory
training is performed only once.
Change-Id: I0ef5693eaa6ed34dc08c94e5db153f4295578f5f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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Enhanced Intel SpeedStep Technology (EIST) and Intel Speed Shift
Technology (ISST) - also know as HWP - are two independent mechanisms
for controlling voltage and frequency based on performance hints.
When HWP is enabled, it overrides the software-based EIST. It does not
depend on EIST, though, but can be enabled on its own.
Break up that currently existing dependency in ACPI generation code.
It was tested that HWP can be enabled and gets used by the Linux pstate
cpufreq driver. With HWP disabled, the frequency does not decrease, even
not in powersave mode. After enabling HWP the frequency changed in
relation to the current workload. (Test device: Acer ES1-572)
Change-Id: I93d888ddce7b54e91b54e5b4fdd4d9cf16630eda
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44137
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix function call to invoke 16-bit read in 16-bit api instead of 8-bit read.
Signed-off-by: Igor Bagnucki <bagnucki02@gmail.com>
Change-Id: Ifd9079fc6446125e0e58402fdb64bc198bb8e381
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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PMC support was not enabled on Xeon_sp platforms. This involves turning
on SOC_INTEL_COMMON_BLOCK_PMC and then adding the proper hooks in SOC
specific code. This patch leverages code from the Skylake project and
adds the bare minimum hooks to leverage PMC common code. Most
importantly this enables power management registers located in the PMC
device (under ACPI_BASE_ADDRESS). Access to this device is also needed
for SMM setup and handling.
TEST=build for Tiogapass and enable the following Kconfig options:
select SOC_INTEL_COMMON_BLOCK_PMC
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select CPU_INTEL_COMMON_SMM
Boot the system and ensure pmbase is programmed. (Look for pmbase in
debug messages). Secondly check that SMIs are enabled by looking at the
debug messages (search for "Enabling SMIs") and verifying in HW by
reading IO port 0x530.
Change-Id: I6d57a8282a8b6dc4314f156c39deb09535575cbd
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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IIO_UDS HOB was searched several times during the creation of DMAR table.
Reduce it to only once to improve boot time.
Both DRHD and ATSR subtable creations involve addition of PCIe bridge
device entries, combine the functions with
acpi_create_dmar_ds_pci_br_for_port().
When looping through ports to create PCIe bridge device entries,
use MAX_PORTS intead of NUMBER_PORTS_PER_SOCKET to improve boot time.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I469cd8473c50e105daeda6c5607592ae7cef6032
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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CPX-SP processor supports X2APIC.
Remove DMAR_X2APIC_OPT_OUT flag from DMAR table.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I63c9feda74c7abb591eac991cb98cdcad8afc158
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45375
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch uses the common code to avoid violating the PCH EDS
recommendation for the PchPmPwrCycDur setting.
Change-Id: I8aba558082ff5bbe2c5b12e0e623c013548e6481
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45030
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch uses the common code to avoid violating the PCH EDS
recommendation for the PchPmPwrCycDur setting.
Change-Id: Id418480bc779d56ff5586516d9bd99ca15133203
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45029
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add THERMCTL_LIMIT (die temperature limit) DPTC parameter
for clamshell/tablet mode.
BUG=b:157943445
BRANCH=zork
TEST=build
Change-Id: Id193a74210c92d1e45ed4824ee9c0fc9ceaa5e3a
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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USE_PSPSCUREOS -> USE_PSPSECUREOS.
Change-Id: I5c89975cc317cb93e79509e885010d14a79dd7e1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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List of changes:
1. Check if CSE is enabled from devicetree.cb
2. Create helper function cse_request_reset()
3. Modify caller function argument cse_request_global_reset()
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I3668b473bec8d51f847908d11e2e25c485ec7a97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45341
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The following parameters do nothing else than configuring the
corresponding pads to native mode:
- DdiPortEdp
- DdiPort*Hpd
- DdiPort*Ddc
- GpioDdp*
- SpiGpioAssign
- I2c*GpioAssign
- SerialIoUartDebugEnable
- Gp*GpioAssign
- Uart*GpioAssign
- GpioEnableHdaLink
- AudioLinkDmic*
- AudioLinkSsp*
- GpioEnableHdaSspMasterClock
- AudioLinkSndw*
- SmbAlertEnable
Add the missing special function gpio pad groups for CNL, to be able to
configure them via gpio.h instead having to set various FSP parameters.
The groups and names are documented in the PCH EDS, in Linux
(linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places.
Also, see soc/intel/tigerlake for reference.
Change-Id: Ia3bc1df1a14dbca7c7213577cb2d5b98bb0acf64
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux
(linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places.
Also, see soc/intel/tigerlake for reference.
Change-Id: I59df09c8fd464e75f918455aa1972765abc51459
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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platforms
BUG=b:145958015
TEST= Build Volteer coreboot and boot on Volteer Proto 2 and Delbin.
Cq-Depend:chrome-internal-review:3249528
Change-Id: I0ff896424ab23dba43075c44eb9b2c2c480ccbfb
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Clean up configuration of the legacy UART and add Kconfig options for
the mapping between UART and legacy I/O decode.
BUG=b:143283592
BUG=b:153675918
TEST=Linux detects an additional legacy serial port for each active MMIO
one if PICASSO_UART_LEGACY is selected.
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id08ff6428d4019303ebb6e44e13aba480cf1fde2
Reviewed-on: https://chromium-review.googlesource.com/2037891
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This corrects the GPIO community numbers in CNL-LP ACPI code.
Change-Id: I9f13a28d3e8f427859570a4d209304ae8444efd9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45209
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Found-by: Klocwork, Pointer soc_config is used uninitialized.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I7e2aa4ef23a68a2ec2ba9d55cf890a7f81e3e278
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Found-by: Klocwork, Avoid NULL pointer (ctx) dereference.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I16015b538112e0b125b4a5e145c26263c456953c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45411
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: If16d244e07d9f369efd991132587a92e38200b45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Using common mtcmos code to power on audio and display modules in SOC.
TEST=Boots correctly on MT8192EVB. Passes the status check at the end of
mtcmos_power_on()
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ie7bff831eecfc2b4d315a577f6ff86befc483eab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45394
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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add dptc support for different power parameter on tablet/clamshell mode
The BIOS may choose to adjust power and/or thermal parameters at its own
discretion. The DPTC interface(DPTCi) ALIB Function adds flexibility by
allowing the BIOS to request power state changes independently of specific
events.
BUG=b:157943445
BRANCH=none
TEST=Build.Generated ASL code from SSDT by acipgen_dptci().check the setting changed.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Icae94103f254f8fdb84e6ee0f5404fb09fa97b2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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If a given PRMRR size is not supported, do NOT brick people's devices.
We don't do that when PRMRRs aren't even supported anyway.
Change-Id: Ib917be873aedbc5e789bb0894fca335b5ee9e2c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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The register number is always non-negative, so it should be an unsigned
type.
Change-Id: I6b6df5a41fe58efc53eaa87c01b88426ea8daa6e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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data_fabric.c uses types from stdint.h, but doesn't include stdint.h
directly, so replace the inclusion of stdbool.h with types.h which
includes both stdbool.h and stdint.h.
Change-Id: I4c1ea444e50218cf19fc8fff499929336265bd03
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
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Reorder to be similar to cpx/include/soc/pci_devs.h.
We may be able to merge the files in the future.
Checked TiogaPass with BUILD_TIMELESS=1
Change-Id: I939707cc9e58e23f053156f40df4c21a6072570b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45220
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I8fc4e07269175eb2f40655b828e340697a9a892a
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45219
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The power status bits of display and audio of MT8192 are different
from the bits of MT8173 & MT8183, so move those under each chip.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Iaa211b8db733d8aa52d93af9e507042bf0984d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Memory speed is given as an integer in MHz. In some cases it has
an implicit fractional speed, so simply multiplying by 2 is not
sufficient.
Use method from dram/ddr4.c instead.
BUG=b:167155849
TEST=Boot ezkinil, check output of 'mosys memory spd print all'
and dmidecode -t17
BRANCH=Zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Icc77c21932c68ee9f0ff0b8e35ae7b1a3732b322
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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add WATCHDOG_TOMBSTONE in memlayout.ld
Change-Id: I57ece39ff3d49f2bab259cbd92ab039a49323119
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This I/O region is already covered by the range declared right above the
deleted one.
Change-Id: I8b8ff3385bbba8e69101ee2c5a5cb39c8f996b94
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This I/O region is already covered by the range declared right above the
deleted one.
TEST=Linux stops complaining about overlapping I/O regions.
BRANCH=zork
Change-Id: I149fb0dc85bfe721a6b0d81e4e9c197194718876
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45368
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Add SA EDS document number and chapter number
4. Fill required FSP-M UPD to call FSP-M API
Change-Id: I4473aed27363c22e92e66cc6770cb55aae83e75c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This fixes commit 1b89f5e "Guard options with if-blocks".
The code no longer returns if SGX is disabled, but as the PRMRR
configuration is missing it runs into die().
Tested on Prodrive Hermes: Boots again into Linux.
Change-Id: I6d32ca32b1b53767b2db91305103cd532823a5ca
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch adds a check to avoid violating the PCH EDS recommendation
that the PchPmPwrCycDur will never be smaller than the the SLP_Sx
assertion widths.
This code was initially added for cannonlake and now moving it to common
code since the same check will be used to program the PchPmPwrCycDur
for Jasperlake and Tigerlake.
Change-Id: Ie7d5f54939c5eb1f885d303f75a04958b9d77f4d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45028
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As the UART clock frequency is no longer required by the UART
driver, remove the unwated frequency.
Tested: Compile and boot up testing.
Change-Id: I137682b3ca45481ad34ac8ddb5cd308444f752a7
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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To achieve 115200 baudrate QcLib reconfigures UART frequency
with the lowest supported frequency from QUP clock table.
With this console logs were getting corrupted at qclib stage.
In ChromeOS coreboot, baudrate is configuarable using Kconfig.
QcLib should not assume the baudrate and reconfigure any UART
register once after the configuration is done in coreboot.
To fix the issue QcLib done the changes to not to reconfigure
any UART registers. Hence clock_configure_qup() is not required
in coreboot UART driver.
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Change-Id: I2531b64eddfa6e877f769af0d17be61f5e4d0c35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Enabling Bus Master isn't required by the hardware, so we shouldn't need
to enable it at all. However, some payloads do not set this bit before
attempting DMA transfers, which results in boot failures.
Replace static sata_final() implementation for BM enabling with generic
pci_dev_request_bus_master() function.
This allows the user to control through Kconfig whether Bus Master
should be enabled.
TEST=Able to boot to OS from SATA device on CML platform.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Icd086184fd6fa9c03c806c857f13fad5a9e78a3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Removed unused header files in chip.h
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Idb9b1ed23df3dbb9dad4d36651064c21a4d913fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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List of changes:
1. Convert inconsistent white space into tab.
2. Group together all MCHBAR offset macros.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ief13406b0116ce0f0b7472e5b133b3fac06f6e27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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PMC core OS driver (intel_pmc_core.c in linux kernel) provides debug
hooks to developers and end users to quickly figure out why their
platform is not entering a deeper idle state such as S0ix.
Include the common pmc.asl added in commit 957481c.
Test: PMC gets detected by Linux kernel module.
Change-Id: Ibf7c8ba7449df15c2ca30d23791e17fc878204f2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45318
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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I plan on adding another eMMC parameter. This refactor keeps the config
contained in a single struct.
BUG=b:159823235
TEST=Build test
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4b57d651ab44d6c1cad661d620bffd4207dfebd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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We added transfer_info_struct to contain various information about
memory region we pass from PSP to x86 in commit 0c12abe462.
This should be at the start of transfer region but we only manipulated
it as local variable and didn't put data into the region, resulting
garbage data for transfer_info when x86 tries to read it.
Copy the content of local variable to beginning of _transfer_buffer
before requesting transfer to PSP so coreboot on x86 can access it.
BUG=b:159220781
BRANCH=zork
TEST=check transfer_info_struct is correctly populated on romstage
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I14bc34e6af501240a6f633db3999a7759e88d60b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44751
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Before MRC code execution, FSP interrogates EMCA MSR registers and other
registers to see if there are fatal errors happened during previous boot
session. If there are, error records are saved into
FSP_PREV_BOOT_ERR_SRC_HOB.
When the value of Length field of FSP_PREV_BOOT_ERR_SRC_HOB is 2, that means
the HOB does not contain any valid error record.
TESTED=Injects MCE error through cscript, reboot into OS, check boot log:
0x75904d70, 0x00000400 bytes: HOB_TYPE_GUID_EXTENSION
5138b5c5-9369-48ec-5b9738a2f7096675: FSP_PREV_BOOT_ERR_SRC_HOB_GUID
================ PREV_BOOT_ERR_SRC HOB DATA ================
hob: 0x75904d88, Length: 0x42
MCBANK ERR INFO:
Segment: 0, Socket: 0, ApicId: 0x0
McBankNum: 0x3
McBankStatus: 0xfe00000000800400
McBankAddr: 0xf0ff
McBankMisc: 0xfffffff0
MCBANK ERR INFO:
Segment: 0, Socket: 0, ApicId: 0x0
McBankNum: 0x4
McBankStatus: 0xfe00000000800400
McBankAddr: 0xfff0
McBankMisc: 0xfffffff0
0x75904d88: 42 00 01 00 00 00 00 00 03 00 00 04 80 00 00 00 B...............
0x75904d98: 00 fe ff f0 00 00 00 00 00 00 f0 ff ff ff 00 00 ................
0x75904da8: 00 00 01 00 00 00 00 00 04 00 00 04 80 00 00 00 ................
0x75904db8: 00 fe f0 ff 00 00 00 00 00 00 f0 ff ff ff 00 00 ................
0x75904dc8: 00 00
Change-Id: Idbace4c2500440b3c1cf2628dd921ca1a989ae81
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44974
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix
cbmem buffer overflow issue.
Bug=None
Branch=None
Test=Boot TGLRVP and check cbmem -c | grep 'CBFS: Locating' lists all stages
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I2393cc83008211be8e6a2ca7a1e41a7e9d92caf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45183
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects Cache QoS mask MSR programming flow for Tigerlake SoC.
BUG=b:145958015
TEST= Build and boot to Chrome OS on TGL-UP3 RVP.
Recipe used:
1. Patch https://review.coreboot.org/c/coreboot/+/43494 that
implements calculation of CQOS mask dynamically based on stack
size usage & incorporates Tigerlake SoC specific programming flow.
2. QS Engineering Microcode based on 0x56 Official Microcode with
LLC CQOS change.
3. QS SoC Part
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I602d93eb4f8243ec49993b00691140d9a6cf5733
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Update the COS mask calculation to accomodate the RW data as per SoC
configuration. Currently only one way is allocated for RW data and
configured for non-eviction. For earlier platform this served fine,
and could accomodate a RW data up to 256Kb. Starting TGL and JSL, the
DCACHE_RAM_SIZE is configured for 512Kb, which cannot be mapped to a
single way. Hence update the number of ways to be configured for non-
eviction as per total LLC size.
The total LLC size/ number of ways gives the way size. DCACHE_RAM_SIZE/
way size gives the number of ways that need to be configured for non-
eviction, instead of harcoding it to 1.
TGL uses MSR IA32_CR_SF_QOS_MASK_1(0x1891) and IA32_CR_SF_QOS_MASK_2(0x1892)
as COS mask selection register and hence needs to be progarmmed accordingly.
Also JSL and TGL platforms the COS mask selection is mapped to bit 32:33
of MSR IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32)
before MSR write instead of eax(maps 31:0). This implementation corrects
that as well.
BUG=b:149273819
TEST= Boot waddledoo(JSL), hatch(CML), Volteer(TGL)with NEM enhanced
CAR configuration.
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I54e047161853bfc70516c1d607aa479e68836d04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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That devicetree setting is about the Audio Co-Processor and not ACPI.
BRANCH=zork
Change-Id: I7f376371ee094392d4434340c77f0fc8d0d8e4e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The AOAC device number is never negative, so make it unsigned.
BRANCH=zork
Change-Id: I3e0d15a646f02da5767504471961d5d9f8f28bea
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45308
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change is separate from CB:45308 to only have the directly UART-
related changes in this patch train.
BRANCH=zork
Change-Id: Ie587fdbd1e6229c1374fce3568c6a361577dc6c4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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BRANCH=zork
Change-Id: I51923d72a2ad8dceeef11e15fb6765262dd514d9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The usual structure of these files is a global enable symbol, usually
followed by an if-block which contains all other dependent symbols.
Use this instead of having a `depends on` line to each symbol. Guard all
symbols, even if they originally were not guarded, since they don't do
anything useful unless the global enable option is selected.
Change-Id: If5347187b07a46192f0063011ab197b5047f555f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45043
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Include console/uart.h for the declaration of uart_platform_base instead
of declaring the function in the source file.
Change-Id: Ib72d8884f27e93cec058dbcda404dd6908de1981
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The UART index is never negative, so make it unsigned and drop the
checks for the index to be non-negative.
Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The UART index is never negative, so make it unsigned and drop the check
for the index to be non-negative.
BRANCH=zork
Change-Id: I38b5dad87f8af4fbe8ee1d919230efe48f68686c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Fix TSC frequency calculation per Picasso PPR. This code was copied
from Stoney and was incorrect for Picasso.
BUG=b:163423984
TEST=verify Dalboz TSC to be 1GHz
BRANCH=zork
Change-Id: Ibe3f49c7d295e7336ee042da2b94823171b6eb55
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Calling espi_open_generic_io_window in espi_open_io_window depends on
the condition in the preceding if statement, so move the command into an
else block to make it more obvious that this is the case.
TEST=Timeless build results in identical image.
Change-Id: I3039817afd79c30a2df2f2f54e7848f52dc2c487
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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List of changes:
1. Convert inconsistent white space into tab.
2. Group together all MCHBAR offset macros.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I82fc362589389081b1b1856524a972b780af9a13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45256
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move APCB generation out of the picasso makefile and into the mainboard
makefile. APCB generation tends to be mainboard specific and does not
belong in the soc makefile.
BUG=b:168099242
TEST=Build mandolin and check for APCB in coreboot binary
Build and boot ezkinil
Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the missing entry using new Kconfig symbol for IOAPIC ID. coreboot
will always enable the GNB IOAPIC.
Cq-Depend: chrome-internal:3247431, chrome-internal:3253044
BUG=b:167421913, b:166519072
TEST=Boot fully to morphius board with and without amd_iommu kernel
parameter. Dump MADT and IVRS tables. Cross check ioapic entries
in MADT against IVRS.
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: Ic4a2e9b71dba948e8a4907e5f97131426d8a4a3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45056
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Kconfig symbols for the FCH and GNB IOAPIC IDs, then pass
the info to FSP to keep it in sync with coreboot. Do the same
for the northbridge's IOAPIC base address.
Use the new values where needed, and reserve the resources
consumed by the GNB IOAPIC.
BUG=b:167421913, b:166519072
TEST=Boot Morphius and verify settings
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45115
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia419de14614a7a1b583e0870e9ca2fcdc8cf815a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Rename the pch_init function to bootblock_pch_init to
maintain the parity with previous generation SoC code block.
Refer to commit 1201696.
Change-Id: Id2a89b2f64b58079062d79e07efbdcfad7ed3d2d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45189
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch converts inconsistent white space into tab.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: If5e191b92e3e53b43335136ef51bc62589b955a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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Add sc7180 display hardware pipeline programming support
and invoke the display initialization from soc_init.
Changes in V1:
- added display init required check.
- added edid read function using i2c communication.
- added sn65dsi86 bridge driver to init bridge.
- moved display initialization to mainboard file.
Changes in V2:
- moved diplay init sequence to mainboard file
- moved edid read function to bridge driver.
- calculated timing paramters using edid parameters.
- removed command mode config code.
- moved bridge driver to drivers/ti.
- seperated out bridge and soc code with mainboard file as interface.
Changes in V3:
- add GPIO selection at runtime based on boardid.
- add vbif register struct overlay.
Changes in V4:
- update gpio config for lazor board.
Change-Id: I7d5e3f1781c48759553243abeb3d694f76cd008e
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This change adds support for sc7180 dsi interface host programming.
Changes in V1:
- remove dual dsi config code.
- update register access using struct overlays.
- remove dsc config & command mode code.
Changes in V2:
- remove dsi read and write functions.
- remove target and panel related code.
Changes in V3:
- move prototypes to headers.
- define macros for constants.
Changes in V4:
- define register bits instead of hardcoded values.
Change-Id: Ie64354ce8bc2a64b891fb9478fbca38d6ec4c321
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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