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2023-01-15soc/intel/xeon_sp/Kconfig: set up HPET_MIN_TICKSTim Chu
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I3256c3c6a4ea331efae00d78192355a1fd78d6d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-15soc/intel/xeon_sp: lock MSR_PPIN_CTL at BS_PAYLOAD_LOADTim Chu
MSR_PPIN_CTL may need to be read more than once, so lock PPIN CTL MSR at a late BS_PAYLOAD_LOAD boot state. This MSR is in platform scope and must only be locked once on each socket. Add a spinlock to do so. Tested=On OCP Craterlake single socket, rdmsr -a 0x04e shows 1. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: I8deb086339267cf36e41e16f189e1378f20b82f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-15soc/amd/mendocino: PSP_INCLUDES_HSPKarthikeyan Ramasubramanian
Select HSP config to indicate that the SoC includes Hardware Security Processor. This will allow PSP verstage to get and report the HSP state. BUG=None TEST=Build Skyrim BIOS image and boot to ChromeOS on Skyrim. Verify that HSP is reported during the boot sequence. Change-Id: I22446c2bd6202529367da040c09449e6b26f9d7a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-15soc/amd/common/psp_verstage: Report HSP Secure StateKarthikeyan Ramasubramanian
Get Hardware Security Processor(HSP) state in PSP Verstage through the SVC call and report it in cbmem logs. BUG=b:198711349 TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Change-Id: Ic4875d1732f22783a90434329188192b106168f4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-15vc/amd/*,soc/amd/*: Add SVC call to get HSP Secure StateKarthikeyan Ramasubramanian
Add an SVC call to get the state of Hardware Security Processor (HSP) in AMD SoCs. This SVC call will be used from PSP verstage to get and report HSP state. BUG=b:198711349 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the HSP state is read and reported in the firmware logs. Change-Id: I7fe3363d308a80cc09e6bdadd8d0bb1d67f7d2bf Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71207 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-15soc/amd/mendocino/include/acpi,lpc: remove TODO after reviewFelix Held
Remove TODO comment after checking against Mendocino PPR #57243, rev 3.02. BUG=b:263563246 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie0e35f4c68ec09304eb892888759c7e5ef3dd0ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/71911 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-15soc/intel/common: Use 'enum cb_error' valuesSridhar Siricilla
The patch uses 'enum cb_error' values as return values for below functions: 1. cse_get_rw_rdev() 2. cse_erase_rw_region() 3. cse_write_rw_region() 4. cse_locate_area_as_rdev_rw() 5. cse_get_target_rdev() 6. cse_copy_rw TEST=Build, boot and perform CSE downgrade test on the Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I9c664430a5015d37b9c329f85886f8622deaa497 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15soc/intel/common: Use 'enum cb_err' valuesSridhar Siricilla
The patch uses cb_err enum values as return values for function cse_get_boot_performance_data() instead of true/false. TEST=Build code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I0153d5496c96fb0c2a576eef1fe2fa7fa0db8415 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15soc/intel/common: Use enum cb_err valuesSridhar Siricilla
The patch uses cb_err enum values as return values for below functions: 1. cse_hmrfpo_enable() 2. cse_boot_to_ro() 3. cse_prep_for_rw_update() 4. cse_sub_part_get_target_rdev() 5. cse_get_sub_part_fw_version() 6. cse_prep_for_component_update() Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I1bdb7d6b2051a69f1021673d464bfad63dd39431 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-13soc/amd/phoenix: update mmconf base address and sizeRitul Guru
0xF8000000 was taken from old platform during phoenix porting, updating it to 0xE0000000 to make room for 256 pci busses which is required for usb4 and hotplug support. mmconf size gets set to 0x10000000 when 256 busses are used. Change-Id: Ic143171f5650aff5db48c8f477d7aca3e7f5c1e7 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71870 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13soc/amd/glinda: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I62b15d59cc4a5f214e45c3995f651228b1ae6ea7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71900 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd/phoenix: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie7ded68f4732ec12a1c7e59445d572763a03c3b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71879 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd/mendocino: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ief1e9c6d6fa0889b947863837bedb2fbdf3120c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71878 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd/cezanne: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b9f1b71a5f8b2776c8b338351b2cca723d00598 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71877 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd/picasso: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iedd99cfb64809c4e111e0931c2260981f465035b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd: introduce common SMU S3/4/5 entry message codeFelix Held
The smu_sx_entry function is identical for all AMD SoCs, so introduce it as common code that can be selected to be included in the build via the SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY Kconfig option. The only SoC-specific difference in this function is the ID of the SMC_MSG_S3ENTRY message which is defined in each SoC's soc/smu.h include file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I49758e9333a351d8e50e8f1b53a7f00fbe89866c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71875 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd/glinda: Use common fsp-s preloaderFred Reitberger
Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I32f8ca02c4de9e882f207c2dd2378b6b44dc61ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/71848 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13soc/amd/phoenix: Use common fsp-s preloaderFred Reitberger
Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Iea7011d37667f3f04ce842038346741fba66b1dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71847 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13soc/mediatek: Include <gpio.h> instead of <soc/gpio.h>Elyes Haouas
<gpio.h> chain-include <soc/gpio.h>. Change-Id: If2af7f77e2d910a3f3470d15dbfc98775a2633b6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2023-01-13soc/intel : Use 'enum cb_err' valuesSridhar Siricilla
Use 'enum cb_err' values for below cse lite functions instead of true or false. Functions whose return values updated in this patch: 1. cse_set_next_boot_partition() 2. cse_data_clear_request() 3. cse_set_and_boot_from_next_bp() 4. cse_boot_to_rw() 5. cse_fix_data_failure_err() TEST= Do boot test on Gimble. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I7fec530aeb617bab87304aae85ed248e51a6966b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-13soc/intel: Use 'enum cb_err' instead of boolSridhar Siricilla
The patch uses 'enum cb_err' values as return values for cse_get_bp_info() function. TEST=Build the code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I900e40b699de344f497e61d974bca3fee7f6ecbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12soc/amd/mendocino: Use common fsp-s preloaderFred Reitberger
Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I74ef10347c37c8371156f89da9f234d170ab1aa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71846 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd/cezanne: Use common fsp-s preloaderFred Reitberger
Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ibbed17445c3cd8fa4da671f2a90532d3c39ad08b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd/common/fsp: Introduce SOC_AMD_COMMON_FSP_PRELOAD_FSPSFred Reitberger
The function to start preloading the fsp-s is identical in cezanne and newer socs, so move it to common with a new Kconfig option to enable it. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia572c99928f4a60896b7a861ab6fb3f1257ac1cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd/mendocino/include/soc/southbridge.h: Use BIT macro for consistencyFred Reitberger
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I2dd17774b79c5adb64c2575ac55dec476c434842 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71843 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd/mendocino: Remove TODO after reviewFred Reitberger
Remove TODO comment after reviewing against mendocino ppr #57243, rev 3.00 BUG=b:263563246 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id517ce6e5f5bee5deffe509d748b16be0eefca96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-01-12soc/amd/mendocino/include/platform_descriptors: remove TODO after reviewFelix Held
This header file is correct for Mendocino, so remove the TODO. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85b47491863bff731b86cf0523253cb547dbb76a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71794 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/mediatek/common/mcu.c: Use 'enum cb_err' instead of 'int'Elyes Haouas
mtk_init_mcu() function already returns enum cb_err. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I562bfbdc5c917a17ce1aa656046b69eb56dce48c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2023-01-12soc/intel/common: Use enum csme_failure_reasonSridhar Siricilla
The patch updates return type for below functions as they uses 'enum csme_failure_reason' type return values. 1. cse_sub_part_trigger_update() 2. handle_cse_sub_part_fw_update_rv() 3. cse_sub_part_fw_update() TEST=Build coreboot code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I43bc2d518a275894860e4d3c930c3c4d9685fb3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71792 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/intel/skylake/Makefile.inc: Remove path to non-existent directoriesElyes Haouas
Fix: cc1: error: 3rdparty/blobs/mainboard/asrock/h110m: No such file or directory [-Werror=missing-include-dirs] cc1: error: 3rdparty/blobs/mainboard/acer/aspire_vn7_572g: No such file or directory [-Werror=missing-include-dirs] ... Change-Id: Icc43e40514a12944fa180197ffe3230ff9800de9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12soc/intel/braswell/Makefile.inc: Remove path to non-existent directoriesElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: I420b60341dfd0119b14e8492722af62e49fceff8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12treewide: Remove unused <cpu/x86/smm.h>Elyes Haouas
Change-Id: Iba5b39c6189d3224ba209c7985153701fe8896fb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12treewide: Remove unused <cpu/amd/mtrr.h>Elyes Haouas
Change-Id: Ibff33c08a1d583b19b205a66d5a4267df65ced75 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-123rdparty/amd_blobs:Advance submodule pointerJason Glenesk
This picks up the following changes: acf73954 phoenix: rename morgana to phoenix a2c15297 mendocino: Upgrade SMU to 90.35.166 28983855 Update Picasso FSP binaries This also updates the phoenix fw.cfg file that points to the submodule. Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1d04d6232307dc913645a3d60ac3711018e2bdfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/71803 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/amd: Change Morgana codename to PhoenixMartin Roth
Now that the next generation of APUs is officially announced, we can unmask morgana. The chip formerly known as Morgana is actually Phoenix. Surprise! This patch just changes the name across the entire codebase. Note that the fw.cfg file will stay pointing to the 3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is updated. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/intel/common/block/early_graphics: Introduce a 200 ms delayJeremy Compostella
It has been reported that the PEIM graphics driver may temporarily fail communication with the display if the time between libgfxinit turning off the displays and the PEIM driver initialization is too short. 200 ms has been identified as a safe delay. This is a temporary workaround and an investigation is in progress to come up with a better and long term solution. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Developer screen is systematically seen Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de1 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71656 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/intel/alderlake: Inform user of memory trainingJeremy Compostella
If memory training is going to happen and early graphics is supported by the mainboard, an on-screen text message is displayed to inform the end user. Memory training can take a while and an impatient end user facing a black screen for a while may reset the device unnecessarily. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=On screen text message during MRC training observed on skolas Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de0 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70300 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/intel/alderlake: Add romstage early graphics supportJeremy Compostella
BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Verify that VGA text mode is functional in romstage Change-Id: I727b28bbe180edc2574e09bf03f1534d6282bdb2 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70303 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/intel/common/block: Add Intel VGA early graphics supportJeremy Compostella
This patch introduces an early graphics driver which can be used in romstage in cache-as-ram mode. The implementation relies on `libgfxinit' and provide VGA text mode support. SoCs wanting to take advantage of this driver must implement the `early_graphics_soc_panel_init' function to set the panel power sequence timing parameters. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Graphics bring up observed on skolas with extra patches Change-Id: Ie4ad1215e5fadd0adc1271b6bd6ddb0ea258cb5b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70299 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11soc/intel/elkhartlake: Provide a way to enable real-time tuningWerner Zeh
Intel provides a Real-Time Tuning Guide for Elkhart Lake to improve real-time behaviour of the SoC (see Intel doc #640979). It describes, amongst knobs for the OS, a couple of firmware settings that need to be set properly to reduce latencies in all the subsystems. Things like clock and power gating as well as low power states for peripherals and buses are disabled in this scenario. This patch takes the mentioned UEFI parameters from the guide and translates them to FSP-M and FSP-S parameters. In addition, a chip config switch guards this tuning which can be selected on mainboard level if needed. When this real-time tuning is enabled, the overall system performance in a real-time environment can be increased by 2-3%. Change-Id: Ib524ddd675fb3ea270bacf8cd06cb628e895b4b6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-11soc/intel/meteorlake: Move ME firmware status register structures toDinesh Gehlot
pertinent header file This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarilly share the same SoC directory. BUG=b:260309647 Test=Able to build and boot Google/rex Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ib3dafd6c030c0c848aa82b03bb336cc8fad14de3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71627 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-11soc/intel/alderlake: Move ME firmware status register structures toDinesh Gehlot
pertinent header file This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarilly share the same SoC directory. BUG=b:260309647 Test=Able to build and boot Google/brya. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ic14305b0479a8c57531d9930946eded7ac518b09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71625 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11device/Kconfig: Fix selection of software connection managerMartin Roth
The patch that introduced the selection of software connection manager, CB:64561 - 060df17f1d (soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM) added a default to enable the software configuration manager directly in the choice. This leads to warnings when running make menuconfig: src/soc/intel/alderlake/Kconfig:439: warning: defaults for choice values not supported src/soc/intel/meteorlake/Kconfig:337: warning: defaults for choice values not supported src/soc/intel/tigerlake/Kconfig:299: warning: defaults for choice values not supported I'm not sure why the Kconfig linter didn't catch this, but this issue is currently breaking the build for me. This patch fixes it so that instead of setting the default directly, a new Kconfig value is selected that then sets the default correctly. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I674046a93af8f7c2f3003900804deefa89dae295 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71776 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-01-11treewide: stop calling custom TPM log "TCPA"Sergii Dmytruk
TCPA usually refers to log described by TPM 1.2 specification. Change-Id: I896bd94f18b34d6c4b280f58b011d704df3d4022 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-01-11soc/intel/xeon_sp: Setup DPR for all VT-d devicesJonathan Zhang
The Data Protected Range (DPR) needs to be set for all DPR devices, not only the root device. Separate the setup from the memory resource map reservation. Change-Id: I7e49db23960e3938e8e158082be3c5ecf3cf95f3 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-11soc/intel/{alderlake,tigerlake}: Fix typo in gpio_defs.hJakub Czapiga
Alder Lake and Tiger Lake had unnecessary lower-case 'i' in GPP_C0_IRQ define name. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ida892b00e5a28544950cb9863d0ff2408a514576 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71819 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-01-11drivers/intel/gma: Hook up libgfxinit in romstageJeremy Compostella
A mainboard port needs to: - select `CONFIG_MAINBOARD_HAS_EARLY_LIBGFXINIT' - implement the Ada package `GMA.Mainboard' with a single function `ports' that returns a list of ports to be probed for displays. - set the desired `GFX_GMA_DEFAULT_MMIO' IO memory address to use in romstage (and ramstage) for the graphic device. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=libgfxinit compiles in romstage. libgfxinit successfully executes in romstage and ramstage using the requested MMIO setting on skolas. Change-Id: I3c2101de10dc5df54fe873e43bbe0f1c4dccff44 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70276 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11soc/intel/meteorlake: Define SA_DEV_IGD for common codeJeremy Compostella
SA_DEV_IGD is used by the early graphics feature implemented by the Intel common block. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Compilation Change-Id: Ic9f0fe1683d55a53c705ae717fe9e40fd8873d1f Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-11soc/intel/elkhartlake/chip.h: Include types.h instead of stdint.hWerner Zeh
As the used 'bool' type is defined in stdbool.h, include types.h (instead of stdint.h) which includes all needed header files. Change-Id: I3f75776575a7a5f70484411b9f3458530f706ec4 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71790 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10soc/amd/common/fsp/Makefile: Fix an error messageAkihiko Odaki
It used to say "FSP-M binary larger than FSP_M_FILE", but FSP_M_FILE is the binary itself. The binary file size is actually compared with FSP_M_SIZE. Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com> Change-Id: If58069944aea8e68117f2ee1d320726d8c6fdfc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65440 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-10soc/intel: Add Kconfigs to define scaling factor for coresSridhar Siricilla
The patch adds Kconfigs to define scaling factor for Efficient and Performance cores instead of using hard coded values in the soc code. Also, the patches uses the Kconfigs directly to calculate the core's nominal performance. So, we don't need to implement soc function soc_get_scaling_factor() to get the scaling factor data for different core types. Hence, soc_get_scaling_factor() function is removed. TEST=Build the code for Gimble and Rex. Also, I have verified that build system logs error when the Kconfigs are undefined. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I55e4d815116ef40c5f33be64ab495e942bf35ee8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71687 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10soc/intel/meteorlake: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes with the common gpio.h which will include soc/gpio.h which will include intelblocks/gpio.h which will include soc/gpio_defs.h BUG=b:261778357 TEST=Able to build and boot Google/rex. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I58e428cde5e13f4f0dfe528d798c0613b7f8a94a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71630 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-10soc/mediatek/common: Reset the watchdog timer before triggering resetRunyang Chen
When the watchdog timer reaches 0, the timer value won't reset to the default value unless there is an external reset or a kick. It will result in the watchdog failing to trigger the reset signal. We kick the watchdog to reset the timer to the default value. Also, because WDT hardware needs about 94us to synchronize the registers, add a 100us delay before triggering the reset signal. BUG=b:264003005, b:264017048 BRANCH=corsola TEST= Reboot successfully with the following cmd stop daisydog sleep 60 > /dev/watchdog& Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Signed-off-by: Kuan-Hsun Cheng <allen-kh.cheng@mediatek.com> Change-Id: Ic4964103d54910c4a1e675b59c362e93c2213b19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71754 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10soc/intel/elkhartlake: Make SATA speed limit configurableWerner Zeh
In cases where there are limitations on the mainboard it can be necessary to limit the used SATA speed even though both, the SATA controller and disk drive support a higher speed rate. The FSP parameter 'SataSpeedLimit' allows to set the speed limit. This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I610263b34b0947378d2025211ece4a9ec8fbfef6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71229 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-01-09treewide: Remove unused <cpu/amd/msr.h>Elyes Haouas
Change-Id: Id24a7c7db24f49672df9d5ceefec5b7596f23e09 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/amd: Remove dummy SOC_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I080b7b579338c3cf342beabda54f43f525d8b65c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/amd/morgana: Double max number of cpus for morganaRitul Guru
Change-Id: I5169a900345e2aabefcf1e2c249ee4bce6dc8fc5 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/amd/morgana: update morgana cpuidRitul Guru
Change-Id: Ieaad72a6b964f4b2ab572733694def88e30888a3 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/amd/mendocino/Kconfig: Remove TODO after reviewFred Reitberger
Remove TODO comments after reviewing against mendocino ppr #57243, rev 3.00 BUG=263563246 TEST=build skyrim Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ie56d481dd8b6b4e0a1e3d50f4ce75f50231fe4dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09soc/amd/common/block/graphics: Fix whitespace consistencyFred Reitberger
Replace spaces with tabs for consistency. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I65b9bec7443094dfd2f6b0d6b11e0100023873b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/intel/xeon_sp/skx: Remove nested check for ACPI supportMarc Jones
Remove redundant nested check for ACPI support. Change-Id: Ie4b40382d304028135bcdd7851e2f48333570421 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-09soc/intel/common: Fix cpu index calculationSridhar Siricilla
get_cpu_index() helper function returns cpu's index based on it's APIC id position from the ascending order list of cpus' APIC IDs. In order to calculate the cpu's index, the helper function needs to traverse through each cpu node to find their APIC IDs. So, the function traverse the CPU node list from the cpu whose APIC ID is 0 assuming it is the first cpu node in the list. This logic works fine where BSP's APIC ID is 0. But, starting from MTL, APIC ID for BSP need not be 0 as APIC ID numbering first get assigned for CPU Die Efficient cores, then Performance cores. Please refer section# 6.1 of doc#643504 for more details on APIC IDs. Considering the APIC Id allotment for MTL cores, as existing code traversing begins from the cpu that has APIC Id#0 which may not be the first cpu node in the list so index calculation results in wrong value. The patch addresses above described issue by traversing all the CPU nodes to calculate the cpu index. Also, prevents inconsistent report of /sys/devices/system/cpu/cpu*/cpufreq/* and /sys/devices/system/cpu/cpuXX/acpi_cppc on each reboot. TEST=Verified that the get_cpu_index helper function returns the correct index id for a CPU on Rex. The coreboot log with code instrumentation, before this patch: [DEBUG] my_apic_id:0x10 cpu_index: 0x6 [DEBUG] my_apic_id:0x11 cpu_index: 0x6 [DEBUG] my_apic_id:0x42 cpu_index: 0x6 [DEBUG] my_apic_id:0x21 cpu_index: 0x6 [DEBUG] my_apic_id:0x40 cpu_index: 0x6 [DEBUG] my_apic_id:0x31 cpu_index: 0x6 [DEBUG] my_apic_id:0x39 cpu_index: 0x6 [DEBUG] my_apic_id:0xa cpu_index: 0x3 [DEBUG] my_apic_id:0x0 cpu_index: 0x0 [DEBUG] my_apic_id:0x8 cpu_index: 0x2 [DEBUG] my_apic_id:0x4 cpu_index: 0x2 [DEBUG] my_apic_id:0x28 cpu_index: 0x6 [DEBUG] my_apic_id:0x2 cpu_index: 0x1 [DEBUG] my_apic_id:0x38 cpu_index: 0x6 [DEBUG] my_apic_id:0x29 cpu_index: 0x6 [DEBUG] my_apic_id:0xe cpu_index: 0x5 [DEBUG] my_apic_id:0x6 cpu_index: 0x2 [DEBUG] my_apic_id:0x20 cpu_index: 0x6 [DEBUG] my_apic_id:0x30 cpu_index: 0x6 [DEBUG] my_apic_id:0x19 cpu_index: 0x6 [DEBUG] my_apic_id:0xc cpu_index: 0x4 [DEBUG] my_apic_id:0x18 cpu_index: 0x6 We can see same cpu_index for multiple cores before fix. After this patch.. [DEBUG] my_apic_id:0x10 cpu_index: 0x8 [DEBUG] my_apic_id:019 cpu_index: 0xb [DEBUG] my_apic_id:0x11 cpu_index: 0x9 [DEBUG] my_apic_id:0x18 cpu_index: 0xa [DEBUG] my_apic_id:0x40 cpu_index: 0x14 [DEBUG] my_apic_id:0x30 cpu_index: 0x10 [DEBUG] my_apic_id:0x42 cpu_index: 0x15 [DEBUG] my_apic_id:0xc cpu_index: 0x6 [DEBUG] my_apic_id:0x2 cpu_index: 0x1 [DEBUG] my_apic_id:0x29 cpu_index: 0xf [DEBUG] my_apic_id:0xe cpu_index: 0x7 [DEBUG] my_apic_id:0x20 cpu_index: 0xc [DEBUG] my_apic_id:0x0 cpu_index: 0x0 [DEBUG] my_apic_id:0x31 cpu_index: 0x11 [DEBUG] my_apic_id:0x28 cpu_index: 0xe [DEBUG] my_apic_id:0x21 cpu_index: 0xd [DEBUG] my_apic_id:0xa cpu_index: 0x5 [DEBUG] my_apic_id:0x38 cpu_index: 0x12 [DEBUG] my_apic_id:0x8 cpu_index: 0x4 [DEBUG] my_apic_id:0x4 cpu_index: 0x2 [DEBUG] my_apic_id:0x39 cpu_index: 0x13 Change-Id: I69e5e6231dd18b43d439340aaed50eb9edeca3b7 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70751 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-09soc/intel/alderlake: Disable Intel TXT based on `INTEL_TXT` configSubrata Banik
This patch makes the call into TXT lib in order to disable the TXT if SoC user haven't selected the `INTEL_TXT` config. Disabling TXT would be helpful to access VGA framebuffer prior calling into FSP-M. TEST=Able to perform disable_txt and unlock memory which helped to access VGA framebuffer prior calling into FSP-M. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9dd7c5492a5f45eef0dd9e836cc2da1844c78919 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71575 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-08soc/intel/common: Untie PRMRR from SGXPratikkumar Prajapati
PRMRR is used by many Intel SOC features, not just Intel SGX. As of now SGX and Key Locker are the features that need PRMRR. Untie it from Intel SGX specific files and move to common cpulib. Also rename PRMRR size config option. Use the renamed PRMRR size config option to set the PRMRR size. TEST=Able to set PRMRR size using config. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I0cd49a87be0293530705802fd9b830201a5863c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70819 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-08soc/intel/xeon_sp: select SCO_INTEL_COMMON_BLOCK_TCOJohnny Lin
Also disable TCO timer through calling tco_configure(). If tco_configure() is not called, the TCO timeout would trigger SMI periodically about every 2 seconds with SMM log: "TCO_STS: BIT18 TIMEOUT" Tested=On AC CRB, does not see periodic SMI log. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I2d307ad16109ae11862dd5e5acc0f12f47b22582 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2023-01-08soc/intel/xeon_sp: Improve final MTRR solutionJonathan Zhang
If cbmem_top is not 1M aligned there will be a hole between DPR base and cbmem_top that the allocator will consider as unassigned memory. Resources could incorrectly be assigned to that region and the final MTRR solution will also try to skip that hole, therefore using a lot more variable MTRRs than needed. TESTED on Archer City 2S system: Uses 1 variable MTRR in the final setup instead of 7. Change-Id: I198f8d83bcfcdca3a770bd7f9a7060d5782a49fe Signed-off-by: Arthur Heymans <arthur.heymans@9elements.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2023-01-08soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCMSean Rhodes
Software Connection Manager doesn't work with Linux 5.13 or later, resulting in TBT ports timing out. Not advertising this results in Firmware Connection Manager being used and TBT works correctly. Add Kconfig options to chose between SCM (Software Connection Manager) and FCM (Firmware Connection Manager). FCM is primary, as it's more compatible save for ChromeOS devices as ChromeOS uses SCM. Linux patch: torvalds/linux@c6da62a c6da62a219d028de10f2e22e93a34c7ee2b88d03 Tested with StarBook Mk VI (i7-1260P). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iac31d37c0873f41f7b14e1051fe214466d1ebdd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-08soc/intel/meteorlake: Add support to configure package c-state demotionKapil Porwal
This patch adds the support to enable/disable package c-state demotion feature from the devicetree based on mainboard requirement. Port of commit 4be8d9e80deb ("soc/intel/adl: Add support to configure package c-state demotion") BUG=none TEST=Boot to the OS on Google/Rex. Snippet from FSP log: [SPEW ] PkgCState Demotion : 0x1 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I0a4b0b181349ce41035524482add4336cf83a68b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-08soc/intel/meteorlake: Set max Pkg C-states to AutoKapil Porwal
This patch configures max Pkg C-state to Auto which limits the max C-state to deep C-state. Port of commit af42906efa72 ("soc/intel/alderlake: Set max Pkg C-states to Auto") BUG=none TEST=Boot to the OS on Google/Rex. Snippet from FSP log: [SPEW ] PkgCStateLimit : 0xFF Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ic403ab83a594b04920d5cf600432939687a2598b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-06soc/intel/: Rename small and big cores referencesSridhar Siricilla
The patch addresses Intel heterogeneous cores as `Efficient` and `Performance` cores instead of `small` and `big` cores. It is to ensure coreboot code has uniform reference to the heterogeneous cores. So, the patch renames all `small` and `big` core references to `efficient` (eff) and `performance` (perf) cores respectively. TEST=Build the code for Brya and Rex boards Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I98c9c0ed86b211d736a0a1738b47410faa13a39f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71639 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-01-06soc/intel/common: Check PRMRR dependent featuresPratikkumar Prajapati
Add below mentioned functions: is_sgx_configured_and_supported(): Checks if SGX is configured and supported is_keylocker_configured_and_supported(): Checks if Key Locker is configured and supported check_prm_features_enabled(): Checks if any of the features that need PRM are configured and supported. As of now SGX and Key Locker are the only features that need PRM. Also, call check_prm_features_enabled() from get_valid_prmrr_size() to make sure PRM dependent features are enabled and configured before returning PRMRR size. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I51d3c144c410ce4c736f10e3759c7b7603ec3de9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-06soc/intel/common: Add Kconfig option for Intel Key LockerPratikkumar Prajapati
Add INTEL_KEYLOCKER Kconfig option. Disable it by default. The specification of Key Locker can be found via document #343965 on Intel's site. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: Ia78e9bfe7ba2fd4e45b4821c95b19b8e580dccab Reviewed-on: https://review.coreboot.org/c/coreboot/+/71118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-06soc/intel/meteorlake: Enable support for common IRQ blockKapil Porwal
Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch allows MTL boards to dynamically assign PCI IRQs. This means not relying on FSP defaults, which eliminates the problem of PCI IRQs interfering with GPIO IRQs routed to the same IRQ, when both have selected IO-APIC routing. BUG=none TEST=Build and boot to google/rex. Check dmesg and make sure that there is no regression. IO-APIC interrupts before: 1: IO-APIC 1-edge i8042 8: IO-APIC 8-edge rtc0 9: IO-APIC 9-fasteoi acpi 14: IO-APIC 14-fasteoi INTC1083:00 16: IO-APIC 16-fasteoi idma64.5, ttyS0, intel-ipu6 28: IO-APIC 28-fasteoi idma64.6, pxa2xx-spi.6 29: IO-APIC 29-fasteoi i2c_designware.3 30: IO-APIC 30-fasteoi i2c_designware.4 32: IO-APIC 32-fasteoi idma64.0, i2c_designware.0 33: IO-APIC 33-fasteoi idma64.1, i2c_designware.1 35: IO-APIC 35-fasteoi idma64.2, i2c_designware.2 88: IO-APIC 88-fasteoi ELAN0000:00 89: IO-APIC 89-fasteoi chromeos-ec 99: IO-APIC 99-edge cr50_i2c 106: IO-APIC 106-fasteoi chromeos-ec IO-APIC interrupts after: 1: IO-APIC 1-edge i8042 8: IO-APIC 8-edge rtc0 9: IO-APIC 9-fasteoi acpi 14: IO-APIC 14-fasteoi INTC1083:00 16: IO-APIC 16-fasteoi intel-ipu6 20: IO-APIC 20-fasteoi idma64.5, ttyS0 27: IO-APIC 27-fasteoi idma64.0, i2c_designware.0 28: IO-APIC 28-fasteoi idma64.1, i2c_designware.1 30: IO-APIC 30-fasteoi idma64.2, i2c_designware.2 31: IO-APIC 31-fasteoi i2c_designware.3 32: IO-APIC 32-fasteoi i2c_designware.4 35: IO-APIC 35-fasteoi idma64.6, pxa2xx-spi.6 88: IO-APIC 88-fasteoi ELAN0000:00 89: IO-APIC 89-fasteoi chromeos-ec 99: IO-APIC 99-edge cr50_i2c 106: IO-APIC 106-fasteoi chromeos-ec _PRT before: Package (0x04) ==> 0x001FFFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x001FFFFF, One, Zero, 0x11 Package (0x04) ==> 0x001FFFFF, 0x02, Zero, 0x12 Package (0x04) ==> 0x001FFFFF, 0x03, Zero, 0x13 Package (0x04) ==> 0x001EFFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x001EFFFF, One, Zero, 0x11 Package (0x04) ==> 0x001EFFFF, 0x02, Zero, 0x1B Package (0x04) ==> 0x001EFFFF, 0x03, Zero, 0x1C Package (0x04) ==> 0x001CFFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x001CFFFF, One, Zero, 0x11 Package (0x04) ==> 0x001CFFFF, 0x02, Zero, 0x12 Package (0x04) ==> 0x001CFFFF, 0x03, Zero, 0x13 Package (0x04) ==> 0x0019FFFF, Zero, Zero, 0x1D Package (0x04) ==> 0x0019FFFF, One, Zero, 0x1E Package (0x04) ==> 0x0019FFFF, 0x02, Zero, 0x1F Package (0x04) ==> 0x0017FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0016FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0016FFFF, One, Zero, 0x11 Package (0x04) ==> 0x0016FFFF, 0x02, Zero, 0x12 Package (0x04) ==> 0x0016FFFF, 0x03, Zero, 0x13 Package (0x04) ==> 0x0015FFFF, Zero, Zero, 0x20 Package (0x04) ==> 0x0015FFFF, One, Zero, 0x21 Package (0x04) ==> 0x0015FFFF, 0x02, Zero, 0x22 Package (0x04) ==> 0x0015FFFF, 0x03, Zero, 0x23 Package (0x04) ==> 0x0014FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0014FFFF, One, Zero, 0x11 Package (0x04) ==> 0x0014FFFF, 0x02, Zero, 0x12 Package (0x04) ==> 0x0012FFFF, Zero, Zero, 0x1A Package (0x04) ==> 0x0012FFFF, One, Zero, 0x25 Package (0x04) ==> 0x0012FFFF, 0x02, Zero, 0x19 Package (0x04) ==> 0x0010FFFF, Zero, Zero, 0x17 Package (0x04) ==> 0x0010FFFF, One, Zero, 0x16 Package (0x04) ==> 0x000DFFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x000DFFFF, One, Zero, 0x11 Package (0x04) ==> 0x000BFFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0008FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0007FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0007FFFF, One, Zero, 0x11 Package (0x04) ==> 0x0007FFFF, 0x02, Zero, 0x12 Package (0x04) ==> 0x0007FFFF, 0x03, Zero, 0x13 Package (0x04) ==> 0x0006FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0006FFFF, One, Zero, 0x11 Package (0x04) ==> 0x0006FFFF, 0x02, Zero, 0x12 Package (0x04) ==> 0x0006FFFF, 0x03, Zero, 0x13 Package (0x04) ==> 0x0005FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0004FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0002FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0001FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0001FFFF, One, Zero, 0x11 Package (0x04) ==> 0x0001FFFF, 0x02, Zero, 0x12 Package (0x04) ==> 0x0001FFFF, 0x03, Zero, 0x13 _PRT after: Package (0x04) ==> 0x0001FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0002FFFF, 0x00, 0x00, 0x00000011 Package (0x04) ==> 0x0004FFFF, 0x00, 0x00, 0x00000012 Package (0x04) ==> 0x0005FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0006FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0006FFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x0006FFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x0007FFFF, 0x00, 0x00, 0x00000013 Package (0x04) ==> 0x0007FFFF, 0x01, 0x00, 0x00000014 Package (0x04) ==> 0x0007FFFF, 0x02, 0x00, 0x00000015 Package (0x04) ==> 0x0007FFFF, 0x03, 0x00, 0x00000016 Package (0x04) ==> 0x0008FFFF, 0x00, 0x00, 0x00000017 Package (0x04) ==> 0x000BFFFF, 0x00, 0x00, 0x00000013 Package (0x04) ==> 0x000DFFFF, 0x00, 0x00, 0x00000014 Package (0x04) ==> 0x000DFFFF, 0x01, 0x00, 0x00000015 Package (0x04) ==> 0x0010FFFF, 0x00, 0x00, 0x00000016 Package (0x04) ==> 0x0010FFFF, 0x01, 0x00, 0x00000017 Package (0x04) ==> 0x0012FFFF, 0x00, 0x00, 0x00000018 Package (0x04) ==> 0x0012FFFF, 0x01, 0x00, 0x00000019 Package (0x04) ==> 0x0012FFFF, 0x02, 0x00, 0x00000011 Package (0x04) ==> 0x0014FFFF, 0x01, 0x00, 0x00000012 Package (0x04) ==> 0x0014FFFF, 0x00, 0x00, 0x0000001A Package (0x04) ==> 0x0014FFFF, 0x02, 0x00, 0x00000013 Package (0x04) ==> 0x0015FFFF, 0x00, 0x00, 0x0000001B Package (0x04) ==> 0x0015FFFF, 0x01, 0x00, 0x0000001C Package (0x04) ==> 0x0015FFFF, 0x02, 0x00, 0x0000001D Package (0x04) ==> 0x0015FFFF, 0x03, 0x00, 0x0000001E Package (0x04) ==> 0x0016FFFF, 0x00, 0x00, 0x00000014 Package (0x04) ==> 0x0016FFFF, 0x01, 0x00, 0x00000015 Package (0x04) ==> 0x0016FFFF, 0x02, 0x00, 0x00000016 Package (0x04) ==> 0x0016FFFF, 0x03, 0x00, 0x00000017 Package (0x04) ==> 0x0017FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0019FFFF, 0x00, 0x00, 0x0000001F Package (0x04) ==> 0x0019FFFF, 0x01, 0x00, 0x00000020 Package (0x04) ==> 0x0019FFFF, 0x02, 0x00, 0x00000021 Package (0x04) ==> 0x001CFFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x001CFFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x001CFFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x001CFFFF, 0x03, 0x00, 0x00000013 Package (0x04) ==> 0x001EFFFF, 0x00, 0x00, 0x00000014 Package (0x04) ==> 0x001EFFFF, 0x01, 0x00, 0x00000015 Package (0x04) ==> 0x001EFFFF, 0x02, 0x00, 0x00000022 Package (0x04) ==> 0x001EFFFF, 0x03, 0x00, 0x00000023 Package (0x04) ==> 0x001FFFFF, 0x01, 0x00, 0x00000017 Package (0x04) ==> 0x001FFFFF, 0x02, 0x00, 0x00000014 Package (0x04) ==> 0x001FFFFF, 0x03, 0x00, 0x00000015 Package (0x04) ==> 0x001FFFFF, 0x00, 0x00, 0x00000016 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I013cd5faab6f425ab1af91fe2a36ac3b8aeef443 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-06soc/intel/common: Use CPUID_STRUCT_EXTENDED_FEATURE_FLAGS macroPratikkumar Prajapati
Use CPUID_STRUCT_EXTENDED_FEATURE_FLAGS macro to get extended CPU capabilities flags using cpuid_ext inline function. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: If680ffff64e2e1dabded8c03c4042d349a11b635 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71646 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04soc/intel: Create common function to check PCH slotKapil Porwal
BUG=none TEST=Build and boot to google/taniks. Check dmesg and make sure that there is no regression. Also confirm that there is no change in ACPI _PRT and IO-APCI interrupt assignment. IO-APIC interrupts before and after this patch: 1: IO-APIC 1-edge i8042 8: IO-APIC 8-edge rtc0 9: IO-APIC 9-fasteoi acpi 14: IO-APIC 14-fasteoi INTC1055:00 23: IO-APIC 23-fasteoi idma64.5, ttyS0 37: IO-APIC 37-fasteoi idma64.0, i2c_designware.0 38: IO-APIC 38-fasteoi idma64.1, i2c_designware.1 40: IO-APIC 40-fasteoi idma64.2, i2c_designware.2 41: IO-APIC 41-fasteoi idma64.3, i2c_designware.3 42: IO-APIC 42-fasteoi idma64.4, i2c_designware.4 45: IO-APIC 45-fasteoi idma64.6, pxa2xx-spi.6 77: IO-APIC 77-edge cr50_i2c 100: IO-APIC 100-fasteoi ELAN0000:00 103: IO-APIC 103-fasteoi chromeos-ec _PRT before and after this patch: Package (0x04) ==> 0x0001FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0002FFFF, 0x00, 0x00, 0x00000011 Package (0x04) ==> 0x0004FFFF, 0x00, 0x00, 0x00000012 Package (0x04) ==> 0x0005FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0006FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0006FFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x0007FFFF, 0x00, 0x00, 0x00000013 Package (0x04) ==> 0x0007FFFF, 0x01, 0x00, 0x00000014 Package (0x04) ==> 0x0007FFFF, 0x02, 0x00, 0x00000015 Package (0x04) ==> 0x0007FFFF, 0x03, 0x00, 0x00000016 Package (0x04) ==> 0x0008FFFF, 0x00, 0x00, 0x00000017 Package (0x04) ==> 0x000DFFFF, 0x00, 0x00, 0x00000011 Package (0x04) ==> 0x000DFFFF, 0x01, 0x00, 0x00000013 Package (0x04) ==> 0x0010FFFF, 0x00, 0x00, 0x00000018 Package (0x04) ==> 0x0010FFFF, 0x01, 0x00, 0x00000019 Package (0x04) ==> 0x0010FFFF, 0x02, 0x00, 0x00000014 Package (0x04) ==> 0x0010FFFF, 0x03, 0x00, 0x00000015 Package (0x04) ==> 0x0011FFFF, 0x00, 0x00, 0x0000001A Package (0x04) ==> 0x0011FFFF, 0x01, 0x00, 0x0000001B Package (0x04) ==> 0x0011FFFF, 0x02, 0x00, 0x0000001C Package (0x04) ==> 0x0011FFFF, 0x03, 0x00, 0x0000001D Package (0x04) ==> 0x0012FFFF, 0x00, 0x00, 0x0000001E Package (0x04) ==> 0x0012FFFF, 0x01, 0x00, 0x0000001F Package (0x04) ==> 0x0012FFFF, 0x02, 0x00, 0x00000016 Package (0x04) ==> 0x0013FFFF, 0x00, 0x00, 0x00000020 Package (0x04) ==> 0x0013FFFF, 0x01, 0x00, 0x00000021 Package (0x04) ==> 0x0013FFFF, 0x02, 0x00, 0x00000022 Package (0x04) ==> 0x0013FFFF, 0x03, 0x00, 0x00000023 Package (0x04) ==> 0x0014FFFF, 0x01, 0x00, 0x00000017 Package (0x04) ==> 0x0014FFFF, 0x00, 0x00, 0x00000024 Package (0x04) ==> 0x0014FFFF, 0x02, 0x00, 0x00000011 Package (0x04) ==> 0x0015FFFF, 0x00, 0x00, 0x00000025 Package (0x04) ==> 0x0015FFFF, 0x01, 0x00, 0x00000026 Package (0x04) ==> 0x0015FFFF, 0x02, 0x00, 0x00000027 Package (0x04) ==> 0x0015FFFF, 0x03, 0x00, 0x00000028 Package (0x04) ==> 0x0016FFFF, 0x00, 0x00, 0x00000012 Package (0x04) ==> 0x0016FFFF, 0x01, 0x00, 0x00000013 Package (0x04) ==> 0x0016FFFF, 0x02, 0x00, 0x00000014 Package (0x04) ==> 0x0016FFFF, 0x03, 0x00, 0x00000015 Package (0x04) ==> 0x0017FFFF, 0x00, 0x00, 0x00000016 Package (0x04) ==> 0x0019FFFF, 0x00, 0x00, 0x00000029 Package (0x04) ==> 0x0019FFFF, 0x01, 0x00, 0x0000002A Package (0x04) ==> 0x0019FFFF, 0x02, 0x00, 0x0000002B Package (0x04) ==> 0x001CFFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x001CFFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x001CFFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x001CFFFF, 0x03, 0x00, 0x00000013 Package (0x04) ==> 0x001DFFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x001DFFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x001DFFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x001DFFFF, 0x03, 0x00, 0x00000013 Package (0x04) ==> 0x001EFFFF, 0x00, 0x00, 0x00000017 Package (0x04) ==> 0x001EFFFF, 0x01, 0x00, 0x00000014 Package (0x04) ==> 0x001EFFFF, 0x02, 0x00, 0x0000002C Package (0x04) ==> 0x001EFFFF, 0x03, 0x00, 0x0000002D Package (0x04) ==> 0x001FFFFF, 0x01, 0x00, 0x00000016 Package (0x04) ==> 0x001FFFFF, 0x02, 0x00, 0x00000017 Package (0x04) ==> 0x001FFFFF, 0x03, 0x00, 0x00000014 Package (0x04) ==> 0x001FFFFF, 0x00, 0x00, 0x00000015 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ib4fc850228b7ddbf84e2feb2433adff5e4002033 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71236 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimizationChris.Wang
Add the UPD dxio_tx_vboost_enable for PCIe optimization. It will impact the PCIe signal integrity, need to double-confirm the SI result after enabling this setting. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71562 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04soc/intel/common/block/fast_spi: Hook up pci_dev_ops_pci to set SSIDKapil Porwal
BUG=none TEST=Verify presence of subsystem ID for fast_spi device on google/rex. lspci output before this patch: 00:1f.5 Serial bus controller [0c80]: Intel Corporation Device [8086:7e23] lspci output after this patch: 00:1f.5 Serial bus controller [0c80]: Intel Corporation Device [8086:7e23] Subsystem: Intel Corporation Device [8086:7e23] Note: UPD SiSkipSsidProgramming was set to 1 for above test. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I08c7a5a3fdc7389b315e85180c16d1ec335fbba2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-04soc/intel/common: Add API to check Key Locker supportPratikkumar Prajapati
Add is_keylocker_supported() API in common cpulib. This function checks if the CPU supports Key Locker feature. Returns true if Key Locker feature is supported otherwise false. Change-Id: Ide9e59a4f11a63df48838eab02c2c584cced12e1 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71117 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-03soc/amd/cezanne/psp_verstage/Makefile.inc: Remove path to non-existent ↵Elyes Haouas
directories Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/cezanne/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I36022a031cc08d2af8b982522b3d6652e679bf14 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-03soc/amd/picasso/psp_verstage/Makefile.inc: Remove path to non-existent ↵Elyes Haouas
directories Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/picasso/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I7713eef54686c58a83215c461c3274cec89e32b0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-03soc/amd/mendocino/psp_verstage/Makefile.inc: Remove path to non-existent ↵Elyes Haouas
directory Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/mendocino/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I1cc084abc7a9bfed760350f304dd074081a7eebf Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-03soc/intel/baytrail: add _HRV to GPIO ACPI devicesMatt DeVillier
For some reason, the Windows LPEA drivers won't attach without _HRV (hardware version) defined for the GPIO controllers. Add it, using value taken from Intel baytrail/valleyview edk2 reference code. TEST=boot Windows 10/11 on google/rambi, verify LPEA drivers load properly. Change-Id: Iaa6e1b3f68537e012e4a58175d5334a8aa2f4178 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-03soc/intel/baytrail: add _HRV to I2C ACPI devicesMatt DeVillier
For some reason, the Windows i2c drivers won't attach without _HRV (hardware version) defined for the i2c controllers. Add it, using value taken from Intel baytrail/valleyview edk2 reference code. TEST=boot Windows 10/11 on google/rambi, verify i2c drivers load properly. Change-Id: I590acd1f1b75f6bf2bf278e67eec1dcc24bcc15d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02soc/intel/common: Move SGX supported API to cpulibPratikkumar Prajapati
Move is_sgx_supported() API to common cpulib code, so that this function can be used by other code without enabling SOC_INTEL_COMMON_BLOCK_SGX_ENABLE config option. Change-Id: Ib630ac451152ae2471c862fced992dde3b49d05d Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-01apollolake/include/soc/meminit.h: Add missing stdboolElyes Haouas
stdbool is added through types.h file. Change-Id: I317faf322a7e73b706724802d99815ab50e655e2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-31Enable VBOOT_VBNV_FLASH for SOC_INTEL_BRASWELLYu-Ping Wu
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with VBOOT_VBNV_FLASH for boards using SOC_INTEL_BRASWELL. Currently BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is selected for CPU_INTEL_HASWELL, SOC_INTEL_BRASWELL and others (see [2]). However, there seems to be no particular reason on those platforms. We've dropped the config for haswell. Now do the same for SOC_INTEL_BRASWELL, so that VBOOT_VBNV_FLASH can be enabled. VBOOT_VBNV_FLASH is enabled for the following boards: - facebook/fbg1701: A 0x2000 RW_NVRAM region is allocated, with the FW_MAIN_A(CBFS) size reduced by 0x2000. - google/cyan, intel/strago: Repurpose RW_UNUSED as RW_NVRAM. [1] https://issuetracker.google.com/issues/235293589 [2] commit 6c2568f4f58b9a1b209c9af36d7f980fde784f08 ("drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config") BUG=b:235293589 TEST=./util/abuild/abuild -t FACEBOOK_FBG1701 -a (with VBOOT selected) TEST=./util/abuild/abuild -x -t GOOGLE_CYAN -a TEST=./util/abuild/abuild -x -t INTEL_STRAGO -a Change-Id: I46542c2887b254f59245f20b8642b023a7871708 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2022-12-27soc/intel/alderlake: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h and soc/gpio.h includes with the common gpio.h which will include soc/gpio.h which will include intelblocks/gpio.h BUG=b:261778357 TEST=Able to build and boot Google/brya. Change-Id: Ia90a8ea7b4ee125657c7277e3e14018cfe5423a9 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71266 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-27tree/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{acpi,arch,soc}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I3dfd7dd1de3bd27c35c195bd43c4a5b8c5a2dc53 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71522 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26tree/acpi: Replace Not(a) with ASL 2.0 syntaxFelix Singer
Replace `Not (a)` with `~a`. Change-Id: I53993fb7b46b3614d18ee001323f17efacbf04c1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71513 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26soc/intel/baytrail/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas
Change-Id: Iab611cda1083da4378a6e509d11ea26bdbb45edd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71503 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26soc/intel/braswell/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas
Change-Id: I7da6ee3c5bce6b32874e59ad46290b86db8f97c6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71502 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-25soc/intel/meteorlake: Make use of is_devfn_enabled() functionDinesh Gehlot
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on MTL. Port of 'commit 50134eccbdf4 ("soc/intel/alderlake: Make use of is_devfn_enabled() function")' Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I54bbd2bdba69a19e0559738035916fa7ac60faaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/71161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-25soc/intel: Move max speed API to commonDinesh Gehlot
This patch moves API "smbios_cpu_get_max_speed_mhz()" to common code from board specific. This API was made generic in 'commit d34364bdea12 ("soc/intel/alderlake: Utilize `CPU_BCLK_MHZ` over dedicated macro")' BUG=NONE TEST=Boot and verified that SMBIOS max speed value is correct on brya and rex. (brya) dmidecode -t : "Max Speed: 4400 MHz" (rex) dmidecode -t : "Max Speed: 3400 MHz" Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I87040ab23319097287e191d7fc9579f16d716e62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70879 Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATETracy Wu
With enabling FSP Notify Phase APIs, it has chance to issue a global reset in FSP after CSE EOP (with selecting SOC_INTEL_CSE_SEND_EOP_EARLY ), which CSE already in idle mode and cause failure. For this reason we should drop SOC_INTEL_CSE_SEND_EOP_EARLY in all ADL sku and select SOC_INTEL_CSE_SEND_EOP_LATE instead. BUG=b:261544011 BRANCH=firmware-brya-14505.B TEST=tested and verified on Marasov, make sure this kind of global reset can be executed successfully. Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Change-Id: I29736ca8efee64dd03feb48404241ee6295b7c72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-24soc/amd/mendocino: Split the EFS from the AMDFW bodyKarthikeyan Ramasubramanian
Contents of unsigned AMDFW in RW sections are verified twice in PSP verstage - first time by vboot verifying the firmware body, second time by CBFS verification while the file is loaded to update PSP about the boot region. This redundant verification adds to boot time. Minimize the redundancy by splitting the EFS header from the AMDFW body and keep them as 2 separate CBFS files. This helps to improve the boot time by another 25 ms. BUG=None TEST=Build Skyrim BIOS image and boot to OS. Observe boot time improvement of ~25ms. Before: 6:end of verified boot 363,676 (16) 11:start of bootblock 641,392 (277,716) After: 6:end of verified boot 361,655 (16) 11:start of bootblock 616,967 (255,312) Change-Id: Ib18a4f5c6781e5a7868e9395c0f1212da0823100 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70839 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23soc/intel/cmn/block/pmc: Add pmc_or_mmio32 utility functionTim Chu
Change-Id: I5f9845dd3ea098d990710eaaa2d5db495f876cdd Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23soc/intel/broadwell: Add Kconfig option to hide Intel MEMatt DeVillier
On broadwell devices, coreboot currently disables and hides the ME PCI interface by default, without any way to opt out of this behavior. Add a Kconfig option to allow for leaving the ME PCI interface enabled, but set the default to disabled as to leave the current behavior unchanged. Change-Id: If670d548c46834740f4e21bb2361b537807c32bf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-12-23soc/intel/meteorlake: Add DPTF ACPI Device IDs into header fileSubrata Banik
This patch adds DPTF ACPI Device IDs into the header file (soc/dptf.h). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib78258ac1b9a5252bb5e6fae4d7cc30a3f103e78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71126 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23soc/intel: Drop SoC specific DPTF implementationSubrata Banik
This patch drops the SoC specific implementation as DPTF driver can now fillin those platform specific data using SoC specific macros. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If65976f15374ba2410b537b1646ce466ba02969b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-05 02:34:21 +0000