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BUG=chrome-os-partner:55639
Change-Id: Idbad4f8763be18002907a62be755b2fdf7e479ec
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15895
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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BUG=chrome-os-partner:55639
Change-Id: Ie859ec3ff682e91a4d7d38d3c3cd6badf7385431
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15894
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and
developer mode check functions to vboot. Thus, get rid of the
BOOTMODE_STRAPS option which controlled these functions under src/lib.
BUG=chrome-os-partner:55639
Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15868
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use
of verified boot library without having to stick to CHROMEOS.
BUG=chrome-os-partner:55639
Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15867
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Currently, coreboot performs an erase of the entire MRC cache region on
flash if there is a version mismatch for the MRC data. Instead of doing
that, store the new MRC data in the next available slot, if there is
enough space available in the cache region.
BUG=chrome-os-partner:55699
Change-Id: Ib24a94f0a47c79941ed9f60095360ae3aad5540b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15915
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The monitor/mwait is broken on Apollolake. So use ACPI legacy
mwait IO redirection as a work around
BUG=chrome-os-partner:55110
Change-Id: I2e1834130d9586b4310466d3549d19bf427ffe24
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/15890
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Quark does not support the rdmsr and wrmsr instructions. In this case
use a SOC specific routine to support the setting of the MTRRs. Migrate
the code from FSP 1.1 to be x86 CPU common.
Since all rdmsr/wrmsr accesses are being converted, fix the build
failure for quark in lib/reg_script.c. Move the soc_msr_x routines and
their depencies from romstage/mtrr.c to reg_access.c.
TEST=Build and run on Galileo Gen2
Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15839
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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All mainboards (nyans) utilizing the cache_policy option
has it set to DCACHE_WRITETHROUGH. This option is for setting
the framebuffer's cache attribute. However, this option is
reliant on an architecture-specific enumeration. Just remove
the option and use DCACHE_WRITETHROUGH across the board. If
someone wants to reconfigure it at a later date one can
introduce a non-architecture specific option.
Change-Id: I6a0848231f5e28d36ec2d56b239bed67619fe5a7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15838
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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We set this driving control to prevent signal attenuation caused by
LVDS DRV termination.
When DA_LVDSTX_PWR_ON is not set, LVSH has no power and LVDS DRV
termination status is unknown (floating). This creates a chance that
MIPI output would be influenced. The DSI's LP signal will be half
voltage attenuation. There will be no display on panel.
When DA_LVDSTX_PWR_ON is set, LVSH and LVDS DRV termination are
effective and termination is fixed OFF. The DSI won't be influenced.
We only need to set this register once, so we set it here to prevent
repeatedly setting in the kernel when the system goes to recovery mode.
BUG=chrome-os-partner:55296
BRANCH=none
TEST=build pass elm and show ui
Change-Id: Ie3ccf6fb611dd5a1e2c02b7825d42a92e61268c0
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0d25a27f300acc4b65a894110d3ee0cc9676cd12
Original-Change-Id: Ie71f9cc41924787be8539c576392034320b57a49
Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/360850
Original-Commit-Ready: jitao shi <jitao.shi@mediatek.com>
Original-Tested-by: jitao shi <jitao.shi@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15807
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This allows the board to save the recovery request in case of unexpected
reboots caused by FSP.
With recovery module in vboot handling the saving of recovery reason
across reboots, there is no need to have special fsp reset handling
under soc.
BUG=chrome-os-partner:55431
Change-Id: I0b7ce14868a322072d3e60c1dae43f211b43fdbf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15804
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This allows the board to save the recovery request in case of unexpected
reboots caused by FSP.
BUG=chrome-os-partner:55431
Change-Id: If71802d2cba52a426f4c2db90d6c5384ed03ce68
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15803
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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As shown in testing, if CA use 34.3ohms drive strength, it leads
to an overshoot. To fix this, change the drive strength to 48 ohms.
BRANCH=none
BUG=chrome-os-partner:54871
TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass
Change-Id: I8666474fc18391da14a3338611f962f2f08f36d0
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: fbc1c13f9ab808fc907b2e3f9bde1d09f92980f1
Original-Change-Id: I231f5b1bd45ff262686fbacbaf119a8a57fad27b
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/358761
Original-Commit-Ready: Dan Shi <dshi@chromium.org>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15811
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Fix the board ID handling.
Recovery switch and WP status GPIO has been reassigned in board rev3.
Configure related GPIOs based on Board ID.
BUG=chrome-os-partner:55320
TEST=Verified GPIO assignment for Rev.1 board.
BRANCH=None
Change-Id: Id8e1ba1c039f8b5b503f0da038e5cfc84b72678f
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: d295ab514e31d9ebd1b77e0af9b769e64cbf567e
Original-Change-Id: I6d3d5df2e9017f7845edc3cd0b2c19ad7c58a97c
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/361393
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/15809
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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1. Remove unused functions/structures.
2. Add checks for NULL return values.
3. Change prefixes to vb2 instead of vboot for functions used internally
within vboot2/
4. Get rid of vboot_handoff.h file and move the structure definition to
vboot_common.h
5. Rename all functions using handoff structure to have prefix
vboot_handoff_*. All the handoff functions can be run _only_ after cbmem
is online.
6. Organize vboot_common.h content according to different
functionalities.
BUG=chrome-os-partner:55431
Change-Id: I4c07d50327d88cddbdfbb0b6f82c264e2b8620eb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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All the mainboards share the same config options for CHROMEOS. Instead
of duplicating those in every mainboard, move the CHROMEOS config to SoC
and make it dependent on MAINBOARD_HAS_CHROMEOS.
BUG=chrome-os-partner:55431
Change-Id: Iafabb6373dfe16aaf0fe2cbc4e978952adeb403e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15822
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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All the mainboards share the same config options for CHROMEOS. Instead
of duplicating those in every mainboard, move the CHROMEOS config to SoC
and make it dependent on MAINBOARD_HAS_CHROMEOS.
BUG=chrome-os-partner:55431
Change-Id: I2d54ff6beac9fca7596a8f104e3c1447cada5c05
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15821
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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The controller for device mode USB is not plan of record
on apollolake. However, one still needs to configure the
one port to be host mode by default such that the devices
work as expected when plugged into the board.
BUG=chrome-os-partner:54581,chrome-os-partner:54656
TEST=Enabled xdci controller. Used USB type C->A dongle to
check that a mass storage device worked on port 0 on
reef.
Change-Id: Ia9ec5076491f31bc5dc3d534e235fb49f7b2efac
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15781
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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The gpio bank irq is not correct and hence gpio
bank handler is never called in case of gpio based irq.
Correct the gpio bank irq to enable gpio based irq.
BUG=chrome-os-partner:55433
TEST=cat /proc/interrupts | grep INT3452 should
output 14.
Change-Id: I54253786425b7d4c2007043d49a91dfa6db0397b
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/15756
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The 'dram density' is a misnomer because the memory initialization
code treats that input parameter as a per rank density. Therefore,
update the variables to further clarify how it's actually being
used.
BUG=chrome-os-partner:55446
Change-Id: Ie4c944f35b531812205ac0bb1c70f39ac401495e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15773
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Despite the UPD comments the Chx_RankEnable fields are a bit
mask which indicates which ranks are enabled for physical
channel. Add the ability to set the rank mask correctly for
dual rank LPDDR4 modules.
BUG=chrome-os-partner:55446
Change-Id: I9dbed7bb6a4b512e57f6b4481180932a7cce91ff
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15771
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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The reset requests are handled in the FSP 2.0 wrapper, but
the current code doesn't check any non-successful return
values. Provide parity with the memory init path which die()s
under those circumstances.
Change-Id: I9df61323f742b4e94294321e3ca3ab58a68ca4dd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15766
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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B stepping onwards we have to support two Graphics Device ID.
BUG=chrome-os-partner:55449
Change-Id: I520791ad8573dc5deb6ea1e33e1486f05050438c
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/15767
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Add missing break to LEG_GPIO_REGS case to return the correct value for
legacy GPIO reads. Fixes coverity issue CID 1357460.
Found by Coverity, Fixes:
* CID 1357460 (#1 of 1): Unused value (UNUSED_VALUE)
returned_value: Assigning value from reg_legacy_gpio_read(step->reg)
to value here, but that stored value is overwritten before it can be
used.
value_overwrite: Overwriting previous write to value with value from
reg_pcie_afe_read(step->reg).
TEST=Build and run on Galileo Gen2.
Change-Id: I6c52e8801a32f510ac94276fe0c097850cbfde57
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15732
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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The 'speed' variable isn't being used after refactoring.
Change-Id: Id27a920c61b2bba18d391a7bfefe570235402dec
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/15749
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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FSP 2.0 spec only defines 2 reset request (COLD, WARM) exit codes. The
rest 6 codes are platform-specific and may vary. Modify helper function
so that only basic resets are handled and let SoC deal with the rest.
Change-Id: Ib2f446e0449301407b135933a2088bcffc3ac32a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15730
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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At first boot CSE spends long time preparing media for use. As result
it may not be able to deal with a CPU reset. Add reset_prepare()
callback that polls CSE readiness.
BUG=chrome-os-partner:55055
TEST=build with release version of fsp, reboot, observe polling for
CSE, then proper reboot happening
Change-Id: I639ef900b97132f1a7f269bb864d70009df9fdfe
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15721
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Some Intel SoC may need preparation before reset can be properly
handled. Add callback that chip/soc code can implement.
BUG=chrome-os-partner:55055
Change-Id: I45857838e1a306dbcb9ed262b55e7db88a8944e5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15720
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add functions to read Host Firmware Status register and a helper
function to determine if CSE is ready.
BUG=chrome-os-partner:55055
TEST=none
Change-Id: If511a51c04f7e59427d7952fa67b61060e2be404
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15713
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The FSPS component loading was just loading to any memory address
listed in the header. That could be anywhere in the address space
including ramstage itself -- let alone corrupting the OS memory on
S3 resume. Remedy this by loading and relocating FSPS into cbmem.
The UEFI 2.4 header files include path are selected to provide the
types necessary for FSP relocation.
BUG=chrome-os-partner:52679
Change-Id: Iaba103190731fc229566a3b0231cf967522040db
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15742
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: John Zhao <john.zhao@intel.com>
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The previously implementation for loading the FSPM component didn't
handle platforms which expects FSPM to be XIP. For the non-XIP case,
romstage's address space wasn't fully being checked for overlaps.
Lastly, fixup the API as the range_entry isn't needed any longer.
This API change requires a apollolake to be updated as well.
BUG=chrome-os-partner:52679
Change-Id: I24d0c7d123d12f15a8477e1025bf0901e2d702e7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15741
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Instead of performing the same tasks in the chipset code move
the common sequences into the FSP 2.0 driver. This handles the
S3 paths as well as saving and restoring the memory data. The
chipset code can always override the settings if needed.
BUG=chrome-os-partner:52679
Change-Id: I098bf95139a0360f028a50aa50d16d264bede386
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15739
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The amount of reserved memory just below the DRAM limit in
32-bit space is defined in the FSP 2.0 specification within
the FSPM_ARCH_UPD structure. There's no need to make the
chipset code set the same value as needed for coreboot.
The chipset code can always change the value if it needs
after the common setting being applied.
Remove the call in soc/intel/apollolake as it's no longer
needed.
BUG=chrome-os-partner:52679
Change-Id: I69a1fee7a7b53c109afd8ee0f03cb8506584d571
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15738
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
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Change-Id: I97be4f8cecbf9cf2adda2e0c1650e03acd7eb1cb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15736
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
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Fix issue where zero-sized BIOS region could cause bitshift
for '-1' which is an unspecified behavior.
Change-Id: Icb62bf413a1a0d293657503ef21fe97b5f9a5484
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15727
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Asserting this GPIO will send a signal to the EC to trigger a reset
for the AP and the CR50.
BRANCH=none
BUG=chrome-os-partner:55252
TEST=the device now reboots when it needs to switch between different
boot modes instead of hanging with "failed to reboot" message.
Change-Id: I8d168e313b6983c96c80f7ad6d70bb84c1ec1d9c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 83a4c8ff68ab24a103f2166e948eb23624ea97f7
Original-Change-Id: Idfd20977cf3682bd8933f89e8eec53005e55864e
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/360238
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15718
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
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Since the Integrated Sensor Hub can be disabled through devicetree.cb
as a PCI device, there is no need for a separate register variable.
Remove handling the register and update mainboards' devicetrees. Also
keep ISH disabled on both Reef and Amenia.
Change-Id: I90dbf57b353ae1b80295ecf39877b10ed21de146
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15710
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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1. The hotplug feature needs to be disabled
so that pcie root ports will be disabled by fsp
2. Correct PcieRootPortEn mapping.
The correct mapping should be like below
PcieRootPortEn[0] ==> 00:14.0
PcieRootPortEn[1] ==> 00:14.1
PcieRootPortEn[2] ==> 00:13.0
PcieRootPortEn[3] ==> 00:13.1
PcieRootPortEn[4] ==> 00:13.2
PcieRootPortEn[5] ==> 00:13.3
BUG=chrome-os-partner:54288
BRANCH=None
TEST=Checked pcie root port is disabled properly
and make sure pcie ports are coalesced.
Also make sure the device will still be enabled after coalescence
when pcie on function 0 is disabled devicetree
Change-Id: I39c482a0c068ddc2cc573499480c3fe6a52dd5eb
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/15595
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Implement poweroff() by putting the chipset into ACPI S5 state.
BUG=chrome-os-partner:54977
Change-Id: I9288dcee13347a8aa3f822ca3d75148ba2792859
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15688
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
|
|
Implement poweroff() by putting the chipset into ACPI S5 state.
BUG=chrome-os-partner:54977
Change-Id: I4ee269f03afd252d4bce909a8cc7c64d6270b16e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15686
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
|
|
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I034c083604892a5fa25dff3b50e327e0a885b021
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15683
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
|
|
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I1ff1517ded2d43e3790d980599e756d0d064f75c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15674
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I99d909ee72c3abebb1e9c8ebf44137465264bf0d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15673
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: Iecd94494cb568b20bdf6649b46a9a9586074bdc7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15672
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: York Yang <york.yang@intel.com>
|
|
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I5f2aa424a167092b570fda020cddce5ef906860a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15671
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
|
|
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: Ia3860fe9e5229917881696e08418c3fd5fb64ecc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15670
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
|
|
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: Idf055fa86b56001a805e139de6723dfb77dcb224
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15669
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I40560b2a65a0cff6808ccdec80e0339786bf8908
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15668
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: Icaca9367b526999f0475b21dd968724baa32e3f6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15667
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
|
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The ramstage main() in lib/hardwaremain.c has the logic
to set the ACPI sleep state based on romstage_handoff. Thus,
there's no need to do it a second time.
Change-Id: I75172083587c8d4457c1466edb88d400f7ef2dd0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15662
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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The ramstage main() in lib/hardwaremain.c has the logic
to set the ACPI sleep state based on romstage_handoff. Thus,
there's no need to do it a second time.
Change-Id: I88af301024fd6f868f494a737d2cce14d85f8241
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15661
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
|
|
CBMEM should be placed at the top of RAM, which can be found by parsing
the configuration string. Configuration string parsing isn't yet
implemented, so I'll hard-code the CBMEM location for now.
Change-Id: If4092d094a856f6783887c062d6682dd13a73b8f
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15284
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
rk3399 sdram size is 192K, and there still some unused space.
We need more romstage space to include the sdram config, so extend
the romstage range.
BRANCH=none
BUG=chrome-os-partner:54871
TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass
Change-Id: Ib827345fe646e985773e6ce3e98ac3f64317fffb
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 626ab15bb4ebb004d5294b948bbdecc77a72a484
Original-Change-Id: Ib5aa1e1b942cde8d9476773f5a84ac70bb830c80
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/359092
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15660
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
kevin rev3 pwm regulator ripple is still not great, especially for
center logic. To make sdram at 800MHz stable, raise it to 0.95v.
BRANCH=none
BUG=chrome-os-partner:54871
TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass
Change-Id: If4a15eb7398eea8214cb58422bca7cfb5f4a051a
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: d29bc581effb0008eb196685aa22dd65b5d478a5
Original-Change-Id: Ideec9c3ab2f919af732719ed2f6a702068d99c8f
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/359130
Original-Commit-Ready: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15659
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This removes an empty function for sdram training. If it's needed
later, we can always add it back.
BRANCH=none
BUG=none
TEST=build and boot firmware for kevin/gru
Change-Id: Id526ef86cf5044894a1a736cc39f10d32f49c072
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 3e93461b96bfadc08bf0b46cf99052d9cdffa422
Original-Change-Id: I6bf77d2f81719c68cd78722c3fe9ae547ea1e79c
Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/354164
Original-Reviewed-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/15657
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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This changes the src arg for copy_to_reg to a const u32 * instead of a
u32 * in sdram.c.
BRANCH=none
BUG=none
TEST=emerge-gru coreboot
Change-Id: I80f49258b2f8102f0d988fec85b8038a00e18a34
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: e0342e5c0181bf65ae78aa9518b0d6bd6cb1d5ec
Original-Change-Id: I362727f1dbe6726bf3240f9219c394786162a1a0
Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/354163
Original-Reviewed-by: Martin Roth <martinroth@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15656
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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This simplifies some of the code with better variable declaractions
which removes a lot of line continuations. Instead of declaring a
pointer to the container of the needed struct or array, this retrieves
a pointer to the struct or array instead.
BRANCH=none
BUG=none
TEST=check that gru and kevin still build and boot properly followed
by running "stressapptest -M 1024 -s 1000" and making sure it passes
Change-Id: I34a9be0f35981c03a6b0c27a870981a5f69cecc0
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 5c17449fcdfbe83ec75a3a006aaf7393c66006b7
Original-Change-Id: If4e386d4029f17d811fa3ce83e5be89e661a7b11
Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/354162
Original-Reviewed-by: Martin Roth <martinroth@chromium.org>
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://review.coreboot.org/15655
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This removes a variable that was only used once and makes variable
declarations consistent by moving those only used in one block of code
into that block.
BRANCH=none
BUG=none
TEST=on kevin/gru, run "stressapptest -M 1024 -s 3600"
Change-Id: Iacfc0ffef34a4953cfb304b8cb4975b045aea585
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: a79bbbc83d0f5cccf6bb4ad44ae2239c7f4b45e3
Original-Change-Id: Id0ff0c45189c292ab40e1c4aa27929fb7780e864
Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/355667
Original-Reviewed-by: Martin Roth <martinroth@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15654
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This adds two local variables for dramtype and ddr_freq to sdram_init
since those two values are commonly used in the function. It also
removes a variable that is just used once and directly uses the value
for a function call instead.
BRANCH=none
BUG=none
TEST=on kevin/gru, run "stressapptest -M 1024 -s 3600" and check that
it passes
Change-Id: I4e9dbc97803ff3300b52a5e1672e7e060af2cc85
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: b7d1135c65298a73e6bf2a4a34b7c9b84f249ea8
Original-Change-Id: I4e1a1a4a8848d0eab07475a336c24bda90b2c9f8
Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/355666
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15653
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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It is not used in this file.
Change-Id: I59bb41370b97b79073c0fd82b1dbcae9fd8a62d0
Reported-by: GCC 6.1.0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15552
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
There is currently a SMBus driver implemented for soc/intel/broadwell
which nearly matches Broadwell-DE as well. Use this driver as template
and add minor modifications to make it work for Broadwell-DE. Support in
romstage is not available and can be added with a different patch.
Change-Id: I64649ceaa298994ee36018f5b2b0f5d49cf7ffd0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15617
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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With recent bootblock code additions the CBMEM console buffer is not
large enough to store the entire log accumulated before DRAM is
initialized, spilling 700 bytes or so on the floor.
This patch adds 1 KB to the CBMEM console buffer, at the expense of the
bootblock area in SRAM. The bootblock is taking less then 26K out of
31K allocated for it after this change.
Placing CBMEM console area right after the bootblock makes sure other
memory regions are not going to be affected should memory distribution
between bootblock and CBMEM console need to change again.
BRANCH=none
BUG=none
TEST=examining /sys/firmware/log after device boots up into Chrome OS
does not report truncated console buffer any more.
Change-Id: I016460f57c70dab4d603d4c5dbfc5ffbc6c3554f
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: bfa31684a1a9be87f39143cb6c07885a7b2e4843
Original-Change-Id: I2c3d198803e6f083ddd1d8447aa377ebf85484ce
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/358125
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15607
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This patch adds the support for gpio_tier1_sci_en bit which
needs to be set before going to sleep so that when
gpio_tier1_sci_sts bit gets set platform can wake
from S3.
BUG = chrome-os-partner:53992
TEST = Platform wakes from S3 on lidopen,key press.
Tested on Amenia and Reef boards.
Change-Id: I3ba79fa53ca8817149d585fa795a8f427c128dcb
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15612
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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FSP is currently setting a hard-coded policy for the interrupt
polarity settings. When the mainboard has already set the GPIO
settings up prior to SiliconInit being called that results
in the previous settings being dropped. Work around FSP's
default policy until FSP is fixed.
BUG=chrome-os-partner:54955
Change-Id: Ibbd8c4894d8fbce479aeb73aa775b67df15dae85
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15649
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
For APIC routed gpios, set the corresponding interrupt polarity
for the associated IRQ based on the gpio pad's invert setting.
This allows for the APIC redirection entries to match the hardware
active polarity once the double inversion takes place to meet
apollolake interrupt triggering constraints.
BUG=chrome-os-partner:54955
Change-Id: I69c395b6f861946d4774a4206cf8f5f721c6f5f4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15648
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The interrupt and timer subsystem (ITSS) sits between the APIC
and the other logic blocks. It only supports positive polarity
events, but there's a polarity inversion setting for each IRQ such
that it can pass the signal on to the APIC according to the
expected APIC redirection entry values. This support is needed
in order for the platform/board to set the expected interrupt
polarity into the APIC for gpio signals.
BUG=chrome-os-partner:54955
Change-Id: I50ea1b7c4a7601e760878af515518cc0e808c0d1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15647
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Internally, apollolake routes its interrupts as active high.
This includes SCI, SMI, and ACPI. Therefore, provide helper
macros such that the user can describe an interrupt's active
high/low polarity more easily. It helps for readability when
one is comparing gpio configuration next to APIC configuration
in different files. Additionally, the gpio APIC macros always
use a LEVEL trigger in order to let the APIC handle the
filtering of the IRQ on its own end.
BUG=chrome-os-partner:54977
Change-Id: Id8fdcd98f0920936cd2b1a687fd8fa07bce9a614
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15644
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
|
|
Change-Id: I195fd3a9c7fc07c35913342d2041e1ffef110466
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15549
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This patch adds the handler to enable bit for gpio_tier1_sci_en.
gpio_tier1_sci_en enables the setting of the GPIO_TIER1_SCI_STS
bit to generate a wake event and/or an SCI or SMI#. We are setting
the bit for gpio_tier1_sci_en from the ASL code as OS clears this bit
if set from BIOS. As per ACPI spec _GPE is defined as the Named
Object that evaluates to either an integer or a package. If _GPE
evaluates to an integer, the value is the bit assignment of the SCI
interrupt within the GPEx_STS register of a GPE block described in
the FADT that the embedded controller will trigger. FADT right now
has no mechanism to acheive the same.
Change-Id: I1e1bd3f5c89a5e6bea2d1858569a9d30e6da78fe
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15578
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Properly obtain the top of memory address from the hardware registers
set by FSP.
TEST=Build and run on Galileo Gen2
Change-Id: I7681d32112408b8358b4dad67f8d69581c7dde2e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15594
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Add host bridge register access routines and macros.
TEST=Build and run on Galileo Gen2
Change-Id: I52eb6a68e99533fbb69c0ae1e6d581e4c4fab9d2
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15593
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The pull bias settings for GPIO0_A, GPIO0_B, GPIO2_C and GPIO2_D
are different from the other GPIO banks.
This patch adds a callback function to get the GPIO pull value
of each SoC(rk3288 and rk3399) so we can still use the common
GPIO driver.
BRANCH=none
BUG=chrome-os-partner:53251
TEST=Jerry and Gru still boot
Change-Id: I2a00b7ffd2699190582f5f50a1e21b61c500bf4f
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 46d5fa7297693216a2da9bcf15ccce4af796e80e
Original-Change-Id: If53f47181bdc235a1ccfefeeb2a77e0eb0e3b1ca
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/358110
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15587
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
coreboot boots from the little core, and doesn't use the big core for
now, but if apll_b is set to the default 24MHz, it will take a long time
to enable the big core. This will cause a watchdog crash, so apll_b
initialization to 600MHz needs to be done in coreboot.
BRANCH=none
BUG=chrome-os-partner:54817
TEST=Pick CL:353762 and see big CPU clocks look right
TEST=Boot from Gru and see no cpufreq warnings
Change-Id: Ie45cd2271555942e4321e9a9e523dc10f63d8107
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id:
Original-Change-Id: I20b8b591db3171e27740d85edce11f9e8797d849
Original-Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Original-Commit-Id: 16bc916174042620bebe19ae73d241002491aecc
Original-Original-Change-Id: Id3487138b383b6643ba7e3ce1eae501a6622da10
Original-Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Original-Reviewed-on: https://chromium-review.googlesource.com/356399
Original-Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15583
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Use the apll define instead of the apll_l define so it can be reused
when setting apll_b.
BRANCH=None
BUG=None
TEST=Boot from Gru
Change-Id: Iebc4ce3b66a86c33653292340b9855265ac4fc07
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: eb578110d19a35ef04f8749fdc202055abd50fd1
Original-Change-Id: I63966e98af48eaf49837eb0b781eea001a376ef4
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/356398
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Tested-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/15582
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Currently aclkm pclkdbg atclk clocks use apll_l as a parent, but the
apll_l frequency may change in firmware, so we need to caculate the div
value based on the apll_l frequency.
BRANCH=None
BUG=chrome-os-partner:54376
TEST=Boot from Gru
Change-Id: I2bd8886168453ce98efec58b5490c2430762769b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 116ae863a504630e2aff056564836d84198fcae2
Original-Change-Id: I7e3a5d9e3f608ddf15592d893117c92767fcd015
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/356397
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15581
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Cleans up the comments in sdram.c to make them consistent.
BRANCH=none
BUG=none
TEST=make sure gru/kevin build and boot
also, run "stressapptest -M 1024 -s 3600" to make sure it passes
Change-Id: I1daf72b847374d549389bacd2fa0a9f8f231b190
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 63a224d6f4b0e4d13bc372c05c4b9196895d553f
Original-Change-Id: Iaf8a32cfe2b22c4ccff71952f90d162ad8c2d3e7
Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/355665
Original-Reviewed-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/15579
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I2c49d68ea9a8f52737b6064bc4fa703bdb1af1df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15463
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Specify the memory initialization parameters in
mainboard/intel/galileo/devicetree.cb. Pass these values into FSP to
initialize memory.
TEST=Build and run on Galileo Gen2
Change-Id: I83ee196f5fb825118a3a74b61f73f3728a1a1dc6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15260
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove the unused Kconfig values which specify the PDAT file, its
location and inclusion into the coreboot file system. Remove the code
in romstage which locates the pdat.bin file.
TEST=Build and run on Galileo Gen2
Change-Id: I397aa22ada6c073c60485a735d6e2cb42bfd40ab
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15205
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add the gpio_defs.h reference in chip.h to enable
reef and amenia devicetree.cb to use the definitions from gpio_defs.h.
Change-Id: I333d4e810e42309ac76dd90c19f05cf3e3a517b1
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/15550
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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There is a second ACPI _DSD document from the UEFI Forum that details
how _DSD style tables can be nested, creating a tree of similarly
formatted tables. This document is linked from acpi_device.h.
In order to support this the device property interface needs to be
more flexible and build up a tree of properties to write all entries
at once instead of writing each entry as it is generated.
In the end this is a more flexible solution that can support drivers
that need child tables like the DA7219 codec, while only requiring
minor changes to the existing drivers that use the device property
interface.
This was tested on reef (apollolake) and chell (skylake) boards to
ensure that there was no change in the generated SSDT AML.
Change-Id: Ia22e3a5fd3982ffa7c324bee1a8d190d49f853dd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15537
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Instead of having all the mainboards put similar logic
into their own code provide common mechanism for memory
SKU selection. A function, meminit_lpddr4_by_sku(), is
added that selects the proper configuration based on the
SKU id and configuration passed in. LPDDR4 speed as well
as DRAM device density configuration is associated for
each logical channel per SKU id.
BUG=chrome-os-partner:54949
BRANCH=None
TEST=Built and used on reef for memory config.
Change-Id: Ifc6a734040bb61a58bc3d4c128a6420a71245c6c
Signed-off-by: Aaron Durbin <adurbin@chromuim.org>
Reviewed-on: https://review.coreboot.org/15559
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The internal pulls for gpio_input_pullup() and gpio_input_pulldown()
were using fairly strong pulls. Weaken them so that external pulls
can override the internal ones. This matches the current assumptions
of lib/gpio.c.
BUG=chrome-os-partner:54949
BRANCH=None
TEST=Built and used on reef for memory config.
Change-Id: Ifda1d04d40141325f78db277eb0bd55574994abf
Signed-off-by: Aaron Durbin <adurbin@chromuim.org>
Reviewed-on: https://review.coreboot.org/15558
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The name must not terminated with a newline character `\n` as it would
make it hard to use it strings. So, remove the newline from the two SoCs
with it.
Change-Id: I7570442b38a455e7c497d7f461c208fb0a88296d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/15540
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This includes the proper Kconfig options (based on the chromium os
coreboot configuration) for setting up verstage on tegra124 devices.
Change-Id: I4a1976ff684a417cae6fa718ef53cad763cee47d
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/15451
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The SCI interrupt can be routed to different IRQs using ACPI control
register. Instead of using hard coded IRQ9 for ACPI table generation
read back the register and return the used IRQ number. This way SCI IRQ
can be modified (e.g. for a given mainboard) and ACPI tables will
remain consistent.
Change-Id: I534fc69eb1df28cd8d733d1ac6b2081d2dcf7511
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15548
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: York Yang <york.yang@intel.com>
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There are several different macros available to convert a PCI device and
function to a single 8 bit value. One is PCI_DEVFN and is defined in
device/pci_def.h. The other is DEV_FUNC and is defined in several intel
fsp based chipset implementations. In fsp_broadwell_de DEV_FUNC is even
used without being defined at all. This patch unifies the situation so
that only PCI_DEVFN is used.
Change-Id: Ia1c6d7f3683badc66d15053846936d88aa836632
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15546
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784
Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15055
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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This patch adds the basic framework for SCI to GPE routing code.
BUG = chrome-os-partner:53438
TEST = Toogle pch_sci_l from ec console using gpioset command and
see that the sci counter increases in /sys/firmware/acpi/interrupt
and also 9 in /proc/interrupts.
Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15324
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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On Apollolake CSE can be used to fetch firmware from boot media. However,
when this feature is not used, CSE needs to be explicitly notified of it
before memory training is complete. This way it can transition to next
state.
BUG=chrome-os-partner:53876
TEST=CSE can be power-gated during S0iX. Confirmed with LTB.
Change-Id: I5141bff350b6c0bb662424b7b709f0787ec5fd28
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15494
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add the Audio DSP device for apollolake as a PCI driver with a static
scan_bus handler so generic devices can be declared under it.
This is for devices like the Maxim 98357A which is connected on the
I2S bus for data but has no control channel bus and instead just has
a GPIO for channel selection and power down control and needs to
describe that GPIO connection to the OS via ACPI.
Change-Id: Icb97ccf7d6a9034877614d49166bc9e4fe659b12
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/15528
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The P2SB device is device 0xd and function 0. If hidden that
causes the latter pci devices on function >= 1 to not be probed
in the kernel. This is also a problem for coreboot if the P2SB
device is hidden by FSP. That means the coreboot driver won't
be ran. Therefore, provide hide and unhide functions for the
P2SB device.
The other quirk is to allow the GPIO devices to work correctly.
Those devices are ACPI devices. However, their resources are
sub-regions within the P2SB BAR. Sadly, linux doesn't handle
ACPI devices being children of PCI devices. This leads to resource
conflict errors when the P2SB device is visible. For the
time being keep the P2SB device hidden, but also ensure the
resources it is using are accounted for and reserved. The fallout
of that is the PMC and SPI device are no longer probed by the
kernel.
BUG=chrome-os-partner:53017
TEST=Ensured P2SB device is visible and pci resources are allocated
correctly for the devices.
Change-Id: I24e59bbde74310e1ce8425b344a3ad0b88702153
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15530
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add the function defined in gpio.h to translate a gpio_t into a
value for use in an ACPI GPIO pin table.
For skylake this just returns the gpio_t value as the pins are
translated directly and they are all in the same ACPI device.
Change-Id: I00fad1cafec2f2d63dce9f7779063be0532649c7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15520
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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There are four GPIO communities in this SOC and they are implemented
as separate ACPI devices. This means the pin number that is used in
an ACPI GPIO declaration needs to be relative to the community that
the pin resides in. Also select GENERIC_GPIO_LIB in the SOC Kconfig
so this function actually gets used.
This was tested on the reef mainboard by verifying the output of the
SSDT for the Maxim 98357A codec that the assigned GPIO_76 is listed
as pin 0x24 which is the value relative to the Northwest community.
Change-Id: Iad2ab8eccf4c91185a075ffce8d41c81f06c1113
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15513
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Support the I2C interfaces on this SOC using the Intel common lpss_i2c
driver. The controllers are supported in pre-ram environments by
setting a temporary base address in bootblock and in ramstage using
the naturally enumerated base address.
The base speed of this controller is 133MHz and the SCL/SDA timing
values that are reported to the OS are calculated using that clock.
This was tested on a google/reef board doing I2C transactions to the
trackpad both in verstage and in ramstage.
Change-Id: I0a9d62cd1007caa95cdf4754f30c30aaff9f78f9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15480
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add support for the soc_acpi_name() handler in the device operations
structure to translate a device path into ACPI name.
In order to make this more complete add some missing devices in
include/soc/pci_devs.h.
Change-Id: I517bc86d8d9fe70bfa0fc4eb3828681887239587
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15479
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Have the Skylake SOC generate ACPI timing values for the enabled I2C
controllers instead of passing it in the DSDT with static timings.
The timing values are generated from the controller clock speed and
are more accurate than the hardcoded values that were in the ASL which
were originally copied from Broadwell where the controller is running
at a different clock speed...
Additionally it is now possible for a board to override the values
using devicetree.cb. If zero is passed in for SCL HCNT or LCNT then
the kernel will generate its own timing using the same forumla, but if
the SDA hold time value is zero the kernel will NOT generate a correct
value and the SDA hold time may be incorrect.
This was tested on the Chell platform to ensure all the I2C devices on
the board are still operational with these new timing values.
Change-Id: I4feb3df9e083592792f8fadd7105e081a984a906
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15291
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Provide the initial NHLT support for the following hardware:
1. 2 channel digital microphone array
2. Dialog 7219 headset
3. Maxim 98357 speaker amplifiers.
The code utilizes the Intel SoC common NHLT support.
Change-Id: Ic31e834a08f29c66512a7a63ad7bb35e0374e86a
Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15504
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
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The nvs.h header is the one which defines global_nvs_t proper.
Don't rely on an indirect inclusion.
Change-Id: I89d6a73f65e408c73f068b4a35b5efd361a6e5d3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15503
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
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Every other platform has global_nvs_t as a typedef. For some
reason apollolake didn't bother following current conventions.
Fix this omission to allow for better code sharing and consistency.
Change-Id: Id596eed517737759a64ce803c89ea2a05cbe2cce
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15502
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
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This patch exposes a function to read pmc bar.
PMC bar is read in function read_pmc_mmio_bar which
is defined static in file pmutil.c. This patch exposes
that functionality to call it from other files.
BUG=chrome-os-partner:53438
TEST= Read the PMC bar value properly from outside
pmutil file.
Change-Id: I26ee13e6ab95d3a8991c7f8ea4b3856ceb015d10
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15460
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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