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2022-07-06soc/intel/alderlake: Add check for CSE FW sync in romstageKrishna P Bhat D
Some Alder Lake-N boards will use compressed ME RW blobs to obtain savings on the SPI size (1916KB before compression, ~1132KB after compression). So add an additional check before calling cse_fw_sync() from romstage. When compressed blobs are used, the call to CSE firmware update has to be in post-RAM stages. BRANCH=firmware-brya-14505.B Change-Id: I0d9ede52cb493974e4ba6e2e2cf11c9789b3b087 Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63760 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-05nb,soc/intel: Handle upper RAM boundaryKyösti Mälkki
Change-Id: I2d99523647dfb43265db8f2701b525afd1870fc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-05soc/intel/meteorlake: Enable X2APICSubrata Banik
This patch enables X2APIC to avoid hang-ups due to `Switching from X2APIC to XAPIC mode is not implemented.`  BUG=b:237924211 ([MTL-FSP][v2222.1] Lists of boot issue with MTL FSP) TEST=Able to enable X2APIC on rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I58649a9a6c9c0ba86856f6aa5fb470e2ef774e90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65617 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-05soc/intel/baytrail,braswell,quark: Drop RES_IN_KIBKyösti Mälkki
Change-Id: I2360a1a79f07ff8466ed01aa7f180d410e019292 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-04soc/intel/alderlake: RPL-P power limits and VR settingsJeremy Compostella
This patch sets the Power Limits and Voltage Regulator settings for three RaptorLake SKUs (45W, 28W and 15W) following the guidance from document 686872 (June 7th edition). BUG=b:237809660 TEST=Power Limit and VR serial logs review + debug instrumentation SKUs successfully booted Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I7e9d4039615e6c33b869c6243efbfeb2259ac219 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65582 Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-04mb/qemu-i440fx,soc/nvidia: Fix coverity reported defectsKyösti Mälkki
In reality the expression should not overflow as the value fits in 32 bits. Change-Id: I50d83dce25a4d464e1c979502c290d8ecd733018 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-04soc/intel/alderlake: remove unnecessary test conditionJeremy Compostella
mch_id is set to zero and then unnecessarily tested. TEST=build and boot image on ADL RVP board Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I4f48742b04edd50fbc0db342b563534e709d6fdd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-04soc/intel/alderlake/fsp_params.c: Handle CnviWifiCore parameterMichał Żygowski
Platform with public FSP hooked-up have an additional parameter to control CNVi WiFi with CnviWifiCore UPD. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I19efb645fbe1530a571c92d0573c1c60ff6605a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-04soc/intel/alderlake: Hook up ADL-P and ADL-S public FSPMichał Żygowski
Update 3rdparty/fsp submodule to include AlderLake FSP. Hook up the Kconfig settings to point to Fsp.fd and headers for ADL-S and ADL-P platforms which the FSP has been published for. The FSP binaries are compliant with the specification revision 2.3 so update these settings accordingly. Although FSP header is v2.3 compliant, the features set of the FSP v2.3 is not being met. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I577931da7952b681534bb78b7b2c7683cd99febd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65519 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-04soc/qualcomm/sc7180: Update hardware watchdog loggingKshitiz Godara
Move watchdog functionality to common folder. BUG=b:221393157 TEST=None Signed-off-by: Kshitiz Godara <quic_kgodara@quicinc.com> Change-Id: Ib2f7f21ce991fd8193329e7b8260e58e47bf39c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-04treewide: Unify Google brandingJon Murphy
Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-04soc/amd/sabrina: Add support for Rembrandt SoC as base SoCRitul Guru
This change adds new Rembrandt SoC support by defining it as base SoC of sabrina as sabrina is derived from Rembrandt SoC. All the needed changes for Rembrandt SoC will be applied under SOC_AMD_REMBRANDT config. Change-Id: I1c9392918cc2c6b511d467f99aceefc725750ce6 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-04soc/mediatek/mt8188: Add a stub implementation of the MT8188 SoCRex-BC Chen
Add new folder and basic drivers for Mediatek SoC 'MT8188'. Difference of modules including in this patch between MT8188 and existing SoCs: Timer: Similar to MT8195 and MT8186, MT8188 uses v2 timer. EMI/PLL/SPI: Different from existing SoCs. The implementation is based on these files: MT8188G_Application Processor Technical Brief_v0.4.pdf MT8188G_Functional Specification v0.4.pdf MT8188 Application Processor Registers-1.pdf MT8188 Application Processor Registers-2.pdf TEST=saw the coreboot uart log to bootblock BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I3320f3d49a9b9ed781ceb812e4341e379db4ac20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65585 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@chromium.org>
2022-07-03soc/intel/meteorlake: Use coreboot native event handler for FSP-M/SSubrata Banik
This patch assigns FSP handler event for FSP-M and FSP-S with coreboot romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig is enabled. BUG=b:237263080 TEST=Able to build and boot MTL simics. Also, verified the FSP debug log is using coreboot debug library as below: Before: Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000F961B000, size is 0x00150000, handle is 0xF961B000 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 With this code change: [SPEW ] Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE [SPEW ] Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 [SPEW ] Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A [SPEW ] The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000 [SPEW ] Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 [SPEW ] Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 [SPEW ] Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I80ba73afed642e6d21c5310e9bf734f6f7170347 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-01soc/intel/mtl: Add GPIOs for Meteor Lake SOCRavi Sarawadi
Add definitions for the GPIO pins on Meteor Lake SoC, as well as GPIO IRQ routing information and supporting ACPI ASL. For now, add the following GPIO communities and GPIO groups: Comm. 0: GPP_CPU, GPP_V, GPP_C Comm. 1: GPP_A, GPP_E Comm. 3: GPP_H, GPP_F, SPI0, VGPIO3 Comm. 4: GPP_S, JTAG Comm. 5: GPP_B, GPP_D, VGPIO BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I7fe9654f22b074a9af18eb7bcdc21812dee77035 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64169 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-30soc/qualcomm: Do resource transitionKyösti Mälkki
For ipq806x this fixes two resources getting declared with same index. The latter previously overwrote former. Change-Id: Ifee321d930d5433c824e2e977f1bb455766582f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-30soc/intel/common: Compile debug_feature in ramstage to fix build errorKrishna P Bhat D
In ADL-N, cse_fw_sync is done in ramstage. Compile debug_feature.c in ramstage to fix build error. BRANCH=firmware-brya-14505.B Change-Id: I0118b024fce4781cf6008b1c0b416e409fc52065 Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63979 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-30soc/alderlake: Enable all bits for IO decode / enable registerSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I86423c45ca33a79d3d8cf8e4ca4737da94a4aa4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-06-30soc/intel/common: Update CSE FW update flow for compressed ME_RW blobsKrishna P Bhat D
In the CSE FW update flow, update is triggered when there is a mismatch in CSE versions. CSE RW blob is directly mapped from SPI flash, hashed, compared and then the CSE RW region is updated. However, in the case of compressed blobs, we cannot directly map the blobs from SPI. It needs to be decompressed before the hash is calculated and compared. Add a check for compressed blobs and figure out whether it needs to be directly mapped from SPI or loaded into memory allocated for file in CBMEM, with the provided CBMEM ID. BRANCH=firmware-brya-14505.B Change-Id: I3bc7708c95272e98702bc25b2334e6e64a93da8a Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-30common/block/cse: Add Kconfigs to indicate when CSE FW sync is performedKrishna Prasad Bhat
CSE FW sync is currently performed in romstage, when uncompressed ME_RW blobs are used. When compressed blobs are used, this has to be done in post-RAM stages. Add Kconfigs to describe when the CSE FW sync will be performed, in romstage or in ramstage. BRANCH=firmware-brya-14505.B Change-Id: Iac37aaa5ede5e1cd2d76a58ce2db9cb5b8f42398 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65366 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-30soc/intel/alderlake: Add BUILDING_WITH_DEBUG_FSPKangheui Won
Intel FSP has "debug" build which is not public, used for debugging by approved developers. Add a Kconfig to indicate that coreboot is building with debug version of FSP so we can adjust few things (i.e. flash layout) in the case. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ibc561498d7edcb9d7ec155f090822f1eb25d10cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65466 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-30soc/intel/alderlake: add chipset devicetree for ADL-SMichał Kopeć
Add chipset devicetree and power limits for AlderLake-S platform. Based on Intel docs #619501, #619362 and #626343. Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2022-06-30soc/nvidia/tegra124: Do resource transitionKyösti Mälkki
Change-Id: I422ece7b64bf81bcc75a414fd27f15ec330d40be Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-30soc/amd/common/psp: Revert AMD_SOC_SEPARATE_EFS_SECTIONFred Reitberger
Reverting commit 1e25fd426ad8 ("soc/amd/common/block/psp: introduce AMD_SOC_SEPARATE_EFS_SECTION"). A better solution was used in commit c17330c1dddb ("mb/amd/chausie: Add EC blob into CBFS"), and this is no longer necessary. TEST: Boot chausie Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I27a8622a1f0d871690b181a79adca225a20996ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-30soc/intel/alderlake: Add ADL-S PCI IRQ constraintsMichał Żygowski
Add ADL-S specific table with IRQ constraints to avoid accessing non-existent devices. Also when using debug FSP, silicon init would assert on assigning IRQs for non-existent devices. This patch fixes the problem. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib4464a85bc11a8603bf471ea348bbfc9481db4aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-30soc/intel/alderlake/iomap: Correct the ADL-S reserved rangeMichał Żygowski
Due to incorrectly interpreted DOC #630603, the reserved range remains the same for all ADL platforms and is sync with src/soc/intel/common/block/acpi/acpi/northbridge.asl which defines the range as 0xfc800000-0xfe7fffff. The range 0xfe000000-0xfe7fffff was only mean for static allocations, but the rest is also reserved. The only difference between ADL-S and other ADL platforms is Trace Hub base. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I9b1f79cc351de422acf182c27870c29dbe57fe4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-29soc/intel/jasperlake: Fix PMC read_resources callbackTim Wawrzynczak
The `limit` field for the PMC fixed BAR was incorrectly set to the `base + size + 1`, where it should be `base + size - 1`, to correctly tell the allocator the limit. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Icf51333f438ce2597c008b48305cf5816dacd3f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65461 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29soc/intel/elkhartlake: Fix PMC read_resources callbackTim Wawrzynczak
The `limit` field for the PMC fixed BAR was incorrectly set to the `base + size + 1`, where it should be `base + size - 1`, to correctly tell the allocator the limit. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib2d8c7ffe87fdd970f3172bb4e6b2c9386859ab3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65460 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29soc/cavium,ti: Do resource transitionKyösti Mälkki
Change-Id: I0b9bd00a5de4c2c8d91fa9d595d3ee313356048a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-29soc/intel/mtl/acpi: Add SoC ACPI directory for Meteor LakeRavi Sarawadi
List of changes: 1. Select common ACPI Kconfig to include common ACPI code block from IA-common code 2. Select ACPI Kconfig support for wake up from sleep states. 3. Add SoC ASL code in ASL 2.0 syntax for SoC IPs like IPU, ISH, LAN, HDA etc. BUG=b:224325352 TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'. Change-Id: Iebe3d38f50e202d75add88f336b5f3e9ba9f5a22 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64168 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29soc/intel/mtl: Do initial Meteor Lake SoC commit till ramstageRavi Sarawadi
List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Fill required FSP-S UPD to call FSP-S API BUG=b:224325352 TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ie746c0bfcf1f315a4ab6f540cc7c4933157551d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63364 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29soc/intel/meteorlake: Change VBOOT_HASH_BLOCK_SIZE to 4 KiBSubrata Banik
Default VBOOT_HASH_BLOCK_SIZE is 1 KiB and increasing it to 4 KiB helps in improving overall boot time since it reduces hashing and body loading time (~30ms). Backport changes from commit hash 84532dae1 (soc/intel/alderlake: Change VBOOT_HASH_BLOCK_SIZE to 4 KiB). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3784b99bf06e0c03d123f290a98a0b1e4528b8d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64792 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29soc/intel/mtl: Do initial Meteor Lake SoC commit till romstageRavi Sarawadi
List of changes: 1. Add required SoC programming till romstage 2. Include only required headers into include/soc 3. Fill required FSP-M UPD to call FSP-M API BUG=b:224325352 TEST=Build 'util/abuild/abuild -p none -t google/rex -a -c max'. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I3d5c6ceb7f97429ff903e7577186e8d8843c1f14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63363 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-28soc/intel: Add Raptor Lake device IDszhixingma
Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs. References: RaptorLake External Design Specification Volume 1 (640555) 600/700 Series PCH External Design Specification Volume 1 (626817) BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=Booted to OS on adlrvp + rpl silicon Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: I8e8b9ec6ae82de7d7aa2302097fc66f47b782323 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65117 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-28soc/intel/apollolake: Add chipset devicetreeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic2b9a22bc6c32030f960d59b2874be5459c3ba28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-28soc/intel/alderlake/fsp_params.c: Fill PCI SSID parametersMichał Żygowski
Code taken from TGL base. TEST=Boot MSI PRO Z690-A WIFI DDR4 and see all devices have SSID applied Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I3a6d299ec40bac8e29d06926572e375d7d835e29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-28soc,sb/amd: Change SPI controller resourceKyösti Mälkki
This replaces IORESOURCE_SUBTRACTIVE with IORESOURCE_RESERVE. Change-Id: Ib3d934ca704273daacbeb3c52412bf04e2be7217 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64695 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-28soc/alderlake: Add ADL-S PCIe supportMichał Żygowski
Extend the code to support ADL-S PCIe Root Ports. Based on DOC #619362 and #619501. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ibb57ad5b11684c0079e384d9a6ba5c10905c1a23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63654 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-28soc/intel/alderlake/acpi: Add ADL-S devicesMichał Żygowski
Add PCIe Root Ports, USB ports and SIO devices for ADL-S chipset. Add IRQ routing tables for PCIe Root ports up to 28th. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I508fa1396b07f38801bcf50cdfdc876356d7ae9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63785 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-27soc/intel/*/Kconfig: Fix typo in commentAngel Pons
clcok ---> clock Change-Id: Ie41524f6500479162984fa9050d942f4e295f00a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-27soc/intel/alderlake: Implement MultiPhase SI Init Index 2 callbackSubrata Banik
The details about how the CPU multiprocessor init (MP) has migrated from coreboot to FSP can be found in https://doc.coreboot.org/soc/intel/mp_init/mp_init.html. The major reason behind this migration is to support the Intel proprietary and restricted CPU feature programming which can't be performed if coreboot sets the BIOS_DONE or BIOS Reset CPL as part of coreboot MP Init flow (prior to calling FSP-S). Hence, the new flow introduced with Tiger Lake platform forced having monolithic MP Init peformed by FSP (using coreboot MP PPI wrapper code). The last 3-4 years of FSP doing MP Init has demonstrated ample issues during platform bringup which is specific to UEFI MP Service implementation and not relevant to open source coreboot. This new flow makes the debug and validation aspect complicated where any FSP MP Init code changes should have been validated with coreboot MP PPI wrapper else might cause some failure, unfortunately, the validation commitment has never been met, hence, issue debugging is the only solution that remains in practice. Most importantly, the restricted feature programming which demanded closed source MP Init (for features like SGX and C6DRAM) has never been enabled in coreboot (starting with Alder Lake, the SGX feature has been dropped). This patch attempts to decouple FSP-S doing MP Init from the rest of the FSP-S silicon init and introduces 2nd MultiPhase SI init which allows bootloader to perform the mandatory SoC programming before FSP-S has done with PM programming (a.k.a set the reset CPL). The core/uncore BWG suggests the minimum SoC programming before BIOS Reset CPL is set. coreboot uses the MultiPhaseSI Init Index 2 to perform the required CPU programming before enabling the BIOS Reset CPL. This implementation would allow us to get rid of FSP running CPU feature programming and additionally make several EDK2 MP service modules optional (those are packed to create FSP-S blob). In summary, this change would allow coreboot to utilize open source MP init without running into FSP-S related code blocks. Note: At present, Intel Alder Lake FSP doesn't have support for MultiPhase SI Init, Index 2 (submitted a FSP code changes over chrome-internal to enable this feature to decouple MP Init from FSP-S init). BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Perform several thousands cycles of suspend test and power cycle without running into any issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I314c63c917ef6fdd32f364b2c60bae22486b8b74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64979 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-27soc/qualcomm: Make sc7180 mdss configurations common codeVinod Polimera
This change makes mdss configuration common for both sc7180 & sc7280 to avoid code duplicacy. Changes in v2: - Move soc related mdss changes to soc specific disp.c BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Monitor name: LQ140M1JW49 Change-Id: Ibc43ab6ee5ced08e34625e1485febd2f4717d6a0 Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-06-27soc/intel/common/block/gpio: Add gpio pad based functionEric Lai
Introduce three functions: - new_padbased_table: Returns the gpio pad number based table - gpio_padbased_override: Must pass the table with padbased table - gpio_configure_pads_with_padbased: Must pass the table with padbased table, will skip configures the unmapped pins by check pad and DW0 are 0. Some boards may have complex, SKU-based GPIO programming. This patch provides for a simpler pattern of controlling overrides of GPIO programming by providing a table of pad configuration indexed by pad number. Thus, pad state can be overwritten over multiple overrides until the final takes place, and then all GPIO programming is performed at once. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I8b99127b73701b50a7f2e051dee9d12c9da9b741 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64712 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-26soc/intel/baytrail,braswell: Do resource transitionKyösti Mälkki
Change-Id: Ia44be7d63b0e6e16a49695d430715a7e5785d530 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55925 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-26soc/samsung/exynos: Do resource transitionKyösti Mälkki
Change-Id: I9c680d12f023d8682288e9d3619f549484f3b975 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55915 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-26soc/rockchip: Do resource transitionKyösti Mälkki
Change-Id: I80ee3a8bb28d5f7b2a47b0a98abbc53a95ad25bc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55917 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-26soc/nvidia/tegra210: Do resource transitionKyösti Mälkki
Change-Id: I0e68912bf7f1ccb130b8bc6213308ec2e846efc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55920 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-26soc/mediatek: Do resource transitionKyösti Mälkki
Change-Id: I668a39c603870329fd1528ddc5f3a42a379e1e76 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65267 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-26soc/intel/xeon_sp: Do resource transitionKyösti Mälkki
Replace xx_resource() calls with calls that take the base and size arguments as-is, without dividing by KiB (or >> 10). With replacement of the allocator/constructor function caller can use log_resource() instead. Change-Id: I7e4e1e5a779c418f369dd2dab8c811f67ad1399f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55477 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-26soc/intel/alderlake: Drop debug interface selectionSubrata Banik
This patch drops FSP Debug interface selection as coreboot now decides the UART inerface to redirect the debug msg. BUG=none TEST=Able to see all coreboot and FSP debug log with and without this patch. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If8c07d7e63c5d445fdb77ac38b99217bf015e15f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-24device/resource: Modify some resource allocation instancesKyösti Mälkki
These changes made my crude pattern matching work with coccinelle simpler. Change-Id: I83f3ef38b8663640594b4d726838f7a6f96a58a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-24soc/amd/common/block/noncar/cpu: Provide correct smbios processor familyFred Reitberger
Return the correct processor family code for smbios per System Management BIOS (SMBIOS) Reference Specification DSP0134 revision 3.5.0. BUG=b:234409052 TEST=Boot chausie to chromeos and verify "dmidecode -t processor" outputs the correct processor family. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I617ce3e23f4b28a197034756d285339595d3b53b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65364 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-24sc7180/sc7280: Add missing set_resourcesKshitiz Godara
Added missing set_resources function to avoid error messages in boot up logs. BUG=b:230576402 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Kshitiz Godara <quic_kgodara@quicinc.com> Change-Id: Ie0a5bd345486293ce07e586a423d53740ad377f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-06-24soc/intel: Move top_swap Kconfig symbols into soc/intel/commonMartin Roth
Move the Intel top_swap feature into the intel/common Kconfig file. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3ed649aaeb51c2250be9473114c17d3f191d2c38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-24src/soc: Get rid of most src/soc/Kconfig filesMartin Roth
Most of the src/soc/Kconfig files are only there for AMD and Intel to load the main SoC Kconfig files before any common files. That can be done in src/Kconfig instead. Moving the loads to the lower level allows the removal of all but the Intel soc/Kconfig file, which can be removed in a follow-on patch. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5061191fe23e0b7c745e90874bd7b390806bbcfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-06-24soc/mediatek: Clean up Makefile.inc for mt8186, mt8192 and mt8195Yidi Lin
Clean up Makefile.inc by sorting entries and moving common entries to all-y. In this way it is more clear to know what drivers have been involved in each stage and the hardware differences between each SoC. BUG=none TEST=emerge-corsola coreboot TEST=emerge-asurada coreboot TEST=emerge-cherry coreboot Change-Id: Idfc7de36ebf36650f7c6bd1584ef77e2a540cde9 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65315 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-23soc/intel/adl: Cast size in systemagent.c to fix overflowEran Mitrani
This CL fixes my previous CL (commit ca741055e) which introduced a couple of issues found by Coverity (see below). The Coverity explanation is: "Potentially overflowing expression "size_field * 1048576U" with type "unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned)." *** CID 1490122: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /src/soc/intel/alderlake/systemagent.c: 305 in get_dpr_size() *** CID 1490121: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /src/soc/intel/alderlake/systemagent.c: 254 in get_dsm_size() BUG=b:149830546 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage' builds correctly. Tested on an Anahera device which successfully boots to ChromeOS with kernel version 5.10.109-15688-g857e654d1705. Change-Id: Ib2d66ad24a5ad67b51036ad376a6938f698134c3 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65212 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-23soc/intel/alderlake/romstage: Add desktop UserBd optionsMichał Żygowski
Add the desktop board types as per DOC #573387. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8cca98f0fac51e537b472958ee602e116b48f6d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-06-23soc/intel/alderlake: Fix PRMRR resource range calculation issueSubrata Banik
This patch fixes an issue introduced with commit ca741055e (soc/intel/adl: Add missing claimed memory regions) where PRMRR base should be read using MSR 0x2a0 and mask from MSR 0x1f5 instead System Agent PCI configuration space. With this change, coreboot is able to read PRMRR base when the PRMRR size > 0. TEST=Able to read PRMRR base MSR 0x2a0 in proper with this CL. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3770b1a92dbd2552cf1b9764522c9cac9f29c13c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eran Mitrani <mitrani@google.com>
2022-06-23soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_ACPI_GPIOFelix Held
The common AMD ACPI GPIO access code is verified to be correct for Sabrina. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I834076c0a1d1784a272896f2d8f082ebfb86a383 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-23soc/amd/sabrina: remove TODOs from MCA code/configFelix Held
The MCA banks were updated in commit 736d68c0b36e ("soc/amd/sabrina/mca: update MCA bank names to match the hardware"), but seems that I forgot to remove the TODO about checking if this is still correct for Sabrina. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd86113ccb9eeab704679afab0b985f9febed13b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65314 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-23soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_UCODEFelix Held
The common microcode update mechanism is verified to be correct and work on Sabrina. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5c41674299a829507438beb3ea597a71a0c5a972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-23soc/amd/sabrina/Kconfig: set soft fuse bit 34Felix Held
The bits are documented in NDA document #55758. BUG=b:228458221 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibc27f617ca9c9620b3b2cb0837b661fa0cd36c2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-23soc/intel/apollolake: Enable SATA Power OptimisationSean Rhodes
Enable PwrOptEnable FSP S UPD and hook it to the inverted value of SataPwrOptimizeDisable to allow it to be disabled from the devicetree. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I056fd7b16dadb213b3326523b0c7943ce35b8dc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-22soc/intel/tigerlake: Replace spaces with tabsSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9b64375d905d93a8db726202ed2ce932fa536da3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-22security/vboot: Deprecate VBOOT_VBNV_ECYu-Ping Wu
Boards using VBOOT_VBNV_EC (nyan, daisy, veyron, peach_pit) are all ChromeOS devices and they've reached the end of life since Feb 2022. Therefore, remove VBOOT_VBNV_EC for them, each with different replacement. - nyan (nyan, nyan_big, nyan_blaze): Add RW_NVRAM to their FMAP (by reducing the size of RW_VPD), and replace VBOOT_VBNV_EC with VBOOT_VBNV_FLASH. - veyron: Add RW_NVRAM to their FMAP (by reducing the size of SHARED_DATA), and replace VBOOT_VBNV_EC with VBOOT_VBNV_FLASH. Also enlarge the OVERLAP_VERSTAGE_ROMSTAGE section for rk3288 (by reducing the size of PRERAM_CBMEM_CONSOLE), so that verstage won't exceed its allotted size. - daisy: Because BOOT_DEVICE_SPI_FLASH is not set, which is required for VBOOT_VBNV_FLASH, disable MAINBOARD_HAS_CHROMEOS and VBOOT configs. - peach_pit: As VBOOT is not set, simply remove the unused VBOOT_VBNV_EC option. Remove the VBOOT_VBNV_EC Kconfig option as well as related code, leaving VBOOT_VBNV_FLASH and VBOOT_VBNV_CMOS as the only two backend options for vboot nvdata (VBNV). Also add a check in read_vbnv() and save_vbnv() for VBNV options. BUG=b:178689388 TEST=util/abuild/abuild -t GOOGLE_NYAN -x -a TEST=util/abuild/abuild -t GOOGLE_VEYRON_JAQ -x -a TEST=util/abuild/abuild -t GOOGLE_DAISY -a TEST=util/abuild/abuild -t GOOGLE_PEACH_PIT -a BRANCH=none Change-Id: Ic67d69e694cff3176dbee12d4c6311bc85295863 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-22soc/intel/alderlake: add GPIO definitions for PCH-SMichał Kopeć
Add GPIO definitions for ADL-S, similarly to how TGL/TGL-H handles the split. Based on: - Intel PCH-S EDS Vol2 (#621483) - Alderlake-S FSP - slimbootloader sources - Linux alderlake-pinctrl driver Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-22soc/amd/picasso/acpi: Add missing UART resourcesMatt DeVillier
Both UART and DMA MMIO regions for each UART are mapped by the UEFI reference code, so do the same here. Without these defined, UART-attached devices fail to correctly initialize under Windows. Change-Id: I0e1af9028c7c1746407e923cebe824a15aeb565e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65233 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-22soc/intel/alderlake: Remove menu option for MAX_PCIE_CLOCK_SRCCliff Huang
MAX_PCIE_CLOCK_SRC is not an user-configurable option. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: Ia49f6e236e8853c377e9096500d96f21dbdc9b8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65298 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22soc/intel: Add Meteor Lake SA device IDSubrata Banik
Add Meteor Lake SA device ID 0x7d14 (4+8, 15W). BUG=b:224325352 TEST=Able to build MTL SoC and verified SA DID is now shown proper. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I051a40136ed89e837945bf4569c77d2a80375ed6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65111 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22soc/cannonlake: Hook up Comet Lake U 06-a6-01 microcodeMichał Żygowski
The file is already present in the microcode submodule repository. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib284908db165dc95a5895979174512818f2aceff Reviewed-on: https://review.coreboot.org/c/coreboot/+/65292 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22soc/intel/mp_init: Skip before_post_cpus_init if !USE_COREBOOT_MP_INITSubrata Banik
This patch ensures all APs finish the task and continue before_post_cpus_init() if coreboot decides to perform multiprocessor initialization using native coreboot drivers instead of using FSP MP PPI implementation. BUG=b:233199592 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3b76974ab19323201bf1dca9af423481a40f65c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65173 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22soc/intel/alderlake: Allow possible options for MP InitSubrata Banik
This patch creates choice that lists all possible options to perform MP Init as below: 1. USE_FSP_MP_INIT: Allow coreboot to bring APs from reset and FSP runs feature programming based and selects MP_SERVICES_PPI_V2 config. 2. USE_COREBOOT_MP_INIT: Allow coreboot to perform MP Init (both AP init and feature programming) using native implementation. Additionally, selects required RELOAD_MICROCODE_PATCH when coreboot is expected to run MP Init. Refactor SoC code to allow required FSP UPD override based on selected MP Init option. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I20adc1935890c4c6bcd11fd086838f15d0723932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64977 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22soc/intel/cmn/block/cpu: Perform PRMRR sync on all coresSubrata Banik
This patch ensures to perform core PRMRR sync if SoC decides to perform MP Init using coreboot native implementation. Also, implement a function to allow calling `init_core_prmrr()` for all CPUs from `before_post_cpus_init()`. BUG=b:233199592 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9b6222c98ff278419fa8411054c0954689e1271e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64978 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22intel/mp_init: Call `intel_reload_microcode()` before post_cpus_init()Subrata Banik
This patch calls into `intel_reload_microcode() function to load second microcode patch after BIOS Done bit is set and before setting the BIOS Reset CPL bit. Also, remove redundant microcode reloading debug print. BUG=b:233199592 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Icb3fcfd7ef5478be0a40f8f1358f55c0247b4914 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65157 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22intel/broadwell,lynxpoint: Change formula around 4 GiBKyösti Mälkki
Let's not rely on the type to get the correct result, casting 0 to 0ull made the result wrong. Change-Id: I6dfba3800170fdd4267e3bb74c55b05533c101fc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-21soc/amd/*/Kconfig: drop unused SOC_AMD_COMMON_BLOCK_UCODE_SIZE optionFelix Held
Commit 96f7b96866b0bce7a1323c4da478f838f884383f (soc/amd/common/block/ cpu/: Make ucode update more generic) removed the code that used the SOC_AMD_COMMON_BLOCK_UCODE_SIZE Kconfig value. Drop the now unused Kconfig option. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I079f229678452ff20d8bb282804cd2e49555a6fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65255 Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-21soc/amd/common/i2c: Add i2c bus ops handlerMatt DeVillier
Without this, calls to i2c_link() and runtime i2c detection fails on AMD common platform boards. Test: Runtime i2c detection of correct touchpad model succeeds on google/zork. Change-Id: I238b680b2afb4b9d3e5ac75fe9e630b2adc74860 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-21soc/amd/*: Move selection of DRIVERS_I2C_DESIGNWARE to common blockMatt DeVillier
All AMD SoCs which select SOC_AMD_COMMON_BLOCK_I2C also select DRIVERS_I2C_DESIGNWARE, so make the pairing explicit by moving the selection into SOC_AMD_COMMON_BLOCK_I2C. This will facilitating adding the Designware I2C bus ops handler in a subsequent commit. Change-Id: Ice30c8806766deb9a6ba617c3e633ab069af3b46 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-06-20soc/intel/apollolake: Hook Up SataPortEnable to devicetreeSean Rhodes
Hook Up SataPortsEnable to the devicetree. As the default value is 0, set both [0] and [1] in all mainboards so they aren't affected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ica8cf9484a6e6fe4362eabb8a9a59fcaf97c1bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64524 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20soc/intel/alderlake/chip.c: Add missing ADL-S USB ports ACPI namesMichał Żygowski
ADL-S has more USB ports than mobile chipsets. Add missing ACPI names. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ice5f7784f9de0364681be00fc5cc445caf9d1b3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63655 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20soc/amd/stoneyridge: Align get_cpu_count to other targetsArthur Heymans
The CPUID function to get the number of cores on a package is common across multiple generations of AMD cpus. Change-Id: I28bff875ea2df7837e4495787cf8a4c2d522d43d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64869 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-20soc/amd/*: Make mtrr decision based on syscfgArthur Heymans
The syscfg has to option to automatically mark the range between 4G and TOM2, which contains DRAM, as WB. Making it generally not necessary to allocate MTRRs for memory above 4G if no PCI BARs are placed up there. Change-Id: Ifbacae28e272ab2f39f268ad034354a9c590d035 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-20soc/intel/apollolake: Hook up C1e to enhanced_cstatesSean Rhodes
Hook up C1e FSP S UPD which enables enhanced C-states, to enhanced_cstates. This allows it to be enabled in the devicetree with a value of "1" as the default is disabled. C1e exists on both APL and GLK, and has been there since their initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie803a75ac9fb64a6c21b31baeea7b736e4fbf5fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/64708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20soc/intel/apollolake: Hook up UfsEnabled to devicetreeSean Rhodes
Hook up FSP S UfsEnabled UPD (1d.0) to devicetree. UFS only exist on GLK, and has been there since its initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1976bfd340c728c64aaf36d296ac41dcd47bfc61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20soc/intel/apollolake: Allow configuring the LPC IO registersSean Rhodes
Allow configuring the LPC IO registers in the devicetree with: * gen1_dec * gen2_dec * gen3_dec * gen4_dec Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2a7ab3faf927cda76640227feff4e19017442897 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-18soc/intel/alderlake: Skip PCIe source clock assignment if incorrectCliff Huang
When an enabled root port without pcie_rp clock being specified, the empty structure provides invalid info, which indicates '0' is the clock source and request. If a root port does not use clock source, it should still need to provide pcie_rp clock structure with flags set to PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it is considered that pcie_rp clock structure is not provided for that root port. Add check and skip for enabled root port that does not have clock structure. In addition, a root port can not use a free running clock or clock set to LAN. Note that ClockUsage is either free running clock, LAN clock, or the root port number which consumes the clock. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I17d52374c84ec0abf888efa0fa2077a6eaf70f6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-17soc/intel/{alderlake, common}: Rename the pre_mem_ft structureSridhar Siricilla
The patch renames identifiers (macros, function and structure names) in the basecode/debug/debug_feature.c to generic names so that they can be used to control the features which may have to be controlled either during pre and post memory. Currently, the naming of identifiers indicate that it meant to control the features which can be controlled during only pre-memory phase. TEST=Build code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I53ceb25454027ab8a5c59400402beb6cc42884c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-17soc/amd/smm_relocate.c: Improve TSEG programmingArthur Heymans
TSEG does not need to be aligned to 128KiB but to its size, as the MSR works like an MTRR. 128KiB is a minimum TSEG size however. TESTED on google/vilboz. Change-Id: I30854111bb47f0cb14b07f71cedacd629432e0f4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64865 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-17soc/intel/denverton_ns: enable Denverton to use common msr definesJeff Daly
Use Intel common SoC msr.h for Denverton refactor Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Ic5f99fbcd2f936d4e020bd9b74b65dcd6e462bdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61016 Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-17soc/intel/denverton_ns: enable Denverton to use common SoC SPI codeJeff Daly
Use Intel common SoC SPI code for Denverton refactor Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Ic1d57c6b348adb934785b0e2bec4e856f0bf8d77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61014 Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17soc/intel/denverton_ns: Define macro TOTAL_PADSEric Lai
Define total GPIO pins as TOTAL_PADS. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I220b6f1a968667a68c30c7287ab5af1912959e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-17soc/intel/xeon_sp: Define macro TOTAL_PADSEric Lai
Define total GPIO pins as TOTAL_PADS. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ic7c48415d1fa3067ac62520a542058e7cab45941 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-06-17soc/intel/skylake: Define macro TOTAL_PADSEric Lai
Define total GPIO pins as TOTAL_PADS. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I40294339c79f5db1850ccd546292c67169890b2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65161 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17soc/intel/alderlake/report_platform.c: Add ADL-S identificationMichał Żygowski
Based on DOC #619501, #619362 and #618427 TEST=Boot MSI PRO Z690-A DDR4 WIFI and see the silicon info is reported as ADL-S. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8051113515ef63fc4687f53d25140a3f55aadb6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-16soc/intel/alderlake: Unselect USB4 and TCSS options for ADL-SMichał Żygowski
Alder Lake-S CPUs do not have TCSS and USB4 devices. Unselect them. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ifc643d440107754dfe1a0844964f70de670cb1f1 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-16soc/intel/alderlake/fsp_params.c: Add VccIn Aux Imon IccMax for ADL-SMichał Żygowski
Based on DOC #619501. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia95404e717787edbdb67c9e584e749526b973427 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15soc/intel/adl: Add missing claimed memory regionsEran Mitrani
The Alder Lake chipset has several more reserved memory regions that are unavailable to the resource allocator than are currently marked as such in the system agent code. This CL adds the following regions (documented in Intel docs #626540, #619503): 1. TSEG 2. GSM 3. DSM 4. PCH_RESERVED 5. CRAB_ABORT 6. APIC 7. TPM 8. LT_SECURITY Claimed regions before this change: ======================================================== base 0 size a0000 // 0 - > 0xa0000 base a0000 size 20000 // legacy VGA base c0000 size 40000 // RAM base c0000 size 76f40000 // 0xc0000 -> top_of_ram base 77000000 size 9400000 // top_of_ram -> TOLUD base c0000000 size 10000000 // PCIEXBAR base f8000000 size 2000000 // MMSPI base fb000000 size 1000 // REGBAR base fed80000 size 4000 // EDRAMBAR base fed84000 size 1000 // TBT0BAR base fed85000 size 1000 // TBT1BAR base fed86000 size 1000 // TBT2BAR base fed87000 size 1000 // TBT3BAR base fed90000 size 1000 // GFXVTBAR base fed91000 size 1000 // VTVC0BAR base fed92000 size 1000 // IPUVTBAR base feda0000 size 1000 // DMIBAR base feda1000 size 1000 // EPBAR base fedc0000 size 20000 // MCHBAR base 100000000 size 17fc00000 // 4GiB -> TOUUD Claimed regions with this change: ======================================================== base 0 size a0000 // 0 - > 0xa0000 base a0000 size 20000 // legacy VGA base c0000 size 40000 // RAM base c0000 size 76f40000 // 0xc0000 -> top_of_ram base 77000000 size 9400000 // top_of_ram -> TOLUD base 7b800000 size 800000 // TSEG base 7c000000 size 800000 // GSM base 7c800000 size 3c00000 // DSM base c0000000 size 10000000 // PCIEXBAR base f8000000 size 2000000 // MMSPI base fb000000 size 1000 // REGBAR base fc800000 size 2000000 // PCH_RESERVED base feb00000 size 80000 // CRAB_ABORT base fec00000 size 100000 // APIC base fed40000 size 10000 // TPM base fed50000 size 20000 // LT_SECURITY base fed80000 size 4000 // EDRAMBAR base fed84000 size 1000 // TBT0BAR base fed85000 size 1000 // TBT1BAR base fed86000 size 1000 // TBT2BAR base fed87000 size 1000 // TBT3BAR base fed90000 size 1000 // GFXVTBAR base fed91000 size 1000 // VTVC0BAR base fed92000 size 1000 // IPUVTBAR base feda0000 size 1000 // DMIBAR base feda1000 size 1000 // EPBAR base fedc0000 size 20000 // MCHBAR base 100000000 size 17fc00000 // 4GiB -> TOUUD BUG=b:149830546 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage' builds correctly. Tested on an Anahera device which successfully boots to ChromeOS with kernel version 5.10.109-15688-g857e654d1705. Also ran dmseg, and saw the added regions in e820 prints. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I058a5c1cc59703e35ceddb8a7e26fb22a6a2b75e Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15soc/intel/common: support for configurable memory regions claimed by SAEran Mitrani
see https://review.coreboot.org/c/coreboot/+/65072/8 BUG=b:149830546 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage' builds correctly. Tested on an Anahera device which successfully boots to ChromeOS with kernel version 5.10.109-15688-g857e654d1705. Change-Id: I80df95f9146934d6a2d23e525c22be3a9a7e2b9f Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64677 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 02:26:11 +0000