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2021-10-17soc/intel/skylake: switch to common ACPI codeMichael Niewöhner
Use the common ACPI code to reduce code duplication. After this change, `PSS_MAX_ENTRIES` is honored correctly in P-state table generation (as of commit c2540a9) and the number reduces from 10 to 7 entries. Also, remnants of P_BLK support missed in CB:58096 will vanish. Tested on google/fizz: no errors in dmesg, ACPI tables remain the same (except PSS, as mentioned above). Change-Id: I1ec804ae4006a2d9b69c0d93a658eb3b84d60b40 Tested-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-10-17soc/intel/{common,apl,glk}: guard PM Timer option on SoCs w/o PM TimerMichael Niewöhner
Apollo Lake and Gemini Lake do not have a hardware PM ACPI timer but only uCode PM Timer emulation. Add a Kconfig `NO_PM_ACPI_TIMER` denoting SoCs without PM Timer and make it mutually exclusive with the Kconfig `USE_PM_ACPI_TIMER`. This is partly redundant to `PM_ACPI_TIMER_OPTIONAL`, which will be dropped in the follow-up change, though. Change-Id: Ic323bbfb7089c53a6f22724910a0ff3df8904ebd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel/*: only enable PM Timer emulation if the PM Timer is disabledMichael Niewöhner
uCode PM Timer emulation is only needed when the hardware PM ACPI timer is disabled. Also, since it redirects any register accesses to uCode, it overrides the hardware PM Timer. Thus, only enable emulation when required. Change-Id: I60a775bd6eb4206750f606ce8a8777d2e2dfb579 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel: transition full control over PM Timer from FSP to corebootMichael Niewöhner
Set `EnableTcoTimer=1` in order to keep FSP from 1) enabling ACPI Timer emulation in uCode. 2) disabling the PM ACPI Timer. Both actions are now done in coreboot. `EnableTcoTimer=1` makes FSP skip these steps in any possible case including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP Multiphase Init. This way full control is left to coreboot. Change-Id: I8005daed732c031980ccc379375ff5b09df8dac1 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lance Zhao
2021-10-17soc/intel/{skl,cnl,dnv}: disable PM ACPI timer if chosenMichael Niewöhner
Disable the PM ACPI timer during PMC init, when `USE_PM_ACPI_TIMER` is disabled. This is done to bring SKL, CNL, DNV in line with the other platforms, in order to transition handling of the PM timer from FSP to coreboot in the follow-up changes. For SKL and CNL, this temporarly redundantly disables the PM Timer, since FSP does that, too. This redundancy is resolved in the follow-up. Change-Id: I47280cd670a96c8fa5af107986496234f04e1f77 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel: implement ACPI timer disabling per SoC and drop common codeMichael Niewöhner
Since it's just a one-liner, implement disabling of the ACPI timer in soc code. This reduces complexity. Change-Id: I434ea87d00f6e919983d9229f79d4adb352fbf27 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel: move disabling of PM Timer to SoC PMC codeMichael Niewöhner
Move disabling of PM Timer to SoC PMC code. The original reason for placing that in `finalize` [1] was FSP hanging due to use of the PM timer without enabling timer emulation first in coreboot, which was added later [2]. [1] commit 6c1bf27dae (intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown) [2] commit f004f66ca7 (soc/intel/skylake: Enable ACPI PM timer emulation on all CPUs) Change-Id: I354c3aea0c8c1f8ff3d698e0636932b7b76125f7 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel/common: add possiblity to override GPE0 to acpi_fill_soc_wakeMichael Niewöhner
Currently, only the PM1_STS mask gets passed to `acpi_fill_soc_wake`. To be able to override the GPE0_STS mask as well, also pass that one. To accomplish that, pointers to the variables are passed now. Change-Id: If9f28cf054ae8b602c0587e4dd4a13a4aba810c7 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel/common/acpi: drop `RTC_EN` from static wake bits maskMichael Niewöhner
`RTC_EN` is in the RTC well* so we can rely on the actual register content instead of statically overriding it. Drop it from the static wake bits mask. * Tested on clevo/l140cu Change-Id: Ia0ae71f0a472513233bc0fd5625faf15bf86beaf Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-17soc/intel: deduplicate acpi_fill_soc_wakeMichael Niewöhner
The PM1_EN bits WAK_STS, RTC_EN, PWRBTN_EN don't need any SoC-specific handling. Deduplicate `acpi_fill_soc_wake` by setting these bits in common code. Change-Id: I06628aeb5b82b30142a383b87c82a1e22a073ef5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel/skylake: switch to common GNVSMichael Niewöhner
Switch to common GNVS. No additional fields to those being present in common GNVS are used by any SKL/KBL device. Thus, they're dropped completely. Change-Id: I87ab4ab05f6c081697801276a744d49e9e1908e0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-10-17soc/intel/common: add SGX fields to GNVSMichael Niewöhner
Add the SGX fields to the GNVS. This is required for Skylake to use the common GNVS. Change-Id: I0077260b7eb1bc2b2fe2af69ac039b38ca0e7423 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-16soc/amd/stoneyridge/include/iomap: rename I2C[ABCD]_BASE_ADDRESS definesFelix Held
Picasso and Cezanne define and use APU_I2C[01234]_BASE for the base addresses of the I2C controllers, so align Stoneyridge with this. The ACPI device names aren't changed from I2C[ABCD] to I2C[0123] for now since this might change behavior in the OS and would also change the resulting binary of a timeless build. TEST=Timeless build results in identical image for Google/Treeya. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9c400c073eba5c14bd35703b717f75df89a8719d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58370 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-16soc/intel/dnv_ns: enable uCode PM Timer emulationMichael Niewöhner
Denverton-NS supports uCode PM Timer emulation, according to Intel doc#558579 rev2.2. Thus, enable it. Change-Id: I21f55816da9f5e240fdf01a0e92b67b09ef38599 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-16soc/intel/pmc: add a note about legacy OSes/payloads to PM Timer KconfigMichael Niewöhner
Since ACPI 5.0A it is allowed to disable the ACPI Timer, when the according FADT flag `ACPI_FADT_PLATFORM_CLOCK` is unset. Starting with Skylake, most platforms (except Xeon-SP) support PM Timer emulation, so even legacy OSes and payloads should work fine with the hardware PM Timer disabled. However, when the `TMR_STS` functionality is required, some legacy OSes might still not work (properly). Add a note about this to the Kconfig help. Change-Id: I53f1814113902124779ed85da030374439570688 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lance Zhao
2021-10-16soc/intel/{common,skl}: set ACPI_FADT_PLATFORM_CLOCK based on KconfigMichael Niewöhner
The FADT contains a flag `ACPI_FADT_PLATFORM_CLOCK` telling the OSPM if a specification-compliant PM Timer is present. Currently, this flag is set regardless of the timer being enabled or disabled. To be specification-compliant, only set that flag, when the hardware PM Timer is enabled. This changes behaviour of all mainboards defaulting to USE_PM_ACPI_TIMER=n. Note: On platforms supporting uCode PM ACPI Timer emulation, this is required, too, because emulation does not support `TMR_STS`. Any OS or software checking this flag and thus relying on the overflow flag would not work (properly). Change-Id: Id2e5d69b5515c21e6ce922dab2cb88b494c65ebe Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-15soc/amd/common: move configure_espi_with_mb_hook implementationFelix Held
Move the actual implementation of configure_espi_with_mb_hook out of the header file and into the espi_util.c file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1106e69a52bf329a41e8e12fd09db846310b102a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15soc/amd: make configure_espi_with_mb_hook call conditionalFelix Held
If a system doesn't use eSPI or has the eSPI interface already configured in verstage on PSP, not calling configure_espi_with_mb_hook from fch_pre_init makes it a bit more obvious that the eSPI interface initialization will be skipped. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia77b83d56a5dab1bac6cfbbd92d33aa60a9e8b89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15soc/amd/common/include/espi: rename configure_espiFelix Held
Rename configure_espi to configure_espi_with_mb_hook to clarify that this function will call into the mb_set_up_early_espi function in the mainboard-specific code if it exists. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5d0f099288b0100242629c736dd69a8add977b5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15soc/amd/stoneyridge/acpi/sb_fch: use I2C[ABCD]_BASE_ADDRESS definesFelix Held
Now that the I2C[ABCD]_BASE_ADDRESS defines aren't macros that calculate the MMIO addresses any more, those defines can also be used in the ACPI code. TEST=Timeless build results in identical image for Google/Treeya. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7de2f83dc2f8061d8f1735caf10314bcddb2d3fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/58337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15soc/amd/stoneyridge/include/iomap: drop I2C_BUS_ADDRESS(x) macroFelix Held
The I2C_BUS_ADDRESS(x) macro isn't used to iterate over the I2C controller base addresses, so drop this and use the fixed MMIO address for the I2C[ABCD]_BASE_ADDRESS defines instead which also allows using those defines in the ACPI code. TEST=Timeless build results in identical image for Google/Treeya. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idd7484a0322dc5167cbb7fdcd9a2583f0dbed50e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15soc/amd/common/block/i2c: implement proper read_resourceFelix Held
Before this patch the reservation of the MMIO region of the I2C controllers was done in the LPC controller PCI device despite the I2C controllers already being devices in the devicetree. This patch implements this functionality as read_resources function of the I2C device instead. This will only reserve the memory when the I2C devices are enabled in devicetree which is a change from the previous behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I67c853df3be2f593ecfa113ae2f74e5df7cf74e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58307 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-15soc/intel/common/cse: Split CSE metadata into two CBFS filesFurquan Shaikh
This change splits CSE metadata structure (added to CBFS) into two separate CBFS files (me_rw.hash and me_rw.version). Since `struct cse_rw_metadata` is now used, it is dropped completely. This change is being made in order to prepare for the upcoming changes to stitch CSE binary at build time. Since the binary might not be available pre-built, it complicates the order of operations for the addition of CSE metadata structure and declaring hash and version as CPPFLAGS_common. Instead rules can be enabled for individual CBFS file targets for hash and version that ensure proper ordering as well. BUG=b:184892226 TEST=Ensured that update works correctly on brya by forcing version mismatch. In case of version match, no update is triggered. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I7c9bb165e6a64415affcd0b3331628092195fa0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-15soc/intel/cannonlake: Enable Energy/Performance Bias controlAngel Pons
Set POWER_CTL MSR bit 18 to enable Energy/Performance Bias control. TEST=Boot and verify EPB is enabled in coreboot log: cpu: energy policy set to 6 Change-Id: Ibd1db77b5b63cb6e2b0ad9d2f79caa2f3b576ead Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-15soc/qualcomm/sc7280: Enable compression of SHRMShelley Chen
The SHRM region needs to be 4 byte aligned, which make enabling compression slightly more complicated. We need to map it to cached memory before loading it and flushing to memory (in aligned chunks) then remapping the address space back to device memory before beginning execution of the SHRM region. Also, did some cleanup in this file based on comments in CB:49392. BUG=b:182963902 BRANCH=None TEST=Make sure we can still boot to kernel on herobrine Change-Id: Iaad8a8a02abe40bd01766d94ef0b61aac7671936 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-15soc/amd/cezanne,picasso/uart: implement read_resourceFelix Held
Implement the read_resources function for the UART devices so that the resource allocator knows about their fixed MMIO resources when enabled. TEST=UART still works on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4ffddee3f5f4281aca98ddfcefa639dfb7a38dae Reviewed-on: https://review.coreboot.org/c/coreboot/+/58306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: This CL did not handle Intel GPIO correctly. We need to add GPIO_EC_IN_RW into early_gpio_table for platforms using Intel SoC. Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57951 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-15soc/amd/common/block/lpc: simplify eSPI part of MakefileFelix Held
Since espi_util.c is also built in the case of verstage on PSP, we can just add it to all stages. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I65e07c356aac73c5de2d9ce5582434872a223c19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15soc/intel/alderlake: fix NULL pointer dereferenceSelma Bensaid
microcode_file could be NULL and passed to get_microcode_size, this was detected by klocwork scan. Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Change-Id: Ibb3d49ab18d8c26bbf5d6bf6bdf1bf91137f5736 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-15soc/intel/broadwell/pcie.c: Simplify AND-maskAngel Pons
There's no need to mask out bit 11, as it is unconditionally set. For some reason, this changes the resulting coreboot image. Also simplify another PCI operation with a redundant AND-mask. Change-Id: I5492acd5f9c61db83a07ce7c1f6b887768c3eadf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-14soc/intel/common/cse: Reorganize firmware update checks for CSE LiteFurquan Shaikh
`cse_fw_update()` is currently checking whether an update is required by comparing versions once and then again comparing versions later in `cse_is_downgrade_instance()` to determine if the update is an upgrade or downgrade. Additionally, if CSE RW partition is corrupt (determined based on `cse_is_rw_bp_sign_valid()`), `cse_is_downgrade_instance()` ends up using the corrupted version information to determine if it is a downgrade instance. This change reorganizes the firmware update checks to return different status values: 1. CSE_UPDATE_NOT_REQUIRED: No update required. Versions match. 2. CSE_UPDATE_UPGRADE: Update required and it is an upgrade. 3. CSE_UPDATE_DOWNGRADE: Update required and it is a downgrade (requires data clear). 4. CSE_UPDATE_CORRUPTED: `cse_is_rw_bp_sign_valid()` failed and hence requires data clear. 5. CSE_UPDATE_METADATA_ERROR: Unable to read CSE metadata from CBFS. This change also prepares the file for follow up changes which completely drop cse_rw_metadata structure. BUG=b:184892226 Change-Id: Iabecab8e373e65a11ba7fe1bfc125467571a0588 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58157 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-14soc/amd/common/acpi/upep: Add Low Power State Entry NotificationsKarthikeyan Ramasubramanian
Add support to handle S0ix entry and exit notifications by adding the corresponding _DSM functions. The function indices are chosen based on the Modern Standby BIOS Implementation Guide 56358 Rev. 1.04. Inside the notification functions perform any mainboard specific S0ix entry and exit actions. BUG=b:195748540 TEST=Build and boot to OS in Guybrush. Ensure that the notification functions are invoked on S0ix entry and exit. Perform suspend/resume cycles for multiple iterations. Change-Id: I3014551f6e281d466628559453a0141a3dd6abad Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58274 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-13src/soc/amd/cezanne: enable clock gatingJulian Schroeder
Enabling clock gating for CGPLL to lower power consumption in S3 and S0i3 states. See also: Cezanne PPR chapter 7, rev 3.03. BUG=b:185273565 TEST=iotools mmio_read32 0xfed80e2c and 0e30 show clk gating enabled and suspend_stress_test works. Change-Id: I33cbdeec62e49db90b680da37e5028df03a9c015 Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13soc/intel/common/tcss: Optimize USB-C DP flow and code structureDerek Huang
HPD event may not be ready when configuring TCSS mux for DP, check if any DP device is connected and wait for HPD ready before TCSS configuration. Remove unnecessary dependency on mainboard functions, use generic interface which provides USB-C mux operations. BUG=b:192947843 TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name for Brya. Build coreboot and update your Brya. Boot Brya with USB-C display connected, you should find `HPD ready after %lu ms` and `Port C%zd is configured to DP mode!` in coreboot log. Display should show screen in developer mode or recovery mode. Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: Ia7e6dd952d3183ecb76de6d4887ee573ef89bb50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-13soc/intel: drop P_BLK supportMichael Niewöhner
P_BLK is legacy and superseded by ACPI _CST. Also, the implementation for most platforms in soc/intel is broken. Thus, drop it. For APL the IO redirection is kept since it's used as replacement for the broken MWAIT instructions. Change-Id: I489aa7886dd9a4c1e6c12542bc2a1feba245ec36 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-13soc/amd/common/block/spi: Support fast speed overrideKarthikeyan Ramasubramanian
Add support to override SPI ROM fast speed based on board version. This will allow boards to start at lower speeds during bringup and then switch to higher speeds after assessing the signal integrity. Also implement a default no-op override. BUG=None TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ia8ff3b3bdb53fee142527ae63aa7785945909304 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13soc/amd/common: Add support to read and set SPI speeds from verstageKarthikeyan Ramasubramanian
Currently all SPI speed configurations are done through EFS at build time. There is a need to apply SPI speed overrides at run-time - eg. based on board version after assessing the signal integrity. This override configuration can be carried out by PSP verstage and bootblock. Export the APIs to set and read SPI speeds from both PSP verstage and bootblock. BUG=None TEST=Build and boot to OS in guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I281531e506b56173471b918c746f58d1ad97162c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13soc/amd/common/block/espi_util: Refactor eSPI SetupKarthikeyan Ramasubramanian
eSPI is setup in two different locations in bootblock depending on early port80 routing configuration. Also eSPI is setup in PSP, if verified boot starts before bootblock. Consolidate all the scenarios by initializating eSPI very early in fch_pre_init if verified boot starts after bootblock and eSPI is enabled. BUG=None TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13soc/amd/*: Enable ACPIMMIO decode first in fch_pre_initFelix Held
Since the GPIO mux/control MMIO regions are within the ACPIMMIO region, we need to call enable_acpimmio_decode_pm04 here first so that accessing the GPIO registers will work. BUG=None TEST=Build and boot to OS in Guybrush. Change-Id: I4bc076261c72cf999a5f2464b74cff6bf694d473 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13soc/mediatek/mt8192: add tracker dumpZhenguo Li
Tracker is a debugging tool, include AP/INFRA/PERI tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. Signed-off-by: Zhenguo Li <ot_zhenguo.li@mediatek.corp-partner.google.com> Change-Id: I82f8e6e5f8ccb7f8246cae45a01a3ddd5f2966f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58244 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-13soc/mediatek/mt8195: add tracker dumpZhenguo Li
Tracker is a debugging tool, include AP/INFRA/PERI tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. Signed-off-by: Zhenguo Li <ot_zhenguo.li@mediatek.corp-partner.google.com> Change-Id: If457f4a096cd63038bf6b40552aa3caaba33d5fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58243 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-13soc/amd/cezanne,soc/intel/common: rework CPPC table generationMichael Niewöhner
Make use of the newly introduced ACPI macros for CPPC table generation that currently exists of a bunch of confusing assignments of structs that only get partially filled. Test: dumped SSDT before and after do not differ. Change-Id: I844d191b1134b98e409240ede71e2751e51e2159 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lance Zhao Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-12soc/amd/common/block/include/psp_efs: use unsigned type for bitfieldFelix Held
For 1 bit long bit fields an unsigned type should be used. In this case uint32_t is used instead of a generic unsigned int for both consistency reasons with the rest of the file and to clarify that the bits will be packed into a 32 bit memory location. TEST=Resulting image of a timeless build for google/guybrush results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic630d1709174d90336746bc37da504437c12643c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-12soc/intel: replace dt option PmTimerDisabled by KconfigMichael Niewöhner
Replace the dt option `PmTimerDisabled` with use of the Kconfig option `USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer. A default value representing the prior devicetree value was added to the boards system76/{lemp10,galp5,darp7}, so this change will not alter behaviour. Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-12soc/intel/cannonlake: Lock PKG_CST_CONFIG_CONTROL MSRAngel Pons
Set PKG_CST_CONFIG_CONTROL MSR bit 15 to make bits 15:0 read-only. Change-Id: Ia196906d3c2636742ae90160a224354e8df7863a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-12soc/intel/*/cpu.c: Add missing space in commentAngel Pons
Add a space before the `*/` C-style comment ending. Change-Id: Ic8928286c8237808b9e380e4393078792589615d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-10-11soc/amd/cezanne/include/southbridge: add some more PM register definesFelix Held
Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib109efe679560604ff8209b4177611eb2aa9ebdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/58068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11soc/amd/common/include/lpc: add definitions for LPC LDRQ control bitsFelix Held
The definitions of bit 9 and 10 somehow got swapped between Picasso and Renoir/Cezanne, so put those in the Cezanne-specific header file. The reference code writes the same values to the raw bits in both, so we probably would still get away with putting this into the common header, but it's better to keep the defines consistent with the documentation in all cases. Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03 and cross-checked to be compatible with the Picasso PPR #55570 Rev 3.16. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3a033d63eeb06eed6783e4c3797ad8dea490db8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11soc/intel/tigerlake: Add ACPI addition for USB4/TBT latency optimizationJohn Zhao
The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency optimization. This change adds additional ACPI DSM function with both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME to the USB4/TBT topology. The OS is informed to reduce latency for upstream ports while connecting USB4/TBT devices. BUG=b:199757442 TEST=It was validated that the first connected device waits only 50ms instead of 100ms and all functions work on Voxel board. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I5a19118b75ed0a78b7436f2f90295c03928300d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11drivers/intel/dptf: Add support for PCH methodsSumeet Pawnikar
Add various methods support for pch device under dptf driver. This provides support of different control knobs for FIVR. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11soc/intel/dnv_ns: drop redundancies from soc_fill_fadtMichael Niewöhner
Drop overrides from `soc_fill_fadt` that do not differ from what common ACPI code already sets. Change-Id: I7a5f43f844b12ff0e9bc5c7426170383209c8e0a Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-09soc/intel/dnv_ns: add the Kconfig value for CPU_XTAL_HZMichael Niewöhner
Reference: Intel doc#558579 rev2.2 Change-Id: Iab5dca6eb42abc00bc7da33f640350e994f0bd02 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-07soc/intel/tigerlake: Hook up GMA ACPI brightness controlsTim Crawford
Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Tested by adding gfx register on system76/gaze16 and booting Windows. Display settings has a brightness setting, and can change the brightness level. Change-Id: Id8b14c0b4a7a681dc6cb95778c12a006a7e31373 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-07sc7280: Add SHRM firmware supportRavi Kumar Bokka
SHRM is a system hardware resource manager. It is used to manage run time DDRSS activities. DDRSS stands for DDR subsystem. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board by trying DDR clocks which through SHRM RSI command. Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-07soc/intel/cannonlake: Enable x86_64 supportPatrick Rudolph
Select HAVE_EXP_X86_64_SUPPORT. Tested on prodrive/hermes: Boots into Linux. Change-Id: I033ccd5dc793b637a2ac4271b450335464564885 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-07soc/intel/dnv_ns: correct size of GPE0 registers in FADTMichael Niewöhner
There are 4 GPE0 STS/EN register pairs, each 32 bit wide. However, SoC code sets a GPE0 block size of 4 byte length instead of 32 byte. The resulting value of `x_gpe0_blk.bit_with` is wrong, too (32 bit instead of 256 bit). Drop the overrides and let common ACPI code set the correct values based on `GPE0_REG_MAX`. Change-Id: I45ee0f6678784c292ee3ed3446bf3c0f2d53b633 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-07soc/intel/denverton_ns: Always enable SpeedStepDmitry Ponamorev
When "SpeedStep" is disabled on an Intel Atom C3538, the maximum CPU clock speed is always 800 MHz(min CPU clock). Оperating system cannot change the frequency. Avoid this issue allow "Intel Speed step" technology for processors that do not have "Intel Turbo Boost". Signed-off-by: Dmitry Ponamorev <dponamorev@gmail.com> Change-Id: Ia922e45c12e4239f1d59617193cdbde2a813e7d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: King Sumo <kingsumos@gmail.com>
2021-10-06sc7280: Enable UART driverRajesh Patil
Enable common Uart driver on sc7280 BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I015e21081391bfe85edf667685bf117401a9ec00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55963 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-06sc7280: Enable bootblock compressionRavi Kumar Bokka
This patch enables bootblock compression on SC7280. In my tests, that makes it boot roughly 10ms faster (which isn't much, but... might as well take it). Ref link: https://review.coreboot.org/c/coreboot/+/45855 BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Change-Id: I3564a7e531d769c8df16a1592ea98133d83b07b0 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-06soc/intel/alderlake: Skip setting D0I3 bit for HECI devicesSubrata Banik
This patch skips setting D0I3 bit for all HECI devices by FSP. BUG=b:200644229 TEST=FSP-S UPD dump suggested `DisableD0I3SettingForHeci` UPD is set to `1`. Change-Id: I86d61c49b8f187611efd495712ad901184665f31 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57815 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-06soc/intel/alderlake: Perform `heci_finalize` prior to booting to OSSubrata Banik
`heci_finalize` ensures to put all heci devices to D3 by setting the D0i3 bit prior to booting to the OS. BUG=b:200644229 TEST=Verified D0i3 bit is set for all HECI devices prior to booting to OS. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I86d5959646522f9a2169bf13ae04d88b8f685e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-06soc/intel/common: Helper function to check CSE device `devfn` statusSubrata Banik
This patch creates a helper function in cse common code block to check the status of any CSE `devfn`. Example: CSE, CSE_2, IDER, KT, CSE_3 and CSE_4. Currently cse common code is only able to read the device state of `PCH_DEVFN_CSE` CSE device alone. Additionally, print `slot` and 'func' number of CSE devices in case the device is either disable or hidden. BUG=b:200644229 TEST=Able to build and boot ADLRVP-P with this patch where the serial message listed the CSE devices that are disabled in the device tree as below: HECI: CSE device 16.01 is disabled HECI: CSE device 16.04 is disabled HECI: CSE device 16.05 is disabled Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I208b07e89e3aa9d682837380809fbff01ea225b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-06soc/intel/common/../cse: Allow D0i3 enable/disable for all CSE devicesSubrata Banik
This patch ensures to pass cse device function number as argument for `set_cse_device_state()` to allow coreboot to perform enable/disable of D0i3 bit for all CSE devices to put the CSE device to Idle state or Active state. BUG=b:200644229 TEST= Able to build and boot ADLRVP where `set_cse_device_state()` is able to put the CSE device toidle state or active state based on `devfn` as argument. Change-Id: Ibe819e690c47453eaee02e435525a25b576232b5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-05Revert "soc/amd/cezanne: Disable Co-op multitasking"Raul E Rangel
This reverts commit 5f80e7c764b9a1cb46beeaa490a4f60be04abcd4. The smm_do_relocation failure has been fixed. I also added CPU_INFO_V2 into this patch to satisfy the dependency. BUG=b:194391185, b:179699789 TEST=reboot stress test guybrush for 50 iterations. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I134c14748711a9c9865e0cc3e3185825f85248ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/57894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-05src/soc to src/superio: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-04soc/intel/adl: Drop SGPM, RGPM and EGPM methodsMeera Ravindranath
These methods can now be dropped as Dynamic GPIO PM is enabled. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0c7b67b5414d8c80775ab7678ce7b12181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04src/soc/intel/alderlake: Add PsysPmax settingRyan Lin
This patch feeds PsysPmax setting to FSP through UPD and adds a PsysPmax member in chip information so that we can set PsysPmax through devicetree. The PsysPmax needs to be set correctly mapping to maximum system power. Otherwise, system performance would be limited due to the default PsysPmax setting in FSP is only 21W. BUG=b:193864533, b:195615830 TEST=Set PsysPmax to an example value eg 145 in devicetree && put debug code in FSP to print the PsysPmax value before sending to Pcode, ensure the setting is correctly programmed. Change-Id: Ia07aa815f90739240f110cab984068237c02d896 Signed-off-by: Ryan Lin <ryan.lin@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-02soc/intel/common: round PM Timer emulation frequency multiplierMichael Niewöhner
Round the PM Timer emulation frequency multiplier to the closest value to increase precision. Test: compared hexdumps of CML binaries for the expected result: before: 0x262E8B51, after: 0x262E8B52 Change-Id: Iafd645c248fc17943ea4be558ed7d01a301ba809 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57943 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-02soc/mediatek: add debug dump for ltiming and clock_divRex-BC Chen
ltiming and clock_div are not support for MT8173, so we separate them to weak function: mtk_i2c_dump_more_info() Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I3228c6953be5fac18a76029702b878a34c7563f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58074 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-02soc/mediatek: Fix I2C failures by adjusting AC timing and bus speedDaolong Zhu
1. The original algorithm for I2C speed cannot always make the timing meet I2C specification so a new algorithm is introduced to calculate the timing parameters more correctly. 2. Some I2C buses should be initialized in a different speed while the original implementation was fixed at fast mode (400Khz). So the mtk_i2c_bus_init is now also taking an extra speed parameter. There is an equivalent change in kernel side: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/i2c/busses/i2c-mt65xx.c?h=v5.15-rc3&id=be5ce0e97cc7a5c0d2da45d617b7bc567c3d3fa1 BUG=b:189899864 TEST=Test on Tomato, boot pass and timing pass at 100/300/400/500/800/1000Khz. Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com> Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58053 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-02soc/intel/common/../cse: Avoid caching of CSE BARSubrata Banik
This patch ensures all attempts to read CSE BAR is performing PCI config space read and returning the BAR value rather than using cached value. This refactoring is useful to read BAR of all CSE devices rather than just HECI 1 alone. Additionally, change the return type of get_cse_bar() from `uintptr_t` to `void *` to avoid typecasting while calling read32/write32 functions. BUG=b:200644229 TEST=Able to build and boot ADLRVP where CSE is able to perform PCI enumeration and send the EOP message at post. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Id4ecc9006d6323b7c9d7a6af1afa5cfe63d933e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-02soc/intel/common/../cse: Append `_MS` with CSE_DELAY_BOOT_TO_RO macroSubrata Banik
CSE_DELAY_BOOT_TO_RO -> CSE_DELAY_BOOT_TO_RO_MS Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I4471e4553a081eaf5c8118e9600497a2b2437ac0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01soc/tigerlake: Make IO decode / enable register configurableSean Rhodes
This allows the one 32bit register to be configured in the devicetree in the same way that Skylake can be. i.e. register "lpc_ioe". Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib1a7f2707e565a5651ebe438320de9597f5742c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-10-01soc/intel/alderlake: add power limits for Alder Lake-M 282 SKUSumeet Pawnikar
There are two different types of 282 SKU available with TDP of 15W and 12W for Alder Lake-M SoC. This patch adds support for these TDP values for 282 SKU as per document 643782. BUG=None BRANCH=None TEST=Build FW and test on adlrvp board Change-Id: I553b2362b7bf811e6bf02fd9d68f78c2caeb7398 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
2021-10-01mb/google/brya: move MILLIWATTS_TO_WATTS macro in header fileSumeet Pawnikar
Move MILLIWATTS_TO_WATTS macro in power_limit header file so all other files can use the same macro. BUG=None BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Ic7ecba06b0e0a47546f7307cbfbc3ce0fc634bc3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01soc/intel/common: Add PMC IPC commands for FIVR controlSumeet Pawnikar
Add PMC IPC commands information for FIVR control functionality BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I9d08bb71f7ea5da7614c68fc0ce4edf9aef59baa Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01drivers/gic: Remove unnecessary codeJulius Werner
On AArch64 platforms, GIC initialization is generally the job of Trusted Firmware and shouldn't be necessary in coreboot. Only the ancient T210 platform (which was started before we had decided on using Trusted Firmware) calls this code, and even there they have a comment wondering "do we still need this?". I'm just gonna assume (without testing because that board is ancient and I'm lazy) that they don't, and that the TF GIC initialization[1] is sufficient here. Remove this obsolete driver. [1] https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3ff448/plat/nvidia/tegra/soc/t210/plat_setup.c#259 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3e9d90039dd27cb3a13f830ba21fc5cc7a70abe2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-30soc/intel/common/block/sgx: Fix typo in log messageAngel Pons
The value printed is the EPC (Enclave Page Cache) status, but the printk statement refers to it as `ECP status` instead. Fix the typo. Change-Id: Iba0a6013f2c537072dd7aa8266f2be3c5b0963ed Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58038 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-30soc/intel/alderlake: Add CPU ID 0x906a4Meera Ravindranath
TEST=Build and boot brya Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I4342c7343876eb40c2955f6f4dd99d6346852dc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
2021-09-30soc/intel/common/../cse: Append the time units to the HECI macro namesSubrata Banik
Append `_MS` for miliseconds and `_US` for microseconds to HECI timeout macros to improve the code readability. Change-Id: Ic7f18f07ecaabb3e43356f372d15d18be083464b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-30soc/intel/common/cse: Late sending EOP msg if !HECI_DISABLE_USING_SMMSubrata Banik
Pushing EOP msg post FSP notify helps to save ~30ms+ boot time across various warm reboots. This patch ensures late sending EOP msg when function disabling of CSE is no longer a requirement. BUG=b:200644229 TEST=Able to save ~30ms+ of boot time Without this code change EOP sending timestamp as below: 943:after sending EOP to ME 1,248,328(61,954)) With this code change EOP sending timestamp as below: 943:after sending EOP to ME 1,231,660 (2,754) Change-Id: I2b78a1c07803aacfb34dce9e94b2a05a2491aabc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-30soc/intel/alderlake: Perform `soc_finalize` at entry of BS_PAYLOAD_BOOTSubrata Banik
This patch ensures soc_finalize() is getting called at the entry of BS_PAYLOAD_BOOT boot state instead of BS_PAYLOAD_LOAD, BS_ON_EXIT. The purpose of this change is to accommodate more time to push out sending CSE EOP messages at post. BUG=b:200644229 TEST=coreboot serial log suggests soc_finalize() is getting called as part of the BS_PAYLOAD_BOOT entry. Finalizing chipset. apm_control: Finalizing SMM. APMC done. BS: BS_PAYLOAD_BOOT entry times (exec / console): 21 / 15 ms Change-Id: I8632eca057255d7f4a38b64fd17c1f3d84123051 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-09-30soc/intel/common/../cse: Perform D0I3 bit reset/set prior sending EOPSubrata Banik
Prior to coreboot sending EOP messages during post, it's important to ensure that CSE is not in Idle state. In case CSE is in Dev Idle state (which means D0I3 bit is set), reset this bit before sending EOP command. This patch ensures coreboot has provision to send CSE EOP messages even after the FSP Notify phase without any delays waiting for the device to respond or timeout. BUG=b:200644229 TEST=Able to send CSE EOP message even after FSP Notify phase. Attempting CSE EOP msg sending post FSP notify without this code change causes `timeout` issue as below: BS: BS_PAYLOAD_LOAD exit times (exec / console): 171 / 0 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post HECI: timed out reading answer! HECI: Failed to receive! HECI: receive Failed HECI: EOP send/receive fail ERROR: Failed to send EOP to CSE, 2 cse: CSE status registers: HFSTS1: 0x90000255, HFSTS2: 0xf10516 HFSTS3: 0x20 VB2:vb2api_fail() Need recovery, reason: 0x31 / 0xc Saving nvdata board_reset() called! full_reset() called! Attempting CSE EOP msg sending post FSP notify with this code change is `successful` as below: BS: BS_PAYLOAD_LOAD exit times (exec / console): 170 / 0 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post CSE: EOP requested action: continue boot CSE EOP successful, continuing boot Change-Id: Iae1bc52e94b08f97004424ea0c147d6da8aca6e2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-30soc/intel/common/../cse: Create APIs for CSE device state transitionSubrata Banik
This patch ensures APIs that are responsible for CSE device state transition between active to idle and vice-versa are available publically for other modules/boot stages to consume. BUG=b:200644229 TEST=Able to build and boot ADLRVP-P. Change-Id: Ia480877822d343f2b4c9bf87b246812186d49ea3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-29soc/intel/cannonlake: Guard acpi_fill_ssdt assignment with HAVE_ACPI_TABLESTim Wawrzynczak
Change-Id: I3677b4e545599d00a4ba16464836834febc2d1a5 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58024 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29soc/intel: Drop unnecessary `select REG_SCRIPT`Angel Pons
These platforms no longer use reg-script. Drop unneeded select. Change-Id: I8fc4dc29d25dffbf9ed1947d0ff013b2fae0faaf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-29soc/intel/common/block/smbus: Drop reg-script usageAngel Pons
Using reg-script just to read-modify-write some registers makes no sense. Replace reg-script usage with regular register operations. Change-Id: I87d1278360a231cbe5b5f825ad9a448e59e63ea2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-29soc/intel/skylake: Drop reg-script usageAngel Pons
Using reg-script just to read-modify-write some registers makes no sense. Replace reg-script usage with regular register operations. Change-Id: Ib3c83131c30fd02c579b910cfad6843eb28ba8f1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-29soc/intel/{cnl,jsl,tgl,ehl,adl}: rename PMC device init/enable callbacksMichael Niewöhner
The current names of the PMC init/enable callbacks are very confusing. Rename them. Change-Id: I69f54f3b4e1ea9a9b4fa5c8dd9c0d454d7cd1283 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-29soc/intel: Rename GNVS struct member to match ASLAngel Pons
Rename the `ecps` GNVS struct member to `epcs` to match the name in ASL. Change-Id: I1f6b97309eea75e7dbb4e5e664660df05ec0845e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-29soc/intel/alderlake: Add GFx Device ID 0x46c3Selma Bensaid
This CL adds support for new ADL-M graphics Device ID 0x46c3. TEST=boot to OS Change-Id: Ib55fb501f96fe9bcc328202511bbfe84a3122285 Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-29soc/intel/alderlake: Add ADLP 242 power configurationsTracy Wu
Add ADLP 242 sku power related settings, which follow the settings of ADLP 282 sku (both are 15w). BUG=b:201253904 TEST=Build and check fsp log to confirm the settings are set properly. Change-Id: I829dd690c22d167a507b1910106da06b275cec09 Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-29soc/intel/alderlake: Add support for power cycle and SLP signal durationTim Wawrzynczak
The UPDs for PM power cycle duration and SLP_* signal durations are all identical to Tiger Lake, so add similar support, but use enums instead of comments to represent the durations symbolically. BUG=b:184799383 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4a531f042658894bcbc6a76eff453c06e90d66b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57891 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29{sb,soc}/intel: Drop unused globalnvs.asl methodsAngel Pons
These methods are never used in the code. Drop them. Change-Id: If5568b494f821d2647ada5ae845bcd015708520e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-29{sb,soc}/intel: Drop PRMx from GNVSAngel Pons
These fields are never used in the code. Drop them. Change-Id: Icd07f2d704c19126bf6df4d740c21d5a1342061b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-29{sb,soc}/intel: Drop LCKF from GNVSAngel Pons
This field is never used in the code. Drop it. Change-Id: I88207ec369ab83823ef2f3fc40f68a0980ce9663 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-29soc/mediatek/mt8195: initialize DFDRex-BC Chen
DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values could be showed for debugging. BUG=b:192429713 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507c99b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57980 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-28soc/intel/baytrail: Always handle MRC as ELF fileAngel Pons
The current MRC binaries for Bay Trail are always ELF files. Always adjust the position in CBFS using the ELF header regardless of file names. Without adjusting the position, the system hangs right after calling into MRC. TEST: MRC position in CBFS does not change for bostentech/gbyt4. Change-Id: I74e1246a5fac3f3649be9842ff13c2fc70f72a20 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57989 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-27soc/qualcomm/sc7280: Enable QUP drivers to use lz4 compressionShelley Chen
BUG=b:182963902 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B Change-Id: I3ec557bdf2286c3f60902d5ac018b536fe99afa3 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57896 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-27soc/intel/baytrail: Drop invalid `VGA_BIOS_FILE` defaultAngel Pons
This file does not exist in the coreboot tree. One should place this file in the `site-local` subdirectory and specify the paths by means of `site-local/Kconfig`. Change-Id: I86ac2a6176947f12194bec6b63bedd7db79820a0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>