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Change-Id: I849dd406f5ccc733d4957eaf1c774745782f531a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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STAPM devicetree registers do not indicate the unit, which causes confusion.
More importantly, the time was assumed to be in seconds when it's actually
milliseconds. This caused early STAPM configurations to fail.
BUG=b:117590953
TEST=Build grunt
Change-Id: I2a7e3d43601992d1f7b02456913c763d940fe9ee
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29035
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Bounce buffers used to be used in those cases where the payload
might overlap coreboot.
Bounce buffers are a problem for rampayloads as they need malloc.
They are also an artifact of our x86 past before we had relocatable
ramstage; only x86, out of the 5 architectures we support, needs them;
currently they only seem to matter on the following chipsets:
src/northbridge/amd/amdfam10/Kconfig
src/northbridge/amd/lx/Kconfig
src/northbridge/via/vx900/Kconfig
src/soc/intel/fsp_baytrail/Kconfig
src/soc/intel/fsp_broadwell_de/Kconfig
The first three are obsolete or at least could be changed
to avoid the need to have bounce buffers.
The last two should change to no longer need them.
In any event they can be fixed or pegged to a release which supports
them.
For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the
value needed in 1999 for the 32-bit Linux kernel, the original ramstage)
to 0xe00000 (14 Mib) which will put the non-relocatable x86
ramstage out of the way of any reasonable payload until we can
get rid of it for good.
14 MiB was chosen after some discussion, but it does fit well:
o Fits in the 16 MiB cacheable range coreboot sets up by default
o Most small payloads are well under 14 MiB (even kernels!)
o Most large payloads get loaded at 16 MiB (especially kernels!)
With this change in place coreboot correctly still loads a bzImage payload.
Werner reports that the 0xe00000 setting works on his broadwell systems.
Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fixes builds of that binary in clean trees.
Change-Id: If5a995449a74c00da836fcf22bda44ebc8197518
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Remove assert() and instead use if statement to check if
comm->groups is NULL.
Found-by: klockwork
BUG=None
TEST=Boot to OS
Change-Id: I85a6bc700b52d04c61ca8f2baac62000f40cf2cb
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/28940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change sets PCIEXPWAK_DIS in PM1_EN register if WAKE# pin is not
enabled on the platform. This is required to prevent unnecessary wakes
if the WAKE# pin remains not connected on the platform. Function to
set PCIEXPWAK_DIS gets called in normal boot path (BS_PAYLOAD_LOAD) as
well as S3 resume path (BS_OS_RESUME).
BUG=b:117284700
TEST=Verified that no spurious wakes are observed on nocturne.
Change-Id: Iea93baffc9bb703c0ffedacafc6a9a9410c7ebfe
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Now only those UARTs that are enabled in devicetree.cb are initialized.
Tested on Opencellular Elgon.
Change-Id: I145c224148f0cc078bb1c76f588f603e73121a62
Signed-off-by: Jens Drenhaus <jens.drenhaus@9elements.com>
Reviewed-on: https://review.coreboot.org/28975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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AMD's SOC do not wait for I2C transactions to complete before executing
a reset. Because of this, it's possible for the reset to happen in the
middle of a transaction, resulting on a slave hang. There are 2 possible
solutions:
If the slave has a reset pin connected to a GPIO pin, it can be used to
reset the slave, else the only solution is to bang SCL 9 times. Create
code that makes it easy to implement SCL bang, using a devicetree
register to define which I2C SCL lines needs to be reset.
BUG=b:114479395
TEST=Build and boot grunt. Look at transactions on a scope.
Change-Id: I7f74b7e45c509044825355874753969f074e2382
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28574
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set up DRAM related PLLs.
And update post divider table to fulfill all freqency settings.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Ic197cef7d31f75ffe4e7d9e73c9cc544719943ab
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-on: https://review.coreboot.org/28667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
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This patch creates _PRT entires for each PCIE root port devices.
TEST=Able to see PCIE wake device in cat /proc/acpi/wake list
Change-Id: I183c89c92139e15e0bfc39620710dbdc6597b351
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch provides option for PCI IRQ mapping in both PIC and APIC mode.
TEST=Build and Boot on CNL RVP.
Change-Id: Ie26750ac9dc2ce940b0c116085c041de439075df
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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issue
This patch fixes below ACPI compilation issue:
Found 1 external control methods, reparsing with new information
Pass 1 parse of [DSDT]
ACPI Error: [EPCS] Namespace lookup failure, AE_ALREADY_EXISTS (20160318/dsfield-660)
ACPI Error: [EMNA] Namespace lookup failure, AE_ALREADY_EXISTS (20160318/dsfield-660)
ACPI Error: [ELNG] Namespace lookup failure, AE_ALREADY_EXISTS (20160318/dsfield-660)
Pass 2 parse of [DSDT]
ACPI Warning: NsLookup: Type mismatch on EPCS (Integer), searching for (RegionField) (20160318/nsaccess-664)
ACPI Warning: NsLookup: Type mismatch on EMNA (Integer), searching for (RegionField) (20160318/nsaccess-664)
ACPI Warning: NsLookup: Type mismatch on ELNG (Integer), searching for (RegionField) (20160318/nsaccess-664)
Parsing Deferred Opcodes (Methods/Buffers/Packages/Regions)
TEST=Able to build sgx.asl without any ASL error.
Change-Id: If4e7d4c66b6aab6c081fa272d8c2c9a1f0651ef7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch to fix KW issue due to msg, data and response pointers NULL
check fail.
Change-Id: I39324514079f240ba1683a04e579de85485299bf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Legacy PME are enabled by default in FSP-S UPD. This policy sets
PME Interrupt Enable (PIE) bit of RCTL register to trigger interrupt
generation when RSTS.PS state has changed (either due to 0->1 transition
or due to this bit being set with RSTS.PS already set). Due to this
interrupt generation, system wakes from sleep immediately it enters.
This patch overrides root port legacy pme upd policy from coreboot to
ensure no false SCI is triggerd when system is in S3/S0ix state.
BUG=b:113083354
BRANCH=none
TEST=Able to make S3 resume using wake on wifi connect/disconnect usecase
without any failure.
Change-Id: I779fac711eeeed65ea379fad1cc400052d8a00eb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch save and restore ITSS IPCx register before and after
FSP-S call.
Change-Id: Iea9356b4404d2fa49ea62ef7bc2c72f125054ff3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28792
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch save and restore ITSS IPCx register before and after
FSP-S call.
Change-Id: Ib731f27826d604c305dc52a8488fd6240b01148a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch selects Kconfig for Intel Core Platform in order to ensure
proper ITSS IPCx programming.
Change-Id: I81e75e17ceb23c364b78300c3950144be1580700
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch fixes KW issue due to pointer being NULL and will be dereferenced
Change-Id: Iedb59daf5f448e31c0097873a086e4d08cd4a979
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28948
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It exposes an interface that is as generic as possible, so payloads
and/or kernels can use it for their data.
Change-Id: I9553922f9dfa60b9d4b3576973ad4b84d3fe2fb5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/25182
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28934
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to make the macro name consistent for all PAD_CFG1_IOSSTATE_*
macros, this change uses lower case x for *RXD*. It helps avoid
confusion when using the macros.
Change-Id: I6b1ce259ed184bcf8224dff334fcf0a0289f1788
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28924
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change sets scan_bus operation for HDA to scan_static_bus to
allow enumeration of static devices under HDA.
BUG=b:112888584
TEST=Verified that devices added under HDA get enumerated on Nocturne.
Change-Id: I20759c2b702b2f107f0913e7ce92a82c6070ddc4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28807
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Config option SOC_INTEL_COMMON_BLOCK_HDA is currently used for
initialization of HDA codecs only. This prevents adding of any static
devices under the HDA device node. However, there can be boards which
want to add devices under HDA node (e.g. nocturne that wants to
provide DMIC properties to OS) without performing any codec
initialization using the HDA. This change:
1. Adds a new config option SOC_INTEL_COMMON_BLOCK_HDA_VERB that can
be set explicitly by the boards that want to perform codec
initialization.
2. Uses newly added config option is used to guard the initialization
functions for the codec. Rest of the device operations can still be
used by all the other boards without having to use HDA codec
initialization.
3. Selects the newly added option SOC_INTEL_COMMON_BLOCK_HDA_VERB in
kblrvp which is the only board enabling HDA codec initialization
using common block code.
4. Selects original config SOC_INTEL_COMMON_BLOCK_HDA for skylake SoC.
Above changes need to be bundled and pushed in as a single change in
order to avoid breaking existing users.
BUG=b:112888584
Change-Id: Ie6f39c13a801833b283120a2d4b6f6175688999c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This patch removes assert() and checks if the dev is NULL with "if"
condition only.
Found-by: klockwork
Change-Id: Icd2c8490c8bda14ecd752437d463a7110fe40aea
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/28888
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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TEST=Build Grunt
BUG=b:77602074
Change-Id: I24a46cc3e766ba7e9199723b042476064a698bf2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove AcpiMmio and PCI config registers that are not used.
TEST=build Grunt
BUG=b:77602074
Change-Id: I62f40e421eba41c4a49d85efc975096171cb72fa
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove the step of setting the SATA controller to S0 as the system is
entering S3. This had been duplicated from AMD's FchCarrizo.asl file,
but upon closer inspection, the conditions for this step to run cannot
be met. This does not affect Grunt's behavior, as the SATA controller
is disabled.
TEST=Suspend and resume Grunt
BUG=b:77602074
Change-Id: Ib269a5363d03c7048abd0c8a9a28df92a773790c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Move funtions callbacks used to override FSP upd values to
separate files. This serves as a base change for SoCs for which
FSP is still under development, and hence the FSP header files
are not available yet and in turn the UPDs cannot be referred.
These newer SoCs will implement empty callbacks. The code will
compile with basic header files which only include the architectural
FSP structures.
This allows plugging in these separate files for compilation in an
environment where FSP header files are available.
The fact is, FSP header files are not released externally until PRQ.
However the teams at intel and some partners have access to the development
version of these files. This code refactor helps to continue development
on the pre-PRQ silicons and submit related code to coreboot.org.
BUG=None
BRANCH=None
TEST=Build for cnlrvp
Change-Id: Iffadc57f6986e688aa1bbe4e5444d105386ad92e
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/28661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Increase bootblock size by 4KiB and reduce romstage by 4 KiB.
Change-Id: I604fd9c63a4cf6fb7b18249a6d73cd637e184a71
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I3f4123657a375211f802a7d484a15353f9a256e9
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/28795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
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Use BIOS_DEBUG consistently to log PM1 and PMxC0 status registers
on boot. print_num_status_bits() was already using BIOS_DEBUG.
TEST=Inspect console for Grunt
BUG=b:110788201
Change-Id: If7da8c7c86e90a661338903ad05cc41e11f507d2
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/28885
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Implement the function vboot_platform_prepare_reboot() which is normally
a weak function.
The SlpTyp field of the PM1 register is not reset to its default value
when the APU restarts. This change prevents a failing condition if
vboot decides to reset the system instead of allowing an S3 resume to
continue.
TEST=Resume Grunt when vboot attempts a reset, verify a fresh boot instead
BUG=b:117089826
Change-Id: I6e0e3e541bad89ca5b23d6ddb6e5c0df7f762f10
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28877
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id4f99e82bb97a260d654b49a2ba94fde207d318b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28847
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable the IOMMU in AGESA and copy the AGESA generated IVRS ACPI table.
BUG=b:116196614
TEST=Check dmesg for AMD-Vi messages.
Change-Id: I688d867c7bd4949a57b27c1b6a793c6a6e4a717a
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/28753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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This patch ensures I2C controllers are out of reset without any
assumptions.
BUG=b:116191230
BRANCH=none
TEST=Dump MMIO offset 0x204 to check if I2C host controller is NOT
at reset (by reading Bit 0-1 as 3)
Change-Id: I4b335a834333e01cfa2d802e4aad0735d0212dcc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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`HMRFPO` was spelled as `HMRPFO` twice.
Change-Id: Ibd04004ac5edcdeee49a6a69fcdd5c73603e92e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Make correct spelling for THERMAL_IRQ macro in irq.h file.
Change-Id: I83593822e2abbb07e60fc336b774199fea3b368f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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This patch unified line indentation.
Change-Id: Ife3396e36a0684490d9ed9b31b4c0a543a3e3d24
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Add methods, and call them, for transitioning EHCI and xHCI to D0 or
D3cold. Add device objects necessary for waking the system via USB.
In order for USB to wake the system, it must be in the D3cold state.
Then on resume, its firmware must be reloaded.
This code relies heavily on AMD's FchCarrizo.asl (delivered in NDA PI
package), and has been modified to fit the coreboot ASL names. In
addition, AMD's methodology is to generate a SW SMI for saving/restoring
certain settings. This has been ported into U3D0 and U3D3, as the
necessary registers are now publicly documented.
BUG=b:77602074
Change-Id: I83d0dce13411601691318cc67c99adf291ccf3bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28772
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a method to assist with setting the PwrGood Control register, which
will be useful for various devices.
BUG=b:77602074
Change-Id: Ief602c4bc42d27b3e236d24db815b990f3a2419c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add methods that can be used for preparing all controller hub devices
for sleep, and that will turn the devices back on.
BUG=b:77602074
Change-Id: I4b0c48e96aff23b4c31c9e89582b9fa80dba7bda
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28770
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Duplicate ASL from AMD's FchCarrizo.asl (available in NDA PI package)
that can put AOAC devices into D0 or D3cold. The argument numbers
coincide with the AOAC register offsets for the various devices.
SATA, USB, and SD require additional device configuration. Add a
placeholder and mark as todo.
BUG=b:77602074
Change-Id: I32426f744a5ebbad9e8d3f2f37c4d214ad6dd3d4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28769
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Define various AMD_SB_ACPI_MMIO_ADDR registers at 0xfed80000. Define
various PCI config space registers. These are duplicated from AMD's
FchCarrizo.asl file.
BUG=b:77602074
Change-Id: Ie7447fef682424b05fa912b60c7b80112c6202de
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28768
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Indicate the devices that are enabled. This is somewhat rudimentary, but
could be improved in a later patch (e.g. get settings from devicetree).
Calculate values that may be used for reinitializing the xHCI firmware.
Add the EHCI BAR's current base address to gnvs.
BUG=b:77602074
Change-Id: I8af69c030eb2353ad75beeb2bfd3bef24abff04c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28767
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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A later patch will rely on two USB settings from the BIOS. Add these
to the global_gnvs_t structure.
The first is a data that will be used to locate the xHCI firmware for
reloading after a resume. Although the existing calculations will be
somewhat simple, keeping this on the coreboot side will help in the
event multiple FWs are eventually in the build.
The second item is a usable EHCI base address that may be programmed
during S3 suspend and resume. At the time the PTS and WAK code runs,
the BAR will be clear.
BUG=b:77602074
Change-Id: I32205ac8a6908cca4a38dd68a7c7b591e76c06bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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A later patch will leverage AMD's ASL support for handling AOAC
devices. This will gather coreboot's device enables from a bitwise field,
where each bit corresponds to the register offset used to control
each devices.
Create an identical structure, and add it to the nvs ASL and global_nvs_t
structure.
BUG=b:77602074
Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Regarding the SDMs, IA32_MC0_STATUS register is at 0x401, and
IA32_MC0_CTL is at 0x400.
So replace MSR at (0x400+1) by IA32_MC0_STATUS and the one at
0x400 by IA32_MC0_CTL.
Change-Id: I3f53c80f39078bd0c47c25013657e1169fc6c4a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Change-Id: I07c95b9ea14d47da0497470487fa3f162f8012c8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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The globalnvs.asl file had become mixed with tabs and spaces to align
columns. Use all tabs to align the comments.
BUG=b:BUG=b:77602074
Change-Id: Ife4cf86372a8e24e78b38cca0254dd9fa00dd6b0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
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In preparation to remove AmdLib, remove reference to AmdLib.h in
soc/amd/stoneyridge/BiosCallOuts.
BUG=b:112525011
TEST=Buildgrunt.
Change-Id: If80eb64fb736ff26ab226a16b583c8b1c29831f4
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28741
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Charles Marslett <charles.marslett@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The function to fill out the FADT table exits early if the devicetree
config option to disable the legacy timer is set. This means it never
gets to the later check for s0ix config option and so the flag to
indicate that it supports low-power idle in S0 is not set.
Change-Id: Ia0416f21b6445f6feecb6f0301d48fdf2522b8a6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/28755
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SkipMpInit UPD had ben moved from Fsp SiliconInit UPD to Fsp MemoryInit
UPD, hence change the settings in coreboot side as well. The old options
in SiliconInit get deprecated, so leave the code as is will be
harmless. Make the changes limited to coffeelake itself.
Change-Id: If968de78117068668e4f0006c412442c50658ba9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28740
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In preparation to remove AmdLib, remove all references to AmdLib.h in folder
common/block/pi.
BUG=b:112525011
TEST=Buildgrunt.
Change-Id: I3530857b872d0cb5ed2e3f3a294cc50b45ff6969
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28737
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Charles Marslett <charles.marslett@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ACPI DSDT entry for integrated Gigabit LAN controller.
Change-Id: I15bf1d4065894531871380b3318f553b637f4a97
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28743
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some of the FSP silicon UPD entry can be updated base on device switch
in pci device tree, have both static config setting and device tree "on"
and "off" will be redundant.
BUG=N/A
TEST=Build and boot up fine with Whiskey Lake RVP platform.
Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27766
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As per internal discussion, there's no "ChromiumOS Authors" that's
meaningful outside the Chromium OS project, so change everything to the
contemporary "Google LLC."
While at it, also ensure consistency in the LLC variants (exactly one
trailing period).
"Google Inc" does not need to be touched, so leave them alone.
Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
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Change-Id: Idcd72c558e46637b1b99e9613963436fedd4a8b9
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28699
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These parameters are not used and not necessary in sdram.c, because the
DDR PLL is configured in clock.c.
Change-Id: I8060bd21e05765cedf7bdabc28052c32774f9ca1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28710
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This board doesn't support the newest RISC-V Privileged Architecture
spec (1.10), and it's based on an FPGA so it's a moving target.
Now that there's actual RISC-V silicon out there (from SiFive),
mb/lowrisc/nexys4ddr will only continue to bitrot.
Change-Id: I4e3e715106a1a94381a563dc4a56781c35883c2d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Use of device_t is deprecated.
Change-Id: Id82059898844fbe20665250062b67652d6cc1f9e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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Eliminate the references to PspBaseLib.c and PspBaseLib.h in
agesa_headers.h. Fix psp.c references to definitions in those files
by adding them to include/amdblocks/psp.h.
BUG=b:78514564
TEST=Build and boot grunt/ChromeOS and restore an image from the internet.
Change-Id: I2740ceb945736c6e413f7d0bd0c41a19e19c7d5a
Signed-off-by: Charles Marslett <charles.marslett@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27619
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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STAPM programming was created inside function OemCustomizeInitEarly().
It should be SOC specific, and called by agesawrapper just before the
call to OemCustomizeInitEarly().
BUG=b:116196626
TEST=build and boot grunt
Change-Id: I8a2e51abda11a9d60a9057b38f2a484e1c8c9047
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28705
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support to set eMMC tuning params from the device tree so that it
can be configured per board.
BUG=b:112718426,b:112690628
BRANCH=none
TEST=Build nocturne image and checked values passed in dev tree is set
by FSP.
Change-Id: Ic71934dce9a1c380a057e579ca3fda41983b9385
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/28274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Use of device_t is deprecated.
Change-Id: I9dde92314af8ef87a5acb550f0fb25b8ce875174
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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No support for SoC D-1 stepping is available.
According to Intel doc #332095-015 stepping C-0 has revision
id 0x21 and D-1 revision ID 0x35.
Also correct the RID_C_STEPPING_START value for C-0.
BUG=none
TEST=Built, Intel Cherry Hill Rev F.
Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/27471
Reviewed-by: Wim Vervoorn
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use of device_t is deprecated.
Change-Id: Ia50aa96901b979b947fd4d269b077814c06f60c6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28677
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use of device_t is deprecated.
Change-Id: Ifd1471a9cd76d2cea72262ed81b7071f31f7b375
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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Use of device_t is deprecated.
Change-Id: Ifdf3d1870500812a417eaa5e93fcc168629c094f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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This included the microcode for some CPUID's found in
soc/intel/skylake/bootblock/report_platform.c (others are likely pre-release
SKU's)
The amount of FIT entries needed is currently 7 so setting
CPU_INTEL_NUM_FIT_ENTRIES is set to a safe 10 will be able to fit them all.
Change-Id: I3ba504a07b2697fe55ff8f28a934f761ae05a4ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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According to cannon lake PCH BIOS specification document #570374
target port id for interrupt and timer subsystem(ITSS) is C4 instead of C2.
BUG=None
TEST=None
Change-Id: I9f8783c682d2c4c4a86e1c9cf4b9c27a18fdf494
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Kin Wai Ng <nelsonaquik@gmail.com>
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Remove const define for spd_smbus_address, the value can be updated
depends on platform configuration.
TEST=Build and Run on Whiskey Lake rvp platform.
Found-by: Converity Scan #1395725
Change-Id: Ib933ed872e9f85087bb3cd76a1f1e29cca75cd54
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28664
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When preparing transition of AGESA calls to romstage, I placed a comment
indicating the place to move a particular call. Now that the AGESA call
has been moved to romstage, the comment became obsolete.
BUG=b:116095766
TEST=none.
Change-Id: I2811657385ab088747e32d4c66b99fdd01e7315e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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FSP initializes the VT-d feature on Broadwell-DE and assigns an address
space to the MMIO range. coreboot's resource allocator needs to be aware
of this fixed resource as otherwise the address can be assigned to a
different PCI device. In this case addresses are overlapped and the VT-d
range is not accessible any more.
To deal with it the right way add a fixed MMIO resource to the resources
list if VT-d BAR is enabled.
TEST=Booted into Linux and checked coreboot log for resource assignment.
Change-Id: I626ac17420eadc0b49031e850f0f40b3b221a098
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/28672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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The DMAR table generation depends on the VT-d feature which is
implemented in its own PCI device located in PCI:00:05.0 for
Broadwell-DE. Add a new PCI driver for this device and move
DMAR table generation to this device driver.
Change-Id: I103257c73f5e745e996a441a2535b885270bc204
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/28671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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According to AMD, there exists an undocumented MSR which must be
written with the PSP's base address. Read the value from the PSP's
config space and sync each core's copy of the MSR to match.
BUG=b:76167350
TEST=boot Grunt and verify "rdrand: disabled" goes away from dmesg
Change-Id: I30027d3b0a6fbd540375e96001beb9c25bf3a678
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28608
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use of device_t has been abandoned in ramstage.
Change-Id: If2d643eafea854563f56a7f867b7b492b6d09a19
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28631
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use of device_t has been abandoned in ramstage.
Change-Id: Ifa54624664c06c606fb4e083bae98b4accc61be0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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|
Change-Id: I49526b6aafb516a668b7b5e983a0372e3d26a8fc
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Default STAPM percentage causes a lot of thermal throttling on grunt.
AMD experimented with 80%, it works for grunt. This is initial code to
provide easy change path for other grunt based platforms.
BUG=b:111608748
TEST=build and boot grunt.
Change-Id: I22863f6ed76152bf872fce3e275f8a7fd8077504
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add definition for PCH_GPIO_PIRQ_INVERT, which is needed
for google/buddy, a to-be-merged variant of google/auron.
Taken from Chromium commit 70ee99b [buddy: change trigger type of gpio53]
Change-Id: I21448160cee791710df51d06efa32cdfecf38c0f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/28611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I3eacba9c1c20bbfa270dd7a9afabe48ed9092bcc
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28622
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ram_resource is board specific and should be moved there.
Change-Id: I50bd9aaaae39422e565d8bf205a6365c59299df0
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Mainly update headers to build.
Added option PMC_GLOBAL_RESET_ENABLE_LOCK to remove
function configuring the global reset through PMC base.
On denverton the global reset lock is not in PMC base
but in the PCI registers so this code cannot be shared.
Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/25426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Evandro Luiz Hauenstein <kingsumos@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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After changing clock from 33.33Mhz to 1Ghz the UART divisor needs to be
recalculated. Return correct tlck frequency in uart_platform_refclk.
Change-Id: I2291e4198cf466a8334211c6c46bc3268fc979a9
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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Based on SiFive bootloader code
Change-Id: I71043ce9e458e25e64da28d53cd36b02d2e22acc
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28604
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Invoke clock_init in romstage for SiFive Unleashed.
Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: If6af6f679e24e56c79b995de0970d4e6f455e40a
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The RISC-V Privileged Architecture specification defines the Machine
Time Registers (mtime and mtimecmp) in section 3.1.15.
Makes it possible to use the generic udelay.
The timer is enabled using RISCV_USE_ARCH_TIMER for the lowrisc,
sifive and ucb soc.
Change-Id: I5139601226e6f89da69e302a10f2fb56b4b24f38
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27434
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add original files from SiFive bootloader.
Change-Id: I8beb75c070a6fac1700dd7644fc4fe9df226e716
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Add a __always_inline macro that wraps __attribute__((always_inline))
and replace current users with the macro, excluding files under
src/vendorcode.
Change-Id: Ic57e474c1d2ca7cc0405ac677869f78a28d3e529
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/28587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@google.com>
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Change-Id: Ifa6faffbaf353379f57e0f80c1c4ca2fc380f874
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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The documentation unfortunately doesn't match what SiFive uses in their FSBL.
Use the same values as in FSBL to make DDR RAM work.
Change-Id: I844cc41ed197333adeae495e71ea70b4a9603650
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28582
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The SiFive UART on the HiFive Unleashed uses the tlclk as input clock
which runs at coreclk / 2.
The input frequency is configured in the board code depending on the
current stage. (bootblock + romstage run at 33.33Mhz, ramstage at 1Ghz)
Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid
Inter Flash Descriptor to exist. It does *not* identify platforms or boards
that are capable of running in descriptor mode if it's valid.
Refine the help text to make this clear.
Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply
declare that IFD is supported by the platform. Select this value everywhere
instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to
y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected.
Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to
the mainboard directory.
Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Iba0669e08940e373aaf42cbba3a1ceffd68a4f52
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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Instead of gpio_num, gpio_address should be used as the address in
write32. This lets us also get rid of a few casts.
Commit c9ed3ee8d8 ("soc/amd/stoneyridge: Fix gpio_set function") fixed
one instance of this bug, but it was more widespread.
TEST=None
Change-Id: I0cf87aac2f1b87b6eac2b506515e48fe908c1f2b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add a duplicate ACPI_BERT symbol with a 'y' default setting and additional
help text.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I817111cbd3e81b93d8b02d0654ba68c8678b1bbe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Expand the BERT reserved region size setting to account for the
possibility of no TSEG configuration. This change is only for
completeness, as stoneyridge must always use TSEG.
Change-Id: I90753fa408cfac4de38aff08979c45349bb62a66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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