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2021-04-16soc/amd/cezanne: Add uart controllers to chipset.cbIvy Jian
Add uart controller to chipset.cb and leave it off by default. Turn uart0 on for console for mainboards. BUG=none TEST=builds and boot into OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Iaeb7fea4b92bd89331c7ae7c1c000f8d9961fe9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-16soc/intel/alderlake: Allow devicetree to fill UPD related to TCSS OCMaulik V Vaghela
We need to change OC pin for type C USB3 ports and it depends on the board design. Allowing it to be filled by devicetree will make it easier to change the mapping based on the board design BUG=b:184653645 BRANCH=None TEST=compilation works fine and value of UPD is getting reflected. Change-Id: I61faa661c12dced27c6cdd7005a61ae8de8621e1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-16soc/mediatek: Remove misleading memory logsYu-Ping Wu
When MRC cache region type is not found (for example, in recovery mode with !HAS_RECOVERY_MRC_CACHE), mrc_cache_stash_data() will return 0. Therefore, the platform code is not able to tell from the return value if the MRC cache data is actually written to flash or not. Since the MRC driver is already pretty verbose, ignore the return value and remove the misleading memory logs. BUG=none TEST=emerge-asurada coreboot BRANCH=asurada Change-Id: I6b411664ca91b9be2d4518a09e9734d26db02d6e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52361 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16soc/amd/cezanne: Select VBNV_CMOSRaul E Rangel
Needed so we can switch to normal mode. BUG=b:184126844 TEST=Boot guybrush in developer mode and switch to normal mode. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I26ad160a2372484e9753a727f2b454a31e3537a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-15soc/amd/common/block/gpio_banks: Use configure_scimap()Kyösti Mälkki
There is no need to stash the SCI trigger register configuration and apply it at the end. Remove this to make SCI and SMI programming more symmetrical and to use available configure_scimap function instead of implementing it again, but without the additional checks. Using this function also allows removing soc_route_sci. Change-Id: Ie23da79546858282910db65182a6315ade506279 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-15sc7280: Provide initial SoC supportRavi Kumar Bokka
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-04-15src/*acpi: create acpi table for x2apic modeWonkyu Kim
Create acpi table for x2apic nmi, apic_ids BUG=None BRANCH=None TEST=boot to OS and check apic mode cat /proc/cpuinfo | grep "apicid" Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I9399d30b686b55d86806f5db4110bf4a80fe459b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-14soc/amd/stoneyridge: use common pm_set_power_failure_state functionalityFelix Held
The functionality to restore the previous power state after power was lost that could previously be enabled by selecting MAINBOARD_POWER_RESTORE in the mainboard's Kconfig can now be achieved by selecting POWER_STATE_PREVIOUS_AFTER_FAILURE in the mainboard's Kconfig instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I49c4a44ca2c4fa937a823c4eddf1618739c15114 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14soc/amd/piasso/fch: use common pm_set_power_failure_state functionalityFelix Held
The functionality to restore the previous power state after power was lost that could previously be enabled by selecting MAINBOARD_POWER_RESTORE in the mainboard's Kconfig can now be achieved by selecting POWER_STATE_PREVIOUS_AFTER_FAILURE in the mainboard's Kconfig instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iab9578ebea89651dc2389bf6ca93ca3f3507eb47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14soc/amd/common/block/pm: rework pm_set_power_failure_stateFelix Held
Picasso and Stoneyridge didn't do a read-modify-write operation on the lower nibble of PM_RTC_SHADOW_REG, but just wrote the upper nibble as all zeros. Since the upper nibble might be uninitialized before the lower nibble gets written, do what Picasso and Stoneyridge did here instead of what the reference code does. Also add a comment why and how this register behaves a bit weird. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0bda2349e3ae84cba50b187cc773fd8a5b17f4e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14soc/amd/common/block/pm: remove POWER_STATE_DEFAULT_ON_AFTER_FAILUREFelix Held
Not selecting POWER_STATE_DEFAULT_ON_AFTER_FAILURE brings Cezanne that is currently the only SoC using this functionality in line with Picasso where the default is that the board remains in power off mode after power was lost and later restored. Boards can change this behavior by selecting POWER_STATE_OFF_AFTER_FAILURE, POWER_STATE_ON_AFTER_FAILURE or POWER_STATE_PREVIOUS_AFTER_FAILURE. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic96f40e3c9867cd821e58d752f58b763930f6d0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14soc/amd/common/block/pm: select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILUREFelix Held
Without this being selected, mainboards can't select MAINBOARD_POWER_STATE_PREVIOUS to use the power state restoration code path in pmlib.c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I753659fa753e03a66b6c6b2eb97e7ef20c71ca57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14Rename do_printk() to printk()Nico Huber
The indirection seems unnecessary. The macros throw features like `-Wmisleading-indentation` off, though. Default build for QEMU/Q35 is unchanged. Change-Id: Ie4eab935a367b5ad6b38225c4973d41d9f70ef10 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-14intel: mma: Use new CBFS APIJulius Werner
This patch changes the Intel MMA driver to use the new CBFS API. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Icc11d0c2a9ec1bd7a1d6af362f849dac16375433 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-04-14soc/mediatek: Include sdram_info in ddr_base_infoYu-Ping Wu
Sync dramc_param.h with private repo mtk-dramk (CL:*3751861). BUG=none TEST=emerge-asurada coreboot TEST=Hayato boots with fast calibration BRANCH=asurada Change-Id: I79541f66ce68a75147c22b83a456e6268ca1485e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-04-14soc/amd/picasso/fch: add missing amdblocks/gpio_banks.h headerFelix Held
The prototype of gpio_add_events() is provided by that header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia384c9297ac1e24bf0b1bcce048012a247406f39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52274 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14soc/amd/cezanne/fch: process ACPI PM/GPE and GPIO eventsFelix Held
BUG=b:184549804 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4ebbe9667d18a96b1a363d0353c612e214699d12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52273 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14soc/amd/cezanne: save chipset state to CBMEMMartin Roth
Guybrush complains that this is missing during the boot, so add it to cezanne. I verified that the registers in gpio.c are correct. BUG=b:184549804 TEST=Build and boot Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3de3764c99fe89b962db88065575463b365ddaf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14soc/amd/picasso/romstage: factor out chipset state saving functionalityFelix Held
Since Cezanne needs the exact same code, move it to the common directory and add a Kconfig option to add this functionality to the build. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I04c4295071a3df7afcb4dfd5435b11fb0bf6963f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-13dptf: Move platform-specific information to `struct dptf_platform_info`Tim Wawrzynczak
DPTF HIDs are different per-platform going forward, so refactor these into SoC-specific structures which the DPTF driver can query at runtime for platform-specific information. Change-Id: I6307f9d28f4274b851323ad69180ff4ae35053da Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-13soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoCYidi Lin
TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-11soc/amd/common/block/gpio: remove SoC type check in gpio_fill_wake_stateFelix Held
Verified that all accessed registers exist in all SoCs that use this code (Carrizo, Mullins, Stoneyridge, Picasso and Cezanne at the moment) and that the bit definitions match as well. Also at the time of writing this patch only Picasso calls gpio_fill_wake_state, so dropping the check won't change behavior. This also avoids having SoC specific code that doesn't get selected by Kconfig options in the common AMD SoC directory and also avoids having to add a check for SOC_AMD_CEZANNE to support this functionality on Cezanne in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If770780a67776daf81744db1b635ffd402653a47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52223 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10soc/amd/cezanne: Set Power state after power failureKarthikeyan Ramasubramanian
Configure the power state to return to when the power is re-applied after power failure. BUG=b:183739671 TEST=Build and Boot to OS in Majolica and Guybrush. By default when the power fails the device turns on after power is re-applied. When the POWER_ON_AFTER_POWER_FAILURE is disabled, the device remains off even after the power is re-applied. Change-Id: I21c5da08c82156d6239450ef6921771da74cbaa1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52049 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10soc/amd/common: Handle power resume after power failureKarthikeyan Ramasubramanian
Introduce a power management library to handle the power resume after power failure. Enable HAVE_POWER_STATE_AFTER_FAILURE config when this library is enabled. BUG=b:183739671 TEST=Build Guybrush and Majolica mainboard. Change-Id: Iea4ea57d747425fe6714d40ba6e60f2447febf28 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-10soc/amd/cezanne: Add GRXS and GTXS methodEric Lai
Add GRXS and GTXS support. Move the gpio method into common place. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I8ba377179d6976cf26ed0dc521d8e4eff051dc85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-10soc/intel/alderlake: Drop unreferenced `InternalGfx`Angel Pons
This option is not referenced anywhere. Drop it. Change-Id: Ie59de5399a9b1713109bf334d4ad1d7f7efb91f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52104 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10soc/intel/alderlake: Skip D3Cold for TBTSubrata Banik
Check TBT NVM FW Ready (INFR) bit to skip D3Cold for TBT when device is in disconnected state. Not adhering this recommendation is blocking the S0ix state transition. BUG=b:183670327 TEST=S0ix state transition occurs with TBT disconnected. Change-Id: Ib9b9ceee4393aeba37fdcb4e05d1b279a6ff72d2 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-09mb/ocp/deltalake: Override DDR frequency limit via VPD variableTim Chu
Use VPD variable "fsp_dimm_freq" to select DDR frequency limit. Tested=On OCP Delta Lake, DDR frequency limit can be changed via VPD. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I1232feae5090420d8fa42596b46f2d4dcaf9d635 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-04-09mb/google/asurada: select mmc storage configWenbin Mei
Select mmc storage config for asurada. Build MTK host mmc driver. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: Iac656d57c2b834d1ce393fd991275b897e597b4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-09soc/mediatek: add new driver 'msdc' for eMMCWenbin Mei
Add MTK host mmc driver support. MTK host controller supports eMMC5.1 spec. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-08soc/amd: remove special GPIO_2 override soc_gpio_hookKyösti Mälkki
This override was added to have the SCI mapping configured if GPIO was used as WAKE_L pin. This however didn't set up the SCI level and trigger information, so it likely never worked as intended. Change-Id: I44661f05c8f517ece88714c625603579731d174b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-08soc/mediatek: dsi: fine tune the delta time for EoTpJitao Shi
We seperate the EoTp packet extra data. So need to reduce the delta. BUG=b:173603645 BRANCH=kukui TEST=Display is normal on Kukui Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I0666068cfb04b78eb706278814163f050da32b9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-04-08soc/intel/dnv_ns: hook up new gpio device operationsMichael Niewöhner
This change hooks up the new gpio operations in DNV-NS. Change-Id: I2179e641153da7230467c5766e4ded58fdb90292 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48618 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08soc/qualcomm: move code to commonRavi Kumar Bokka
This commit includes makefile cleanup to exclude common source file compilation in each stage by using all-y flag. BUG=b:182963902 TEST=trogdor validated on limozeen Change-Id: I48464567974a0729c1c6b6157bcce4fac39a8b38 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-04-08soc/amd/common: Add PM_ESPI_INTR_CTRLRaul E Rangel
This register is used for masking/unmasking eSPI IRQs. BUG=none TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia209539b2e0ce390e227757b16c2969b9124a845 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52142 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08soc/intel/{cannonlake,icelake}: Drop unhooked `SendVrMbxCmd`Angel Pons
This option's value is not used anywhere. Remove it. Change-Id: I0f30cddd30d459f48b51f377b111bbc04709c5f8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-08soc/intel/skylake: Drop unnecessary `ignore_vtd` optionAngel Pons
It is zero for all mainboards. If one really wanted to ignore VT-d support, a user-visible Kconfig option would be a better approach. Change-Id: I320c10317f3fabee5443c16ebdf1ffd0e24193b8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-04-08soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPDAngel Pons
Commit 0591348833f730a42e74039d8e2d957ec94a39d5 introduced this Kconfig option inside soc/intel/common scope. However, it was only hooked up in commit d74cd60b8159c3928dba318e6387f200ff3bb0e7 for Alder Lake, and in commit 99157c1f4a80556462ca22a4ade87b2c8d09e674 for Tiger Lake. Hook up the `SOC_INTEL_DISABLE_IGD` Kconfig option to all other platforms which have the `InternalGfx` UPD. Change-Id: Icd1379a835b445a6d4b028ebde5a3e355ee5b67b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52100 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-07soc/amd/picasso/acpi: fix domain argument of acpigen_write_CSD_packageFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I50e88ac946b9d8797571f9e3d4b325db760e423f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51932 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-07soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSPMatt Papageorge
This patch adds the functionality to write the DXIO and DDI descriptors to the UPD data structure to the SoC code and adds the mainboard_get_dxio_ddi_descriptors function to each mainboard using the Cezanne SoC that gets called to get the descriptors from the board code. Change-Id: I1cb36addcf0202cd56ce99e610a13d6d230bc981 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07vc/amd/fsp/cezanne: update UPD headersMatt Papageorge
The UPD header files get generated as part of the FSP build process. For the initial Cezanne development we took the Picasso UPD data structures as a starting point. This patch replaces it with the first version of the Cezanne-specific UPD data structures that is present in version 12 of the internal work-in-progress FSP binary drops. The serial_port_stride UPD-M field is removed, since the information is already given by serial_port_use_mmio. The stride is 4 bytes for the MMIO UART case and 1 byte for the legacy I/O case. BUG=b:182524631 TEST=NVMe works on google/guybrush when the rest of the patch train is applied as well. Change-Id: Idca235029bf2e68d403230d55308820cab61a6c0 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-06intel/tigerlake: Add Acoustic featuresShaunak Saha
On VCCin there was an oscillation which occurred just as the kernel started (kernel starting... message). On some devices, this behavior seems even worse. In previous platforms VCCin toggled for a few ms and then was stable. For volteer, this happens at the same point in time for around 40ms. However, it starts oscillating again later in the boot sequence. Once at the root shell, it seems to oscillate indefinitely at around 100-200Hz (very variable though). To fix this we need to control the deep C-state voltage slew rate.We have options for controlling the deep C-state voltage slew rate through FSP UPDs. This patch expose the following FSP UPD interface into coreboot: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRate We are setting SlowSlewRate for all volteer boards to 2 which is Fast/8. TGL has a single VR domain(Vccin). Hence, the chip config is updated to allow mainboards to set a single value instead of an array and FSP UPDs are accordingly set. BUG=b:153015585 BRANCH=firmware-volteer-13672.B TEST= Measure the change in noise level by changing the UPD values. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-06soc/intel/common: Prevent SMI storm when setting SPI WPD bitAngel Pons
From Skylake/Sunrise Point onwards, there are two BIOS_CNTL registers: one on the LPC/eSPI PCI device, and another on the SPI PCI device. When the WPD bit changes from 0 to 1 and the LE bit is set, the PCH raises a TCO SMI with the BIOSWR_STS bit set. However, the BIOSWR_STS bit is not set when the TCO SMI comes from the SPI or eSPI controller instead, but a status bit in the BIOS_CNTL register gets set. If the SMI cause is not handled, another SMI will happen immediately after returning from the SMI handler, which results in a deadlock. Prevent deadlocks by clearing the SPI synchronous SMI status bit in the SMI handler. When SPI raises a synchronous SMI, the TCO_STS bit in the SMI_STS register is continously set until the SPI synchronous SMI status bit is cleared. To not risk missing any other TCO SMIs, do not clear the TCO_STS bit again in the same SMI handler invocation. If the TCO_STS bit remains set when returning from SMM, another SMI immediately happens and clears the TCO_STS bit, handling any pending events. SPI can also generate asynchronous SMIs when the WPD bit is cleared and one attempts to write to flash using SPI hardware sequencing. This patch does not account for SPI asynchronous SMIs, because they are disabled by default and cannot be enabled once the BIOS Interface Lock-Down bit in the BIOS_CNTL register has been set, which coreboot already does. These asynchronous SMIs set the SPI_STS bit of the SMI_STS register. Clearing the SPI asynchronous SMI source should be done inside the SPI_STS SMI handler, which is currently not implemented. All of this goes out of the scope of this patch, and is currently not necessary anyway. This patch does not handle eSPI because I cannot test it, and knowing if a board uses LPC or eSPI from common code is currently not possible, and this is beyond the scope of what this commit tries to achieve (fix SPI). Tested on HP 280 G2, no longer deadlocks when SMM BIOS write protection is on. Write protection will be enforced in a follow-up. Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50754 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake MMaulik V Vaghela
Added new LPC and IGD device IDs for Alderlake M. Also, added entry for CPUID_ALDERLAKE_M_A0 in report_platform.c TEST=Check if platform information print is coming properly in coreboot Change-Id: If33c43da8cbd786261b00742e342f0f01622c607 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50138 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06soc/intel/alderlake: Update variable SD3C to only track enabled devicesJohn Zhao
Each TCSS DMA is grouped together with two PCIe RPs in terms of PM flow. This change ensures that SD3C is updated for the TCSS DMA devices corresponding to the TBT RP ports. If TBT port is 0 or 1, SD3C for DMA0 is updated, else for DMA1. BUG=None TEST=Built Alderlake image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ia3462dfbb287a374960a57bb4c3541db2a435611 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51965 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06soc/intel/alderlake: Remove TCSS DMA _DSM methodJohn Zhao
The kernel does not need TCSS DMA's _DSM method. This change simply removes this method. BUG=None TEST=Built Alderlake image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I313f9c8913bb8cf54581c5460ac3fb1597291ad5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd/cezanne: Add soc/msr.hRaul E Rangel
This is a copy of picasso. BUG=b:184151560 TEST=Compared with the cezanne PPR. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia4bc40daa971c126c2596837155312d411b91a06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-05soc/amd/common: Add some ESPI register definitionsMartin Roth
Use definitions instead of magic numbers clean up some whitespace while I'm here. BUG=b:183207262 TEST=Build Change-Id: Ieae53b12e5303641fb3f180c47468aaa6906e9af Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-05soc/amd: Make espi_clear_decodes privateRaul E Rangel
espi_setup already clears most of the controller registers. So this change consolidates the clear logic into one spot. This shouldn't result in a behavior change on Picasso. Picasso already has the eSPI decodes clear on boot, so this change is a nop. BUG=b:183524609 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd: Make espi_configure_decodes privateRaul E Rangel
This is only ever called after espi_setup. 55861 - AMD System Peripheral Bus Overview also says that io ranges should be configured before enabling the BUS_MASTER bit. BUG=b:183524609 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd/common/espi: Clear DNCMD_COMPLETE on completionRaul E Rangel
Tidy up the interrupt status. This will leave SLAVE0_INT_STS = 0. BUG=b:183524609 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I950cfb81521e35758c120a482670cfdb924201d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52056 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05soc/amd/common/espi: Reset eSPI registers to known stateRaul E Rangel
This sets the eSPI registers to the reset values specified in the PPR. On Cezanne, the PSP modifies these registers such that the eSPI peripheral cannot send DEFER packets. This causes random bus errors. These reset values are identical to what is currently used on Zork. I didn't clear out ESPI_DECODE because it's currently being done by cb:51749. BUG=b:183524609 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd/common/espi: Add missing eSPI register definitionsRaul E Rangel
These are defined in the public Picasso PPR - 55570-B1 Rev 3.15. BUG=b:183524609 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7e601f767327e0a24a086146623af039388b2e7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52057 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05device/dram/ddr3: Rename DDR3 SPD memory typesAngel Pons
To avoid name clashes with definitions for other DRAM generations, rename the enum type and values to contain `ddr3` or `DDR3`. Change-Id: If3710149ba94b94ed14f03e32f5e1533b4bc25c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51896 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05device/dram/ddr3: Get rid of useless typedefsAngel Pons
These typedefs are not necessary. Remove them, and rename some elements to avoid any confusion with other DRAM generations, such as DDR4. Change-Id: Ibe40f33372358262c540e371f7866b06a4ac842a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51895 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05soc/amd/common/espi: Add ESPI_ prefix to SLAVE0_INT_ENRaul E Rangel
This matches the other register definitions. BUG=b:183524609 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0ed92add633f294f92c6a0dde32851d01b10db3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd/cezanne: Clear eSPI ranges before configuring eSPIMartin Roth
The Cezanne PSP configures the eSPI with the assumption that it's a majolica, setting up both the serial port and the majolica EC IO decode ranges. Since guybrush is NOT a majolica, this doesn't work very well there. Clearing the decode ranges allows the guybrush platform to set the decode ranges needed for its EC. BUG=b:183524609 TEST=Set up eSPI on Guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I77cfb948cb9ae6d1cf001bd9e66cede8d93f50b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd/common: Add func to clear eSPI IO & memory decode rangesMartin Roth
Previously, the eSPI code would only add to existing decode ranges, and there wasn't any way to clear ranges. This clears all the ranges so the eSPI configuration can start fresh. BUG=b:183207262, b:183974365 TEST=Verify on Guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ic4e67c40d34915505bdd5b431a064d2c7b6bbc70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-04soc/ti/am335x/mmc.c: Fix memset length argumentAngel Pons
The sizeof() operator was being applied to a pointer-to-struct type. Correct this, so that the entire struct space gets cleared. Change-Id: Ieab3aaa2d07a928f27004b94132377d5dae935c0 Found-by: Coverity CID 1451732 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52054 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Sam Lewis <sam.vr.lewis@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-02soc/amd/cezanne: Add support to perform early EC syncKarthikeyan Ramasubramanian
Ideally we would like to perform EC Software Sync in payload. But with the hardware requirement (EC_IN_RW) and firmware requirement (TPM command to get EC execution environment) not met yet, adding the support to perform early EC Software sync. With EFS2 enabled, this will also help cr50 to set the boot mode as NORMAL instead of NO_BOOT. BUG=None TEST=Build and Boot to OS in Guybrush. Ensure that the EC software sync is successfully complete. CBFS: Found 'ecrw.hash' @0x50400 size 0x20 in mcache @0x020171ec VB2:check_ec_hash() Hexp RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6 VB2:check_ec_hash() Hmir: 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6 <snip> VB2:check_ec_hash() Heff RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6 VB2:sync_ec() select_rw=RW(active) Change-Id: I820e651c6b22a833fef6f17a4ceb5a8cfb6f1616 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-01soc/amd/cezanne: Enable GENERIC_GPIO_LIBRaul E Rangel
Needed so we write the correct resource into the ACPI tables. BUG=b:183737011 TEST=Boot OS and see GPIO devices working Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2ba4349e0ed500912db40aa6ef9b649046f4358f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51961 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-01soc/amd/cezanne: Add device tree support for I2CRaul E Rangel
This allows the cr50 on guybrush to show up in ACPI. BUG=b:183737011 TEST=Boot OS and see I2C devices initialized Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifb5679b7bbefbf753217981874bb1bdaef35f6db Reviewed-on: https://review.coreboot.org/c/coreboot/+/51958 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-31soc/amd/common/block/graphics: Don't add VBIOS to cbmem when using GOPRaul E Rangel
pci_rom_ssdt reloads the oprom from cbfs. It then places it into cbmem and writes the offsets as the ROM ACPI node. The GOP driver modifies the VBIOS so we don't want to reread from cbfs. When using GOP we also pass the offsets with the VFCT table. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iaf53e750564f1f0e115cd354790da62e672d74b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-31soc/amd/picasso/acpi: pass correct enum to acpigen_write_CSD_packageFelix Held
The coordtype parameter of acpigen_write_CSD_package expects a CSD_coord enum value, but HW_ALL that got passed as parameter is a PSD_coord enum value, so replace that with the correct CSD_HW_ALL enum value. TEST=Timeless build results in identical binary for Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Found-by: Paul Menzel <pmenzel@molgen.mpg.de> Change-Id: I90b19345b8dc6d386b6acfa81c6c072dcd6981ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/51931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-30soc/amd/cezanne: Comment the AOAC register accessKarthikeyan Ramasubramanian
Causing the AOAC register access as part of system suspend (S3) causes the suspend procedure to be stuck. Comment it for now to unblock entering S3 and collecting the power numbers. BUG=b:181766974 TEST=Build and boot to OS in Majolica. Enter S3 through "echo mem > /sys/power/state". Change-Id: Ie93bbe393b209b784b9a2257f3916b29d84b25d1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51926 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-30soc/intel/alderlake: Enable logging of wake sources for S0ixSugnan Prabhu S
This change adds elog.c and xhci.c to smm-y for alderlake platforms to enable the logging of wake sources in eventlog for S0ix. BUG=b:183684923 TEST=Verified on Brya that entry/exit for S0ix are logged in eventlogs. 295 | 2021-03-29 10:31:48 | S0ix Enter 296 | 2021-03-29 10:31:58 | S0ix Exit 297 | 2021-03-29 10:31:58 | Wake Source | RTC Alarm | 0 298 | 2021-03-29 10:32:30 | S0ix Enter 299 | 2021-03-29 10:32:55 | S0ix Exit 300 | 2021-03-29 10:32:55 | Wake Source | Power Button | 0 301 | 2021-03-29 10:32:55 | EC Event | Power Button 305 | 2021-03-29 10:43:13 | S0ix Enter 306 | 2021-03-29 10:43:14 | S0ix Exit 307 | 2021-03-29 10:43:14 | Wake Source | PME - XHCI | 0 308 | 2021-03-29 10:43:14 | Wake Source | PME - XHCI | 0 309 | 2021-03-29 10:43:14 | Wake Source | PME - XHCI (USB 2.0 port) | 8 310 | 2021-03-29 10:43:14 | Wake Source | GPE # | 109 Change-Id: Icc836caa797d3bc4e782c6a51492de23e7b49b71 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51839 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-30soc/intel/xeon_sp: Prepare for CBnT BPM generationArthur Heymans
To generate a working BPM, boot policy manifest for Intel CBnT the tool that generates it, requires ACPI base and PCH PWRM base as input. Therefore make it a Kconfig symbol, that can be used in Makefile.inc. Change-Id: I6f1f9b53e34114682bd3258753f2d5aada9a530d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51805 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-30soc/ti/am335x: Map useable RAMSam Lewis
Maps the useable RAM so that it can be used for booting a payload. TEST: Booted a simple ELF payload (that just flashes LEDs) on the Beaglebone Black. Change-Id: I7f657c97e4753071c90ba8ca800a96108807e6b9 Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44388 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-30soc/ti/am335x: Add SDRAM initialization driverSam Lewis
Adds code taken and (barely) adapted from U-Boot (release 2020.04, commit 36fec02b1f90b92cf51ec531564f9284eae27ab4) for SDRAM initialization. This should in theory work for other configurations than the Beaglebone Black's DRAM configuration, but hasn't been tested. Change-Id: Ib1bc2fa606f7010c8c789aa7a5c37cd41bc484b9 Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44386 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-30mb/ti/beaglebone: Load romstage/ramstage from SDSam Lewis
Adds a "sd_media" boot_device to allow booting from the SD card. This assumes that the generated "MLO" file is placed at a 128KB offset from the start of the SD card, to allow for the MBR etc. to be at the start of the SD card. Placing the MLO file here allows the AM335x boot ROM to load and execute the bootblock stage as well, as 128KB is one of the offsets the boot ROM checks when looking for the next stage to execute. As part of this, a FMD for the Beaglebone has also been defined. It's sized at 32M somewhat arbitrarily, as SD cards could allow for much bigger payloads. TEST: Beaglebone boots from bootblock into romstage. Romstage to ramstage still doesn't work as it needs RAM initialization first. Change-Id: I5f6901217fb974808e84aeb679af2f47eeae30fd Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44385 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-30soc/ti/am335x: Add MMC/SD driverSam Lewis
Adds a driver for the am335x MMC peripheral. This has only been tested with SD cards and probably needs some modification to use eMMC or MMC cards. It's also currently a little slow as it only supports reading a block at a time. Change-Id: I5c2b250782cddca17aa46cc8222b9aebef505fb2 Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-29soc/amd: smbus: Use correct type for uintptr_tPaul Menzel
Fix the format warning below by using `PRIxPTR`, which is defined as unsigned long. src/soc/amd/common/block/smbus/smbus.c:33:56: error: format specifies type 'size_t' (aka 'unsigned int') but the argument has type 'uintptr_t' (aka 'unsigned long') [-Werror,-Wformat] printk(BIOS_ERR, "Invalid SMBus or ASF base %#zx\n", mmio); ~~~~ ^~~~ %#lx src/include/console/console.h:60:61: note: expanded from macro 'printk' #define printk(LEVEL, fmt, args...) do_printk(LEVEL, fmt, ##args) ~~~ ^~~~ 1 error generated. Change-Id: I727c490d3097dcf36cdbcd4db2852cd49d11785f Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-29soc/amd/cezanne: factor out UPD-M configuration from romstageFelix Held
Move the parts of romstage.c that populate the UPD-M data structure to the newly created fsp_m_params.c file. Since platform_fsp_memory_init_params_cb gets called from the FSP driver and not directly from car_stage_entry the two code parts in romstage.c weren't directly interacting. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1f7f5879ac318372042ff703ebbe584ce1c32c91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-29soc/amd/picasso: factor out UPD-M configuration from romstageFelix Held
Move the parts of romstage.c that populate the UPD-M data structure to the newly created fsp_m_params.c file. Since platform_fsp_memory_init_params_cb gets called from the FSP driver and not directly from car_stage_entry the two code parts in romstage.c weren't directly interacting. Since soc/romstage.h only contains the mainboard_updm_update function prototype, rename it to soc/fsp.h. This patch also removes a few unused includes. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I52c21f13520dbdfab37587d17b3a8a3b1a780f36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-29soc/amd/cezanne,picasso: rename fsp_params.c to fsp_s_params.cFelix Held
This file populates the UPD-S data structure that gets passed to the FSP-S, so add that s part to make it a bit clearer which FSP parameters it'll set up. This is also a preparation to add a fsp_m_params.c file in the following patches. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I53786df0909055e66eac675b5580909b7960944f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-29soc/amd: add DISABLE_KEYBOARD_RESET_PIN optionFelix Held
The KBRST_L pin will cause a reset when driven or pulled low even when the GPIO mux is set to GPIO and not native function. So when you want to use that pin as general purpose output the keyboard reset input functionality needs to be disabled by selecting this option in the board's Kconfig file to avoid causing a reset by writing a 0 to the output level bit when it's configured as an output. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Furquan Shaikh <furquan@google.com> Change-Id: I517ad551db9321f26afdba15d97ddb61be1f7d51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51757 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-29soc/amd/cezanne: Implement PROVIDES_ROM_SHARINGRaul E Rangel
BUG=none TEST=Build guybrush and verified with the PPR that the register and bits are still the same Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0619f84cf82cbb90ded9dfd58afa6acc9520fb8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-29soc/amd/common/block/acpimmio/mmio_util: add fch_disable_kb_rstFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kangheui Won <khwon@chromium.org> Change-Id: Ie65e39ffb8c353415f5b68e1e0f378d18eeb7498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51784 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-29soc/amd: move PM_RST_CTRL1 register definition to common acpimmio headerFelix Held
TEST=Verified that this register and the defined bits exist in Cezanne, Picasso, Stoneyridge, Bolton and SB800. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I32d1d577b05edab006981516a5aefd822e7b984a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-29soc/amd/*/gpio: include types.h instead of stdint.h to have size_tFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7a747d4c28e6d449c054ce83966767e13b51a939 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-28soc/intel/alderlake: add processor power limits control supportSumeet R Pawnikar
Add processor power limits control support to configure values for alderlake soc based platforms. BRANCH=None BUG=None TEST=Build and test on alderlake rvp board Change-Id: I9dc37c7a43e6bd6f1ff5e8a97e22a0c7ac421802 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-28soc/intel/common/gpio: Add function to get GPIO index in groupTim Wawrzynczak
The gpio_get_index_in_group function returns the index of the GPIO within its own group Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7f6b312bd1d0388ef799cd127c88b17bad6a3886 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-28soc/intel/common/systemagent: Add macros to access REGBAR spaceTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I97203aca377d4dd77e03b2c83fdd20a2874cc1c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51755 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28soc/intel/tigerlake: Fix REG_BASE_SIZETim Wawrzynczak
REG_BASE_SIZE is supposed to represent the size of the REGBAR MMIO space in KiB. It is currently sized at 4MiB, but this is incorrect, EDS Vol. 2 indicates REGBAR is 16MiB in size, therefore update the constant to reflect this. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0cfbe5b8bb07faa854efd4bf70640daa117f2bb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-28soc/intel/common/tcss: Rename TCSS_DISPLAYTim Wawrzynczak
This name isn't very meaningful, rename the config option to ENABLE_TCSS_DISPLAY_DETECTION to make its meaning more obvious. Change-Id: Ib21a3b5a37d25f93bd515f8c6e5ad39c9d2ea1c4 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51771 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28soc/intel/tigerlake: Move TCSS code to intel/common/blockTim Wawrzynczak
The Type-C subsystem ("TCSS") IP block is similar between TGL and ADL. For pre-boot purposes, the limited amount of functionality required appears to be common between the two, therefore move the functionality to intel/common/block and rename from `early_tcss to `tcss` along the way. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1c6bb9c7098691f0c828f9d5ab4bd522515ae966 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51753 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28soc/amd/common/gpio: add PAD_NF_SCI pad typeFelix Held
This patch adds a pin configuration macro that supports both switching a pin to its native function and configuring it as a SCI source. This is a preparation to remove the GPIO2 soc_gpio_hook. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If0da5c010f35fd902f6b8857368daec93c12394a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50373 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28soc/amd/picasso/mca: add missing comma in mca_bank_name array of stringsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Found-by: Coverity CID 1451389 Change-Id: I0af379360fc95e4c6b72d677738c6e7497ed9206 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-28soc/amd/common/block/i2c: Use `size_t` for `num_pins`Angel Pons
There's no need to use a fixed-width type here. Change-Id: I727c64661990040db356c5508fecc0a65960c095 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51794 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28soc/amd/common/block/i2c: Fix printf format specifiersAngel Pons
The correct printf format specifier for an `unsigned int` is `%u`. Change-Id: Iaf780eb366f8c3493b89beb9a5643fa285e7825d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51793 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-27soc/mediatek: Adjust hsa, hbp, hfp packets for MIPI_DSI_MODE_LINE_ENDJitao Shi
ANX7625 requires the line packets to end at the same time. Otherwise, the display will be shifted. BUG=b:173603645 BRANCH=kukui TEST=Display is normal on Jacuzzi Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I5949de1a9a1947fa188233787166a478b1de68b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-27soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.hSubrata Banik
Lists of changes: 1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS 2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to soc/gpio.h. Refer to detailed description below to understand the motivation behind this change. An advanced GPIO PM capabilities has been introduced since CNP PCH, refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions. Now with TGP PCH, additional bits are defined in the MISCCFG register for GPIO PM control. This results in different SoCs supporting different number of bits. The bits defined in earlier platforms (CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the common GPIO code to keep the bit definitions in intelblock/gpio.h, but the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so that each SoC can provide this as per hardware support. TEST=On ADL, TGL and JSL platform. Without this CL : GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable) With this CL : GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable) Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-27soc/intel/common/block/gpio: Fix typecasting issueSubrata Banik
This patch fixes unsigned conversion from 'int' to 'uint8_t' {aka 'const unsigned char'} changes value from '-256' to '0' [-Werror=overflow]. Change-Id: Ifcc42e5a2ff06f0af0eb96bef4c6044cbcdbd94b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-27soc/intel/alderlake: Correct GPE DWx assignment as per EDSSubrata Banik
List of changes: 1. Update GPIO Group to GPE DWx assignment encoding as per MISCCFG register per GPIO Community. 2. PMC_GPP_* macros are also updated as per GPIO_CFG register in PMC space. BUG=b:183464235 TEST=Able to fix the TPM IRQ issue on SM. Change-Id: Id9f57b0b5726315f5ebba013f11d52ed3ee34484 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51789 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-26soc/intel/xeon_sp: Move PCH PCI device definesMarc Jones
Move the PCH PCI device defines out of the SOC specific PCI defines and into a common include. The PCH is common and doesn't need duplicate definitions. Change-Id: I1ca931e0f01e03c67f8f65ed7fd33c2c1d22183d Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-26soc/intel/alderlake: Add provision to override Rcomp settingsSubrata Banik
Add function to allow overriding the RcompResistor and RcompTarget UPDs from mainboard if required. Mainboard users can pass required rcomp from memory.c file. Refactor ddr_config structure to take out rcomp related variable outside for all memory type to override if required. BUG=b:182772421 TEST=Able to override the default RcompResistor and RcompTarget values. Change-Id: Ie8528bbf0517728534d47f9adaabfc9a2c469609 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-26soc/intel/alderlake: Align RcompResistor definition as per MRCSubrata Banik
List of changes: 1. Alder Lake MRC is expecting a RcompResistor value of word width. Reference RCOMP resistors on motherboard are ~ 100 Ohms but coreboot is passing an array of RcompResistor which is not completely in use. Note: Rcomp resistor value represents rcomp resistor attached to the DDR_COMP pins on the SoC. 2. Also, remove usage of '&' with memcpy the required value into RcompTarget array. 3. Also, update RcompResistor value for ADLRVP. BUG=b:183341229 TEST=Enable FSP debug log to verify the override value for RcompResistor is reflecting correctly. Change-Id: I69c7cec55b65036fc039c33374a3fd363ef7004e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-25soc/amd/common/block/i2c: fix control flow bugFelix Held
commit 4f87ae1d4a3a597f1260534001bd99160cc8ca99 introduced a regression in the I2C initialization resulting in soc_i2c_misc_init never getting called, since the continue statement was indented like it belonged to the if above, but due to the missing curly braces it was outside the if block. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Found-by: Coverity CID 1451395, 1451387 Change-Id: Id1f17ad59cba44e96881f5511df303ae90841ab3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51786 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25soc/amd/common/block/gpio_defs: Wake from either S0i3 or S3Karthikeyan Ramasubramanian
Add a helper bit mask to enable wake from either S0i3 or S3. BUG=None TEST=Build the Guyrbush mainboard. Change-Id: I934abad78135260081a61aee4c496b362e483de1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-24mb/google/guybrush: disable KBRSTENKangheui Won
GPIO129 is muxed with KBRST, so setting GPIO129 to low causes reset when KBRSTEN is set to 1. Since reset value of KBRSTEN is 1 we need a logic to clear it. BUG=b:183340503 TEST=build Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I194e8432a14d6105f6bcf12111647f5aad4e2de2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-04 22:33:19 +0000