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2015-03-26tegra132: provide more robust array bounds checkingAaron Durbin
Make sure the array size matches the number of supported FUNITs. Also remove the FUNIT_NONE enumeration so that there isn't an empty slot in the array at index 0. BUG=chrome-os-partner:31251 BRANCH=None TEST=Built when array wasn't large enough. Compiler threw an error. Change-Id: I1b83ddff799a56ea39efa23a91dca1a9e0f10862 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4cbe74905bbeb815e9f20bcc0fad3751a3133b04 Original-Change-Id: I0bb37c51311d202729b7fb9731d6eec0a28dc040 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212330 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8935 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: add base addresses to funit structuresAaron Durbin
To provide easier access to the base addresses of the controllers by funit identifier add the base addresses to the data structure. BUG=chrome-os-partner:31251 BUG=chrome-os-partner:31106 BRANCH=None TEST=Built. Change-Id: I427d432beef36e6342c188d607c0e33b3845c0e1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c8f09e61e3dbfbc96980b98ad25e09554fd49a8d Original-Change-Id: Iff5564b250dcf2038252d54a4caec3df5f7f3de7 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212169 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8934 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: add more base addresses to address mapAaron Durbin
Provide consistently named base address enumerations as well as provide some that were missing. BUG=chrome-os-partner:31251 BRANCH=None TEST=Built. Change-Id: I2551bbaa83d1d2c158b87d239098c22fba4d3961 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 07954a231f3c11c4102f9db0a2d35654abda208f Original-Change-Id: I75030598f7da7dacf8e8eff1d7427c5bf202814f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212168 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8933 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: break out clock config in funit libraryAaron Durbin
In order to prepare for USB initialization move the clock configuration into a separate routine in the funit library. BUG=chrome-os-partner:31251 BRANCH=None TEST=Built and booted into recovery mode. Change-Id: I090b5d12c5805f0179c29cfc62499fad2f245c01 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f7adaf969762b8296034f4373f550a902d1ed06b Original-Change-Id: Iea6cd2fbe8369a91c06b15d94b63c409ae83124f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212167 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8932 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: use pointers in funitcfgAaron Durbin
Just use direct pointers to the registers in the pre-filled data structures. In 64-bit the sizes increase, but it's small. The fields now directly point to the correct register so no need to do any arithmetic to identify the correct register. BUG=chrome-os-partner:31251 BRANCH=None TEST=Built and booted on ryu into recovery. Change-Id: I0de85c486c005aed23b6118ec91b45dd39acdfb0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 358b78c1c4cb72e0166f91b36011676e65576666 Original-Change-Id: I186bf5d145437472126067960e62d7ed6a25f295 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212166 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8931 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: add i2c2 controller to funit libraryAaron Durbin
BUG=chrome-os-partner:31251 BRANCH=None TEST=Built and ran on ryu through depthcharge into recovery mode. Change-Id: Ie49968c47d59b3149fc75e709825129b3cd9b09f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0cf78e310e51426371b0632e089eef500d687e48 Original-Change-Id: I76fa8f1c3469b049df7f5bf943701ce18deeb927 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212151 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8929 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra: Clean up USB codeFurquan Shaikh
Pull out the common usb setup utmip functions from t124 into tegra usb.h. These can be reused for t132 as well. BUG=chrome-os-partner:31293 BRANCH=None TEST=Compiles successfully for nyan, big and blaze Change-Id: Idddd40e409b56875436db6918d05f2889d83870b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 12f12cb30a033cce645f53457d13a987aeec22a1 Original-Change-Id: I83f83bafad0f52ad651fe5989430f41142803f2b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211200 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8927 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: fix carveout address calculation >= 4GiBAaron Durbin
The high address field was being shifted in the wrong direction resulting in the lower 12 bits of the upper address being dropped. BUG=chrome-os-partner:30572 BRANCH=None TEST=Was able to run on ryu and not hang while wiping memory. Change-Id: If1d7ef1c63ce79c143af3c5012b206ee297cd889 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6b0da6fa391db2ec2bc1e0bec9325f4e74b5286c Original-Change-Id: I7bf173bb0373d2d25ce9014c80236fb55cc8e17e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211941 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/8923 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26t132: Implement clock initialization api for functional unitsFurquan Shaikh
This api provides a common interface to initialize various clock sources, dividers as well as enabling the clock for various functional units. BUG=chrome-os-partner:31251 BRANCH=None TEST=Compiles successfully for rush and boots till last known good point. Change-Id: I2b8df5abf7301bc940315427af4cb38a635f07f8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9814f93a9f99fc9df6267167f991ebef427e9ae3 Original-Change-Id: I7abb193d6a9cfa448df1c48c346b4edbad802329 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211765 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8921 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: move common bootblock init into SoC codeAaron Durbin
The current 2 boards were setting up clocks and enabling peripherals that apply to the SoC generically. Therefore, move the common pieces into the SoC code. BUG=chrome-os-partner:31105 BRANCH=None TEST=Built and booted through depthcharge on ryu. Change-Id: I94ed4b5cc4fafee508d86eefe44cf3ba6f65dc3b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6dad573c8689b79bb4aa615811a10f44e7d8c809 Original-Change-Id: I6df1813f88362b8beaf1a716f4f92e42e4b73406 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211191 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/8917 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-25tegra132: enable pinmux input for PAD_CFG_GPIO_INPUT()Aaron Durbin
The original intent was to set the equivalent flags by default for the PAD_CFG_* macros so as not to make the usage too chatty. The GPIO_INPUT variant didn't have the PINMUX_INPUT_ENABLE field set. Therefore, automaticaly set it for PAD_CFG_GPIO_INPUT(). BUG=chrome-os-partner:29981 BRANCH=None TEST=Built and ran on ryu. Change-Id: Iab058874314430de08010912c3fc758a98b73eb0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 535cdb354efc067caf32d32641846f11fb0cd2ee Original-Change-Id: Ifb630601cf04d2984542933382aace16540863ad Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211133 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8913 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25tegra132: select HAVE_MONOTONIC_TIMERAaron Durbin
The tegra132 SoC provides the monotonic timer API. Therefore, ensure the reset of the coreboot infrastructure is aware. BUG=None BRANCH=None TEST=Built and ran on Ryu. Noted that ramsgage is showing timings for each bootstate. Change-Id: Ifc2d5b7eb318ffac0ad79bfbc3d1b61a7ba4b10c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b691572c63a43a01a290f1c00f71097028d1415e Original-Change-Id: I9b8fcf38cba9bdaaf0455701df1d6328bf1927c1 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211132 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8912 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25tegra132: use pre-existing reset APIAaron Durbin
coreboot already has a reset API. Utilize it by selecting HAVE_HARD_RESET. The tegra132 boards have to provide the hard_reset() implementation as that involves board-specific bits. The tegra132 code then provides a cpu_reset() routine that just promotes that call to a hard_reset(). For the existing tegra132 boards remove the unnecessary files from the build. BUG=chrome-os-partner:30784 BRANCH=None TEST=Ensured hard_reset() does something on Ryu. Change-Id: I6d5aa928fec95b361175e35e0a26812829ffdfc3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 31edd4ff7486ded87d2525cd360d48959b6aef7c Original-Change-Id: I1e1b014062dafb5d81fb9da40006c5405073a95d Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211131 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8911 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25tegra: correct gpio_index_to_port() calculationAaron Durbin
The gpio_index_to_port() incorrectly was dividing by GPIO_PORTS_PER_BANK on a value including the bit number. After masking off the BANK offset just divide by the number of gpios in a port to get the port offset. BUG=chrome-os-partner:29981 BRANCH=None TEST=Built and ran through to depthcharge. Printed bank, port, and bit numbers for validation. Change-Id: I3fbbb90f369bace90e787148a58795b7b1b40c1b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 97e1f830b4a8e948673433bfa6d81586204b6ee2 Original-Change-Id: I8bb50e922c9fd7c0a1c247ba95394f6deb9f1533 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210909 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8908 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25tegra132: fix gpio constantsAaron Durbin
I erroneously added GPIO_NONE_INDEX at the beginning of the enum block effectively putting every GPIO index off by 1. Instead, move it to the end. BUG=chrome-os-partner:29981 BRANCH=None TEST=Built and ran through to depthcharge on rush. Also printed out banks, port, and bit offsets to validate. Change-Id: I4f6510c1b6fcdddddbe36ff738299b4439ffc597 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c020c2125b9a2378a7faa17209d1b78e019c7df Original-Change-Id: I0471480e8658de9e534beb859a1f5027a961d73e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210908 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8907 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25tegra132: output chip information and MTS versionAaron Durbin
It's helpful to be able to track this information. Therefore dump it in to the console log. BRANCH=None BUG=chrome-os-partner:31126 TEST=Built and ran on rush. Revision information is put out on the console. Change-Id: I22e7d222259c1179b90edda6d7807559357f6725 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 18d318331b696a6a32e0a45b8f903eb740896b02 Original-Change-Id: Ic95382126a6b8929d0998d1c9adfcbd10e90663f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210903 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8905 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25tegra132: introduce romstage_mainboard_init()Aaron Durbin
Instead of calling out with function names all the possible combinations of interface and device provide one call to the mainboard to configure all the necessary bits. BUG=chrome-os-partner:31104 BUG=chrome-os-partner:31105 BRANCH=None TEST=Built and ran on rush. Change-Id: Id7817e85065884d64f90ac514bf698bf539f2afe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f4f63f5965d403a32872d7b52c180694f5ef679d Original-Change-Id: Id27d9c2da4dccdff38c48dc5cdeb1a68cf23cbfc Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210838 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8901 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-25ryu: Add mainboard_init_xxx functions to get it building againTom Warren
Rush has its EC on SPI, and Ryu has it on I2C, so need both mainboard_init_ec_spi and mainboard_init_ec_i2c in both builds, due to romstage.c being in the common tegra132 subdir. BUG=none BRANCH=rush_ryu TEST=Built both rush and rush_ryu images OK. Will try to boot on Ryu later. Change-Id: Iddbf9e9f6de7ba7244f9dd2e810fb6178937c85a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d8b81717c366d19b43964bed3c4047598db4495 Original-Change-Id: I48d9530697d5669177ecd9ba3c34360197002003 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210595 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8900 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24tegra132: add bootblock_mainboard_early_init()Aaron Durbin
Instead of hard coding certain pieces of a board in the common chipset code provide a way to initialize things early in the bootblock path. Add a bootblock_mainboard_early_init() function before console init to performany necessary mainboard initialization early in the bootblock. BUG=chrome-os-partner:31104 BUG=chrome-os-partner:31105 BUG=chrome-os-partner:29981 BRANCH=None TEST=built both on rush and ryu. rush still behaves the same. Change-Id: Idcf081eeffd189a4e2cbfeb8a4ac5dd0a3d1f838 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4a523add6de03bea0d88e95b9dbb5e283c629400 Original-Change-Id: I7d93641dff3a961f120e8f0ec2d959182477ef87 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210835 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8877 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24tegra132: use padconfig for initializing uart padsAaron Durbin
Start using the soc_configure_pads() API. This allows for bulk processing of pads. BUG=chrome-os-partner:31105 BUG=chrome-os-partner:31104 BUG=chrome-os-partner:29981 BRANCH=None TEST=Built and can get console messages on rush. Change-Id: Id2c8a685a4566bda8fc260f74f5dffdd0da03056 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bbd7c81bc0777b38bb641b9fcf89425bfd93566d Original-Change-Id: Iaa6a6ff4d559aedb98b078e87b0ecddefd3402d6 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210834 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8876 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24tegra132: provide pad configuration interfaceAaron Durbin
Instead of sprinkling the pad configuration and pinmux selection throughout the code allow for a data-driven initialization sequence. Most of the calls in the original pinmux functions require 12 bytes per pad plus the support code. This implementation allows for 4 bytes per pad in addition to the support code. BUG=chrome-os-partner:29981 TEST=Built and booted into depthcharge on rush. Change-Id: I22c243a5f9891a97e14b78d8c8064e36adaf50b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9329c17bbadcaab803b38842e38e1704d262817d Original-Change-Id: I3a119b4068e880b74a0a1597f143d7c4e108a6c1 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210833 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8875 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24rk3288: sync i2c driver with depthchargeDaisuke Nojiri
this change syncs the i2c driver with the one in depthcharge. BUG=None TEST=Booted Veyron Pinky BRANCH=None Change-Id: Ic9c7006770bba50fd412e0bcefc52f879b7195ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Id: 95ca6c88061062c0de95a8dd3567a71a372771b0 Original-Change-Id: I0d0fdefa58c5b4cc5c991be40796a800ccf074a5 Original-Reviewed-on: https://chromium-review.googlesource.com/218873 Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8872 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24veyron_pinky: Move PMIC driver into SoC directoryJulius Werner
The Rk808 PMIC is a part that will probably be used by most Rk3288 boards, so it makes sense to keep it as common code in the the SoC directory. This patch puts LDO control functions into rk3288/rk808.c, so that the mainboard only has to call a simple interface to set up the specific LDOs it requires. BUG=chrome-os-partner:30167 TEST=Booted both this and the old version with a stubbed-out i2c_writeb(), ensured that the final values are the same. Change-Id: I7efa60f8a357ce6be7490e64d2e0e3f72ad16f1c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4df22cd78ee04fefc6f7fa0e5c3d903eb1794422 Original-Change-Id: Ic172f9c402e829995f049726d3cb6dbd637039d1 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217598 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8871 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24veyron: Fix file permissionsJulius Werner
Some files for the veyron project were checked in with execute permissions where it doesn't make sense. Fix. BUG=chrome-os-partner:30167 TEST=None Change-Id: I2a96816d4fd0af3949b0adaf5208fd2862835b5b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d7a408ff273d848b60aaad4f8b27103318e56111 Original-Change-Id: Ia3788abf3755baf028518efb975701cf6cb37e46 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217673 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8868 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24rk3288: update romstage & mainboardhuang lin
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I877b4bf741f45f6cfd032ad5018a60e8a1453622 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 640da5ad5597803c62d9374a1a48832003077723 Original-Change-Id: I805d93e94f73418099f47d235ca920a91b4b2bfb Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209469 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8867 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24rk3288: add cpu and chiphuang lin
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I4c1864171e56a81e8eda95a15ca6a6bc1adc7a70 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 814af4b653432295cb6d7222af4a6e5a8d9dfbf6 Original-Change-Id: I1a986fbc8b3737bae655207dd89865dd39aecf87 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209467 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Reviewed-on: http://review.coreboot.org/8866 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24rk3288: add ddr driverJinkun Hong
Supports DDR3 and LPDDR3.Supports dual channel.ddr max freq is 533mhz. ddr timing config file in src\mainboard\google\veyron\sdram_inf Remove dpll init in rk clk_init(), add rkclk_configure_ddr(unsigned int hz). BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I429eb0b8c365c6285fb6cfef008b41776cc9c2d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 52838c68fe6963285c974af5dc5837e819efc321 Original-Change-Id: I6ddfe30b8585002b45060fe998c9238cbb611c05 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209465 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8865 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24rk3288: add gpiohuang lin
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I63b4a62f624d34f7028321cb4576cbdb9cd10817 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3606d7eb06d66e23f4ee7ecb6862d23bde3acfd2 Original-Change-Id: I3e0cff1c6de464a8a79e30e239cfb0960cbae253 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209460 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8864 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24rk3288: add i2chuang lin
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I23af280764eb28d3f6b215ab32553fe42ee73272 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: abf5c14c8b32573107d2a1c73a752e740264db7e Original-Change-Id: I46257cc71cc3cd1e867edf589ddf09f7990d6784 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209462 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8863 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24add make_idb.py & update bootblockhuang lin
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: Ica7b2bf2cf649c2731933ce59a263692bb2c0282 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ba9c36daedc749748f45e68a84f8c34c636adb1c Original-Change-Id: Ia0e4e39d4391674f25e630b40913eb99ff3f75c4 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209427 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8862 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-24rk3288: add mediahuang lin
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I74b30ecfe40c039855b835db0dfd0cd25adf960e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a30378a3152c930029a5b170cc6bf46180b5c7b8 Original-Change-Id: I5105e5277b8072c06bb41b39479373697ef81c67 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209468 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8860 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24rk3288: add iomux operationhuang lin
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: Ia19f8084a945992d9f252eb080c6c5c9990ac7de Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 30d02610e8e1e018025c2c1c970fb5b33d67d51b Original-Change-Id: I8f273f8850e4792ca976bb7c2ed39cbe501401f2 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209461 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8861 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24rk3288: add spihuang lin
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I858ac723d640dde8538aebb968fcff364fa7207c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8253a9dbad2afdf9eb9a8554fd355e6815887407 Original-Change-Id: Ib6ee7e3092429a3e47b102751ed6a88aeb9ee7d3 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209429 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8859 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24rk3288: add clock modulejinkun.hong
Call rkclk_init() in bootblock stage. apll = 816MHz, gpll = 594MHz, cpll = 384MHz, dpll = 300MHz arm clk = 816MHz, DDR clk = 300MHz, mpclk = 204MHz, m0clk = 408MHz l2ramclk = 408MHz, atclk = 204MHz, pclk_dbg = 204MHz aclk = 148.5MHz, hclk = 148.5MHz, pclk = 74.25MHz BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: Id5967712e25df5be3a90f5d9ebe8671034deff68 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d35d9fe7b5925291e9303e5eb21d20dbbdee99d9 Original-Change-Id: I97d953258039f6caa499cef4462be8f1a05ce2ab Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209428 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8858 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24vboot2: separate verstage from bootblockDaisuke Nojiri
With CONFIG_RETURN_FROM_VERSTAGE false, the verstage loads the romstage over the bootblock, then exits to the romstage. this is necessary for some SOC (e.g. tegra124) which runs the bootblock on a different architecture. With CONFIG_RETURN_FROM_VERSTAGE true, the verstage returns to the bootblock. Then, the bootblock loads the romstage over the verstage and exits to the romstage. this is probably necessary for some SOC (e.g. rockchip) which does not have SRAM big enough to fit the verstage and the romstage at the same time. BUG=none TEST=Built Blaze with USE=+/-vboot2. Ran faft on Blaze. BRANCH=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I673945c5e21afc800d523fbb25d49fdc83693544 Original-Reviewed-on: https://chromium-review.googlesource.com/212365 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Note: This purposefully is probably broken in vendorcode/google/chromeos as I'm just trying to set a base for dropping more patches in. The vboot paths will have to change from how they are currently constructed. (cherry picked from commit 4fa17395113d86445660091413ecb005485f8014) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I9117434ce99695f9b7021a06196d864f180df5c9 Reviewed-on: http://review.coreboot.org/8881 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24nyans: reduce code duplication in bootblock and romstagesDaisuke Nojiri
this change reduces the code duplication of the bootblock and the romstages for Nyans. BUG=none TEST=Built Nyan, Big, and Blaze. Ran faft on Blaze. BRANCH=none Original-Signed-off-by: dnojiri@chromium.org (Daisuke Nojiri) Original-Change-Id: Ieb9dac3b061a2cf46c63afb2f31eb67ab391ea1a Original-Reviewed-on: https://chromium-review.googlesource.com/214050 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit f3413d39458f03895fe4963a41285f71d81bcf5f) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I912f63b12321aa26a7add302fc8a6c4e607330ef Reviewed-on: http://review.coreboot.org/8880 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23vboot2: read secdata and nvdataDaisuke Nojiri
This code ports antirollback module and tpm library from platform/vboot_reference. names are modified to conform to coreboot's style. The rollback_index module is split in a bottom half and top half. The top half contains generic code which hides the underlying storage implementation. The bottom half implements the storage abstraction. With this change, the bottom half is moved to coreboot, while the top half stays in vboot_reference. TEST=Built with USE=+/-vboot2 for Blaze. Built Samus, Link. BUG=none Branch=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I77e3ae1a029e09d3cdefe8fd297a3b432bbb9e9e Original-Reviewed-on: https://chromium-review.googlesource.com/206065 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-by: Luigi Semenzato <semenzato@chromium.org> (cherry picked from commit 6b66140ac979a991237bf1fe25e0a55244a406d0) Change-Id: Ia3b8f27d6b1c2055e898ce716c4a93782792599c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8615 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-23ipq806x: implement GPIO APIVadim Bendebury
Add implementation of the GPIO API defined in src/include/gpiolib.h. Also, clean up the GPIO driver, make it use pointers instead of integers for register address. This requires a touch in the SPI driver, where the CS GPIO is toggled and in the board function where it enables USB interface. BUG=chrome-os-partner:30489 TEST=tested with the following patches, observed proto0 properly read the board ID. Original-Change-Id: I0962947c6bb32a854ca300752d259a48e9e7b4eb Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210115 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit e951f735001509d135cc61530ed0eecb5fc31a85) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8a612dce000931835054086c1b02ebfc43dc57d2 Reviewed-on: http://review.coreboot.org/8718 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-23Generalize revision number calculation functionVadim Bendebury
Some platforms use tertiary interpretation of GPIO input state to increase number of distinct values represented by a limited number of GPIOs. The three states are - external pull down (interpreted as 0) - external pull up (1) - not connected (2) This has been required by Nvidia devices so far, but Exynos and Ipq8086 platforms need this too. This patch moves the function reading the tertiary state into the library and exposes the necessary GPIO API functions in a new include file. The functions are still supposed to be provided by platform specific modules. The function interpreting the GPIO states has been modified to allow to interpret the state either as a true tertiary number or as a set two bit fields. Since linker garbage collection is not happening when building x86 targets, a new configuration option is being added to include the new module only when needed. BUG=chrome-os-partner:30489 TEST=verified that nyan_big still reports proper revision ID. Change-Id: Ib55122c359629b58288c1022da83e6c63dc2264d Original-Change-Id: I243c9f43c82bd4a41de2154bbdbd07df0a241046 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209673 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c79ef1c545d073eaad69e6c8c629f9656b8c2f3e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8717 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23mips: fix bootblock stack definitionsVadim Bendebury
Bootblock stack on Danube should be SRAM and defined separately from the rest of the coreboot stack. The actual coreboot stack will be defined later. The top of the stack should be above the bottom, as the stack grows towards lower addresses. BUG=chrome-os-partner:31438 TEST=ran bootblock on simulator under codescape, observed stack properly initialized. Change-Id: I43d2bae5f85a09a95ca0103b253399bd92555aef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e02724cb4b30990ebaa631dabb45917af29d6437 Original-Change-Id: I3c37c8b5a1c0e7fd19411558a8f6d899fc283191 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218732 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8767 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-23danube: Use the generic timer interfaceVadim Bendebury
Actual timer support is not yet available for Danube, it will be added soon. For now, just to make the target build, modify it to use GENERIC_UDELAY and HAVE_MONOTONIC_TIMER configuration option. BUG=none TEST=the target builds again Change-Id: Iad1ceb966d5dbc8687b966be4d2506c8f92eba5a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 261837539fb5a31f96e682edbcbbbc0e588f2750 Original-Change-Id: Ie3289eace9d2baadd01bd641b5dffc635ac80c0f Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220395 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8765 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23danube: use SOC specific rom stage codeVadim Bendebury
Romstage initialization code does not need to be board specific, keep it in the SOC directory. Should there be a need for the board specific code, it can be added later. BUG=chrome-os-partner:31438 TEST=with upcoming patches, the urara board coreboot builds fine Change-Id: Ib619fa9313d463ded13e9259e50bb5aeaab4fb05 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c08977aaa5e9b5da29359d1920d7d8b61ce86d3 Original-Change-Id: I27e2d225bd36c42ccd29128d0ea9a970566c02af Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215992 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8764 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23t132: Change romstage base addressFurquan Shaikh
Romstage was overflowing. So move the base address lower BUG=chrome-os-partner:31032 BRANCH=None TEST=Compiles successfully Original-Change-Id: Ia05034477b51b149c87347ed1880f8e85ecbfbf8 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210434 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 14af527a5d7cbb250e2358340196a9d749ec1683) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib261fdd8b4c7eb4a1660c5d02fbcd3e0e3f34b22 Reviewed-on: http://review.coreboot.org/8723 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-23t132: Add support for tpm i2cFurquan Shaikh
Iniitialize I2C bus required for TPM operation. Problem observed was that if frequency is raised above 20KHz, TPM starts responding with NAKs either for address or for data. Need to look into that. BUG=None BRANCH=None TEST=Compiles successfully and TPM success messages seen while booting. Original-Change-Id: I9e1b4958d2ec010e31179df12a099277e6ce09e0 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210001 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 01e87ae35431147f442e3f3e531537b8f0de1c9d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7dddc39d77f9a726fa51dd58ea9b7712c9a6fae2 Reviewed-on: http://review.coreboot.org/8715 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-21tegra132: convert to stopwatch APIAaron Durbin
Simplify the timed operations by using the stopwatch API. BUG=None BRANCH=None TEST=Built and booted to kernel. Analyzed logs. Output as expected. Change-Id: Ia49bccccc412f23bb620ed386b9174468a434116 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a877020c6d8ba12422c9c2c487122b7eb4a1967b Original-Change-Id: Iffc32fcb9b8bfdcfbef67f563ac3014912f82e7f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219494 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8831 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21exynos: convert to stopwatch APIAaron Durbin
Instead of open coding monotonic timer usage, use the stopwatch API. BUG=None BRANCH=None TEST=None Change-Id: I1c541c1c9f3fde0dec9163ad6cc94322538ac7f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 46ede0897687da6bcf730a8904f25e5a4485d6cd Original-Change-Id: Ia63a05850a1b6afdc42c2422332f77af516d27e3 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219716 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8825 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21tegra132: fill out udelay() implementationAaron Durbin
There was an empty udelay() implementation result in 0 waits. Provide an actual implementation. BUG=None BRANCH=None TEST=Built and ran through to depthcharge on rush. Change-Id: Ia7060566a71c36bb7e4543c2fe4ee49d168518c7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c8832e73de238358ea801ccd7c2330de35a7b40e Original-Change-Id: I201f2fdc4e4f5c88d48e4002839b03e808a5a1bc Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210827 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8830 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21tegra124: switch to stopwatch APIAaron Durbin
Instead of using rela_time use the stopwatch API as the semantics fit perfectly with the expiration usage. BUG=None BRANCH=None TEST=Built, but similar usage tested on tegra132. Change-Id: I1147f2bed84b93d1b776205df9ae04d1db9c98a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c38e054dd166d5eb53f692833b5ce88a230816e3 Original-Change-Id: I6d3f3da4e035e872890d8b67947b17a981673dba Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219712 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8819 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21danube: prepare SOC directory for uraraVadim Bendebury
These modules are necessary to resolve external names when building the board image. These are just skeletons for now which will be filled later. BUG=chrome-os-partner:31438 TEST=when config is enabled, emerge-urara coreboot succeeds. more extensive testing to come later Change-Id: I0fcb5d33187172ecac77041425402b33e89e8944 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 94ec79b0ab872f5c5fe7db5bef5fdabf77d6b3b6 Original-Change-Id: I69cc178976a910ebf8031ed9ac9ad67b4cc0878a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215678 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8763 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21imgtec/danube: Add support for ImgTec Danube SoCPaul Burton
Add build infrastructure and basic support code for the ImgTec Danube SoC. This support is sufficient to run on a simulator. BUG=chrome-os-partner:31438 TEST=none yet Change-Id: I59e36589765bf06b075fd4850215a0ef71246bb1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 881278d7fbb8e6803bc8f6f9e84c64640b097401 Original-Change-Id: Ia7ed7288b13085db7ff37b5ad75d978b6137f958 Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207974 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8762 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-20bootblocks: use run_romstage()Aaron Durbin
Instead of sprinkling the cbfs calls around (as well as getting return values incorrect) use the common run_romstage() to perform the necessary work to load and run romstage. Change-Id: Id59f47febf5122cb3ee60f9741cfb58cb60ccab5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-18bootstate: use structure pointers for scheduling callbacksAaron Durbin
The GCC 4.9.2 update showed that the boot_state_init_entry structures were being padded and assumed to be aligned in to an increased size. The bootstate scheduler for static entries, boot_state_schedule_static_entries(), was then calculating the wrong values within the array. To fix this just use a pointer to the boot_state_init_entry structure that needs to be scheduled. In addition to the previous issue noted above, the .bs_init section was sitting in the read only portion of the image while the fields within it need to be writable. Also, the boot_state_schedule_static_entries() was using symbol comparison to terminate a loop which in C can lead the compiler to always evaluate the loop at least once since the language spec indicates no 2 symbols can be the same value. Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8699 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-17ipq806x: Break apart large transfers in spi_xfer()David Hendricks
The current spi_xfer() function sets the count in hardware and then loops while waiting for the requested number of bytes to be sent or received. However, the number of bytes to be transferred may exceed the maximum count that can be programmed into the controller. This patch re-factors spi_xfer() to split the low-level FIFO handling portions for transmit/receive into their own functions to be called by loops in spi_xfer() which will break large transfers into smaller ones. BUG=chrome-os-partner:30904 BRANCH=storm TEST=built and booted with a >64KB payload on Storm Original-Change-Id: I70743487996cf08cfc602449f2181a7fcd99bfa4 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209838 Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> Original-Tested-by: Trevor Bourget <tbourget@codeaurora.org> (cherry picked from commit 5ec28de11f12c2438356f45ce978a17fbb603bf7) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0033e0dd96006cfd30a7a4f5e5a052f677e05108 Reviewed-on: http://review.coreboot.org/8676 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17t132: Add TTB_BUFFER to resource reservedFurquan Shaikh
TTB_BUFFER holds the MMU tables. Thus, this memory needs to be preserved while performing a wipe in depthcharge. Hence, marking it as reserved BUG=None BRANCH=None TEST=Compiles successfully and boots upto depthcharge. Error wiping memory tables is fixed. Original-Change-Id: Idd5cd0235d50f7b9617df2cead3bf71012e3b630 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210000 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 670e21ed11f985ca6cfef4f051c71b3c06f9c6ff) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifcbdd4fdaad0bd4bfe384698b13cc5013317345e Reviewed-on: http://review.coreboot.org/8681 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17Tegra132: Configure CPU clockJimmy Zhang
Since CCLK_BURST_POLICY and SUPER_CCLK_DIVIDER are not accesible from AVP, the first place that can change CPU clock is after CPU has been brought up, ie, ramstage in this case. CPU initial clock source is set to PLLP by MTS. BUG=None TEST=Norrin64 and A44 Original-Change-Id: I525bb2fa2be0afba52837bc0178950541535fd22 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209698 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit ba77e26508bb4a50a08d07ad15632ff1ba501bfa) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Icf2458c491b4b3a553d3e01f88c6f25b25639e89 Reviewed-on: http://review.coreboot.org/8677 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17t132: Add monotonic_timer.c to rmodules_armFurquan Shaikh
Update VBOOT_STUB_DEPS to include monotonic_timer.c BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I3cc559fa21c444da1a7976e4952ea4941c2a1428 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209972 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 8096ae56c4df4013cfc798944b98dd1078c8b451) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I68c13617b96fd872d1eaa9278de6647eccb795c3 Reviewed-on: http://review.coreboot.org/8674 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17coreboot classes: Add dynamic classes to corebootFurquan Shaikh
Provide functionality to create dynamic classes based on program name and the architecture for which the program needs to be compiled/linked. define_class takes program_name and arch as its arguments and adds the program_name to classes-y to create dynamic class and compiler toolset is created for the specified arch. All the files for this program can then be added to program_name-y += .. Ensure that define_class is called before any files are added to the class. Check subdirs-y for order of directory inclusion. One such example of dynamic class is rmodules. Multiple rmodules can be used which need to be compiled for different architectures. With dynamic classes, this is possible. BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles successfully for nyan, rush and link. Original-Change-Id: I3e3aadbe723d432b9b3500c44bcff578c98f5643 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209379 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 242bb90d7476c2ee47d60c50ee18785edeb1a295) Some of this cherry-pick had already been committed here: commit 133096b6dc31163f59f658e15f2eb342a0de2ac6 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9f5868d704c4b3251ca6f54afa634588108a788c Reviewed-on: http://review.coreboot.org/8672 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17soc/ipq806x: Replace GPT with fine grained DGT timer.Deepa Dinamani
Support 1MHz libpayload restriction on timer implementation by using DGT (debug) timer instead of GPT (general purpose) timer. BUG=chrome-os-partner:28880 TEST=manual verified DGT timer functions in coreboot and depthcharge. Original-Change-Id: Iab322d7e863e3959c027e9ce876223a64eb7e257 Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201574 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit ddf11eee5ec2d86a62095e932dbec9313b8fb9e1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id73e805801fd8d135b607df9f4f8caf567ec5b83 Reviewed-on: http://review.coreboot.org/8596 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17rockchip/rk3288: Fix whitespaceKyösti Mälkki
Change-Id: I6c3c1e871de33b4d0e968b254bbcf125cee9fddb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8704 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-16coreboot: rk3288: Add a stub implementation of the rk3288 SOCjinkun.hong
Most things still needs to be filled in, but this will allow us to build boards which use this SOC. BUG=chrome-os-partner:29778 TEST=emerge-veyron coreboot Original-Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205069 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 2f72473a8c2b3fe21d77b351338e6209035878fb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I53fd0ced42f6ef191d7bf80d8b823bb880344239 Reviewed-on: http://review.coreboot.org/8653 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-13nyan: Remove broken setup_display() from romstageJulius Werner
This patch removes a chunk of romstage code from Tegra and all Nyan boards that was supposed to enable some LCD power rails early, but never really worked. The dev_find_slot() function can only find PCI devices, which the CPU cluster is not. Since we're done with Nyan-RO and the ramstage display code is fine as it is, there is no point in trying to fix this... but we should remove it from ToT lest someone uses it as a blueprint to add more dead code to future boards. BRANCH=None BUG=None TEST=None Original-Change-Id: I6eee256873299429d4e3934fe7d454120390f34d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207720 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit a3df62a3bcefcc20ae59648f5d1f0a01db3c02c6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8deedea5e9787848aae3064509c611bc349313cc Reviewed-on: http://review.coreboot.org/8638 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-13coreboot t132: Remove empty function cpu0_config_and_resetFurquan Shaikh
This function is not used/required in t132. BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: Iba5ea3c14cc9facbf2a86aa08021edb9907f92da Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209425 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit c615136aa82d457540eb1f1308c9e986dbc9bce7) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id92d464db24298dd888cbc022204379eb8aa8aba Reviewed-on: http://review.coreboot.org/8652 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13coreboot t132: Stop running AVP at the end of romstageFurquan Shaikh
Stop running AVP at the end of romstage until event conditions are met (JTAG, GIC_IRQ or LIC_IRQ). BUG=chrome-os-partner:30831 BRANCH=None TEST=Compiles successfully and boots till last known good checkpoint. Original-Change-Id: Ia221f08b27ac0c60a66d588e351677144cc6a322 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209424 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit df4e8b4c8a1002443a936bd0563fbc9e0710f489) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I59f7702bd50a1039b8723e9cb12b8d714e353d37 Reviewed-on: http://review.coreboot.org/8651 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13tegra132: fix Rx FIFO underruns with slower SPI clockAaron Durbin
The SPI controller operates on packets which can be variable length up to 32-bit packets. It also has the ability to be put in packed or unpacked mode w.r.t each packet. i.e. does a single fifo register hold >= 1 packet. The current programming uses 8-bit packets in unpacked mode which means 4 fifo slots are used for a 32-bit DMA transfter. As the AHB can only operate on a minimum of 32-bit bursts the triggers need to be programmed correctly so that there is room for a full 32-bit DMA transaction. Previously faster SPI clocks just made things magically work. BUG=chrome-os-partner:30779 BRANCH=None TEST=Built and booted through coreboot with 20MHz SPI clock. Original-Change-Id: I3f1cd4dddcea9514327b2363ed450a527db7e1fe Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208862 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit d9864228a2479e412d7e0d2221fe536f78329acd) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I61c145f35e1f889d4f83f3dfea049bfd347c1196 Reviewed-on: http://review.coreboot.org/8649 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-13tegra132: Add Trust Zone register accessAaron Durbin
The Trust Zone carveout registers are only accessible using a secure access mode. The AVP runs as non-secure all the time. In EL3 the CPU is in secure mode, but when the MMU is enabled the page tables dictate if accesses to certain regions are secure or not. However, ramstage is currently being loaded into non-secure memory and the page tables will live in non-secure memory as well. Therefore, handle all these cases by providing global state which mirrors the TZ register. BUG=chrome-os-partner:30782 BRANCH=None TEST=Built and ran through ramstage with the MMU enabled Resources are read and set accordingly. Original-Change-Id: Ib76b2641497a29ef2adb75934b2df55ecf0b3e78 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209061 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 0bcbdc56978f6ebe3e7d1b74ed2fd861e03bb562) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9c1beed443a48870ba190427e87caf90caf4ff6b Reviewed-on: http://review.coreboot.org/8648 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-13t132: Add mmu supportFurquan Shaikh
Add support for mmu initialization and enabling caches. mmu_operations provides functions to add mmap_regions using memrange library and then calls mmu_init for armv8. BUG=chrome-os-partner:30688 BRANCH=None TEST=Compiles rush successfully and boots until depthcharge load. Goes past all the earlier alignment errors. Original-Change-Id: I57c2be80427fa77239093c79ece73e31fd319239 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208762 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit a6141d13d40cfa5a493bde44e69c588dda97e8fd) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I33bf4b2e28b85a3117b566cb8497f2bd5aabb69b Reviewed-on: http://review.coreboot.org/8647 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13tegra132: Add code to setup chip operations and mem resources.Tom Warren
With this memory resource, the payload loading code should be able to create a bounce buffer and load the payload successfully. Adapted from tegra124 soc.c BUG=None BRANCH=None TEST=Built and booted to ramstage on rush. Original-Change-Id: I2e336ce93c1b0236104e63d3785f0e3d7d76bb01 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208121 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 20765da0b15ee8c35a5bbfe532331fc6b1cef502) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I267ced473ad0773b52f889dfa83c65562444c01f Reviewed-on: http://review.coreboot.org/8644 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-13ryu: Add support for full LPDDR3 SDRAM BCT init via BootROMTom Warren
Once LPDDR3 init is supported in the ryu romstage, this can be reverted. Note that this 528MHz BCT has been pre-qualed by NVIDIA AE's, but will be updated as more tuning is done. BUG=none BRANCH=none TEST=Builds, BCT is in binary, but I have no HW here to test on Original-Change-Id: I315a9a5d56290bb5f51863b15053d2171db7b1e4 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208384 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 660e40cb473d47ce763e79d6061367bf381a1c48) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I29ad31fc83f45ca8f92809a7dc252cf984c8c6fe Reviewed-on: http://review.coreboot.org/8643 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-13tegra132: split memory range querying to above/below 4GiBAaron Durbin
The address map code was originally assuming all carveouts would be packed together in the upper end of the physical memory address space. However, the trust zone carveout is always in the 32-bit address space. Therefore, one needs to query memory ranges by above and below 4GiB with the assumption of carveouts being packed at the top of *each* resulting range. BUG=chrome-os-partner:30572 BRANCH=None TEST=Built and ran through coreboot on rush. Original-Change-Id: Iab134a049f3726f1ec41fc6626b1a6683d9f5362 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208101 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 8d5795fbff36e91906384e10774a32541d358324) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If15ff48d5a4c81731eb364980b30c8086deb1cca Reviewed-on: http://review.coreboot.org/8641 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-12storm: allow to override CBFS_SIZE configuration settingVadim Bendebury
The default CBFS size configuration setting is incorrect in case of Qualcomm SOC targets, as the coreboot blob is much smaller than the actual bootprom. Note that this size also must match the board fmap defined in the appropriate depthcharge board directory. BUG=chromium:394068 TEST=manual . previously failing to boot coreboot image does not fail to load depthcharge anymore. Original-Change-Id: I1b178970b1deee05705490542e4a0c57500379dd Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208146 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 01f3561fdee7b5547534e20d423fbbb1b490532c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If573bbc6254cf6786e75970eae3ad2b327a7ecfe Reviewed-on: http://review.coreboot.org/8640 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-12t132: handle optional Trust Zone region correctlyAaron Durbin
Provide a default Trust Zone region size of 1MiB, and correctly account for it in the AVP and the arm64 cores. The different path between the arm64 cores and the AVP is because the AVP cannot access the Trust Zone region registers. Therefore the AVP needs to account for the Trust Zone region. BUG=chrome-os-partner:30572 BRANCH=None TEST=Built and ran. Noted Trust Zone region being accounted for. Original-Change-Id: Ie0f117ec7a5ff8519c39778d3cdf88c3eee57ea5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208062 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 22f2fa05c009c58f53b99b9ebe1b6d01fdac5ba7) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I28506b4401145d366b56126b2eddc4c3d3db7b44 Reviewed-on: http://review.coreboot.org/8639 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-12intel/fsp_baytrail: Add PCI Root Port IRQ RoutingMartin Roth
This change generates the ASL tables needed for the PCIe bridge routing. It generates this ASL (swizzled for each of the 8 functions) Name(RP1P, Package() { Package() {0x0000ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, Package() {0x0000ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, Package() {0x0000ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, Package() {0x0000ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, }) Name(RP1A, Package() { Package() {0x0000ffff, 0, 0, 20 }, Package() {0x0000ffff, 1, 0, 21 }, Package() {0x0000ffff, 2, 0, 22 }, Package() {0x0000ffff, 3, 0, 23 }, }) Device(RP01) { Name(_ADR, 0x1c0001) Name(_PRW, Package() { 0, 0 }) Method(_PRT,0) { If(PICM) { Return (RP1A) } Else { Return (RP1P) } } } Change-Id: Id51261c11f8457fe2150f2b646aafc4fe1ffec30 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8429 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-10ACPI: Get S3 resume state from romstage_handoffKyösti Mälkki
There is nothing platform specific in retrieving S3 resume state from romstage_handoff structure. Boards without EARLY_CBMEM_INIT update acpi_slp_type from ACPI power-management block or scratchpad registers. Change-Id: Ifc3755f891a0810473b3216c1fec8e45908fc1ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8188 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-09broadwell: enable PCIe endpoint CLK power managementKane Chen
BUG=chrome-os-partner:31424 BRANCH=none TEST=build only, due to I don't have broadwell system with wifi to test need somebody help me to verify Change-Id: I52360176e135ea7f01cc67a926be4870265f57d1 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://chromium-review.googlesource.com/220743 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/8448 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09coreboot: fix munged license textAaron Durbin
At some point the license text for a file was incorrectly changed. That license was then copied and pasted. I'm sure it was myself. Anyhow, fix the bustedness. Change-Id: I276083d40ea03782e11da7b7518eb708a08ff7cd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8620 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-07t132: add Kconfig option for MTS microcode directoryAaron Durbin
In order to make sharing of the location of MTS microcode easier provide a Kconfig option that is the path to the files. BUG=chrome-os-partner:30569 BRANCH=None TEST=Built rush coreboot. Original-Change-Id: I36775d0018fc8591d5e77c2943e28a51381713f5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207839 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 6f1de0e7fd312c1d6798e65d4b43d586f0994337) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I660cb9d8bd13c765c89b54b0807b5b3ee836e807 Reviewed-on: http://review.coreboot.org/8614 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-07tegra132: add preboot MTS to bct generationAaron Durbin
The preboot MTS microcode needs to be supplied within the bct so the BootROM can load it. The size of the bootblock space in SPI needed to be extended to accomodate the extra length. BUG=chrome-os-partner:29059 BUG=chrome-os-partner:29060 BRANCH=None TEST=Built rush with updated cbootimage with t132 support. Original-Change-Id: Iafc1837cd81cc1165a9be5da6ec7425cec2e2ffc Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204940 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 22e054496465c74fc12afd865d14b87c5858d889) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5e46c408a7215ecc789b0a0f35070ef9036a7d11 Reviewed-on: http://review.coreboot.org/8466 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-05tegra132: add support for TZ carve-outAaron Durbin
The TrustZone carve-out needs to be taken into account when determining the memory layout. However, things are complicated by the fact that TZ carve-out registers are not accessible by the AVP. BUG=chrome-os-partner:30572 BRANCH=None TEST=Built and booted to end of ramstage. Noted that denver cores can read TZ registers while AVP doesn't bother. Original-Change-Id: I2d2d27e33a334bf639af52260b99d8363906c646 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207835 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit a4d792f4ed6a0c39eab09d90f4454d3d5dc3db26) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8fbef03d5ac42d300e1e41aeba9b86c929e01494 Reviewed-on: http://review.coreboot.org/8593 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-03-05t132: handle carve-outs for addressable memoryAaron Durbin
The carve-out regions need to be taken into account when calculating addressable memory because those regions aren't accessible from the main cpu. The additional exposed functions are to accommodate adding resources during ramstage resource reading. The TZ (trust zone) region is empty for now until more documentation is provided on determining its location. BUG=None TEST=Built and booted through attempting payload loading. MTS carve-out is taken into account programmatically. Original-Change-Id: I3301b2a12680ad79047198ada41f32eb1b7fa68b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207585 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 15b9c74dd1ef5bfb1fd7c6dab50624f815658e14) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I46d54dbbb8e102fc70ab34bc4bbd2361ef1ea504 Reviewed-on: http://review.coreboot.org/8591 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-05t132: Enable cbmem console supportAaron Durbin
Enabled CBMEM support for t132 platforms. Some of the existing code is moved around to avoid dependencies in the other stages that need it. BUG=None BRANCH=None TEST=Built and booted a rush with cbmem support. Original-Change-Id: I78a31b58ab9cc01a7b5d1fffdb6c8ae0c446c7dd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207163 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit f552197dbda06c754b5664c3bed4ed361154229a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8fa2919714b467cc976e5bb5c4716e5b7979694b Reviewed-on: http://review.coreboot.org/8589 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-05t132: bring up 64-bit denver coreAaron Durbin
The startup sequence for cpu0 is implemented while also providing a trampoline for transitioning to 64-bit mode because the denver cores on t132 come out of cold reset in 32-bit mode. Mainboard callbacks are provided for providing the board-specific bits of the bringup sequence. BUG=chrome-os-partner:29923 BRANCH=None TEST=Built and booted through ramstage. Original-Change-Id: I50755fb6b06db994af8667969d8493f214a70aae Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207263 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 17f09bf4bdb43986c19067ca8fd65d4c5365a7c6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I14d99c24dd6e29a4584c8c548c4b26c92b6ade97 Reviewed-on: http://review.coreboot.org/8586 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-05fsp_baytrail: Add I2C driverWerner Zeh
Add a driver wich can handle the internal I2C controllers of Baytrail SoC. This driver is not suitable for the SMBus controller. Change-Id: I841c3991a2fb0f8b92b8e59ec02d62f5866f5bdf Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/8401 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-05fsp_baytrail: Add new microcode for Bay Trail MWerner Zeh
Add a new microcode for Bay Trail M D0 stepping used in cpu N2807 silicon. In addition, a selection of the used CPU type has been added (I or M/D) which allows to use only the really needed microcode for a given CPU type. Change-Id: I373fc9b535f1dc97eaa9f76ae46f0b69b247a8a0 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/8399 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-04coreboot t132: Stack init re-workFurquan Shaikh
1) In order to avoid stack from overflowing during ramstage decompression, initialize stack right at the beginning of romstage. 2) Declare different Kconfig options for stack at each stage. 3) Provide a macro that does stack seeding if required and calls appropriate function. BUG=None BRANCH=None TEST=Compiles and runs successfully on rush. Original-Change-Id: I55d6ce59ea91affba3e86d68406921497c83fb52 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206880 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 5e32d73803a2a9d222fcc4ca5f58efd3abe95d34) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib833a1badb170a33cbf20d232019425b59db60cd Reviewed-on: http://review.coreboot.org/8583 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04t132: kick off core complex after loading MTS microcodeAaron Durbin
Once the MTS microcode is loaded the core complex can be directed to decode the MTS and start running. The cores, however, won't start executing until instructed to do so. BUG=chrome-os-partner:29222 BRANCH=None TEST=Built, booted, ran. Noted it took about 920ms for the core complex to decode and handshake back. Original-Change-Id: I0a9ed53e596eb65801461b2769d133710a92a48a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/206075 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit 6edb6e21a69d84ba5b23137e9e390954159e7887) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I179e561bb3a34b206620eecde6781a1c05a3744e Reviewed-on: http://review.coreboot.org/8581 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-04t132: load MTS microcodeAaron Durbin
The armv8 cores need to have microcode loaded before they can be taken out of reset. Locate and load the MTS microcode at the fixed address of 0x82000000. The ccplex, once enabled, will decode and transfer the microcode to the carveout region. BUG=chrome-os-partner:29922 BRANCH=None TEST=Built and ran. Confirmed dump of MTS region after loading code. Original-Change-Id: Ie5ab72e5363cbdb251d169356f718020d375fce6 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/206290 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 6726d8862c08b155b9218aa5e2e39428a105089e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I425c2e2fd1eaec49d81bef1ff4bf4f36da9296df Reviewed-on: http://review.coreboot.org/8580 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-04t132: Replace fallback with CONFIG_CBFS_PREFIXMarc Jones
Use the Kconfig value to load the name of the stage instead of the hard-coded fallback stage. (cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1ac707efe38e29f109dbbe206de74fbfe7cb7b0b Reviewed-on: http://review.coreboot.org/8576 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04t132: Add shared romstageAaron Durbin
There's no reason to duplicate code in the mainboards. Therefore, drive the flow of romstage boot in the SoC. This allows for easier scaling with multiple devices. BUG=None BRANCH=None TEST=Built and booted to same place as before. Original-Change-Id: I0d4df84034b19353daad0da1f722b820596c4f55 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205992 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie74f0eb1c983aff92d3cbafb7fe7d9d7cb65ae19 Reviewed-on: http://review.coreboot.org/8575 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot rush: Add dram init codeFurquan Shaikh
Add support for initializing dram within romstage. This is an essential before we move to the armv8 core. BUG=None BRANCH=None TEST=Compiles succesfully for rush. Tried writing to and reading value from the base of sdram and it worked fine. Also tested with primitive_memtest CL: https://chromium-review.googlesource.com/#/c/186309/5 Original-Change-Id: I67ec04c766e249c9727b0cf2ba216522c862c2f5 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205823 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 33c468b16e7ccd8cf9266d6a9ca30c02da104821) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4baface2c109ca74f85f43a25508677c46c64159 Reviewed-on: http://review.coreboot.org/8574 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot rush: Add support for basic romstageFurquan Shaikh
Add basic romstage support for rush. Since, dram init needs to be done before we can jump to armv8 core, romstage will run on armv4 core as well. Thus, correcting the compiler selection options. BUG=None BRANCH=None TEST=Compiles successfully for rush. Prints romstage banner and initial printk Original-Change-Id: Ie3cd290e56a712b07c1503dab199e4e34cec04d2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205763 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit d20b4e66209e902f54a07a17d5ce741f0a0b3a7b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic6b7ef4a2ea01c95d0c7f040bbd079219cf5750a Reviewed-on: http://review.coreboot.org/8573 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-04coreboot t132: Enable loading of romstage from CBFS mediaFurquan Shaikh
Add proper Kconfig options and initialize cbfs media to enable loading of romstage BUG=None BRANCH=None TEST=Compiles successfully for rush and cbfs_load_stage returns entry pointer for romstage Original-Change-Id: If62edcdc0496d89d30003ffd7b827b77835910fd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205762 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c89c05bc86fd6c1e49fbed5e0730659b64bffc6c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I68c10171424c85605b5065a19634d3c5dd639b78 Reviewed-on: http://review.coreboot.org/8572 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot t132: Remove init pllx for nowFurquan Shaikh
We suspect that the code was stuck on init pllx (PLLX - acts as a clock source for the CPU cluster). So, remove the init call for pllx. This needs to be added later when required. Also, add a few more printks to display the progress. BUG=None BRANCH=None TEST=Compiles successfully for rush. Print messages seen on serial console. Original-Change-Id: I70e908a9ce1f3598d68bda68c0401a78834597d1 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205680 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit d557d99edb855fbf7b32231c6746c676041bf62a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iaf56f2d587708c6e9fb01d4ced2edb5931075a81 Reviewed-on: http://review.coreboot.org/8571 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot t132,rush: Add mainboard specific bootblock_initFurquan Shaikh
Pull in mainboard specific bootblock_init function from nyan into rush. Additionally, pull in all files required for proper compilation of rush after adding the bootblock_init function BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I69c736275f66eca3ad92f97d166e91d4c2301364 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205583 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit e7aac547026717d7380f71593010e3ea34ecea51) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie26f91f8caaa06af3b195246febcdc70b9fe9795 Reviewed-on: http://review.coreboot.org/8570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-03coreboot t132: Add clock.c to all three stages of corebootFurquan Shaikh
Enable adding of clock.c to romstage and ramstage in addition to bootblock. Code for enabling armv8 core is not included yet. clock_init added to bootblock.c BUG=None BRANCH=None TEST=Compiles successfully for rush. Original-Change-Id: I858c41a83d665da2c406707586b5e35a732177d4 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205581 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 61dbf1db72307815c4abdc218799479c334a4882) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I688e1e1373dea26557a84507a8e92d3055862801 Reviewed-on: http://review.coreboot.org/8569 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-02coreboot arm: Define function for setting cntfrq registerFurquan Shaikh
Define functions for setting cntfrq register in arm and arm64 arch. This allows SoCs to set this register independently of the architecture being used. BUG=None BRANCH=None TEST=Compiles successfully for nyan and rush Original-Change-Id: I93240419b2c012eee29a408deff34a42af943a63 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205580 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 768463fef5d630dec915aa0b95e7724d4a6f74b6) armv8: GPL license armv8 lib BUG=None BRANCH=None TEST=Compiles successfully. Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250950 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I298c3e76cb52f0876bce3dd4f54d875f62e9310a Reviewed-on: http://review.coreboot.org/8468 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-02tegra132: Enable bootblock support in tegra132 including UART supportFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: Ia9420cfec5333dd5477f04cf080bdad8a37db025 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203143 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit a1037f203c6a07cb116eeb1632cb7200ad022cd3) This cherry-pick was modified to match the tegra124 uart.c, which uses the idx and base address calculations instead of Kconfig settings. This driver could use the 8250MEM driver when the ARM vs x86 IO calling convention is worked out. Change-Id: I6e439359b8bb541db4679ac144c519cf251ffed6 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8517 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-27x86: Fix pointer arithmetic regressions from MMIO changesKevin Paul Herbert
During the development of commit bde6d30 (x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer), there were several iterations and patterns tried. An intermediate pattern was the use of u32 pointers, and division by sizeof(u32). Some of these did not get properly changed to pointer types of length 1, causing a regression in the Intel Ibex Peak SATA driver, fixed in commit 9b5f137 (Intel ibexpeak: Fix SATA configuration). Other regressions of this pattern are fixed here. I audited all changes to u32 types, and the other ones are safe. Change-Id: I9e73ac8f4329df8bf0cdd1a14759f0280f974052 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Reviewed-on: http://review.coreboot.org/8530 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-25tegra124: Clean up ARM UART driver buildMarc Jones
CONFIG_CONSOLE_SERIAL_UART has been updated to CONFIG_DRIVER_UART. The UART may be used for more than serial console. Change-Id: Ife6e6861d210126b2b9ba5eee9ff72e8a447c47f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8516 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-25soc/intel/baytrail/Kconfig: Remove explicit `HAVE_MONOTONIC_TIMER`Paul Menzel
Fix up commit ce7ecf9c (baytrail: enable monotonic timer), which selected `HAVE_MONOTONIC_TIMER` explicitly, although it is already selected by `TSC_MONOTONIC_TIMER` (cf. `src/cpu/x86/Kconfig`). Therefore remove the explicit selection of that Kconfig option. Change-Id: I8964771947a6f7457dcdefe7a17be623ae0ef900 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/8471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-25intel/broadwell: free local heap objectPatrick Georgi
No real harm done (thanks to our free() implementation), but let's do it right. Change-Id: Ib98d28aabc043dff5c288728c33490a79f09f35a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/8511 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>