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2023-05-13soc/cavium: Guard gcc specific compiler flagArthur Heymans
TEST: BUILD_TIMELESS=1 remains the same. Change-Id: I740b59574303145fc673a97556367daefe8d1540 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74540 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13soc/mediatek/mt8195/apusys_devapc.c: Fix unsigned comparisonArthur Heymans
Clang warns about unsigned comparison below 0. Use the enum value itself to fix this warning. Change-Id: I12fccff2fb7d43fd4582afd518a7eab632908a5f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74553 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-12soc/intel/apl: Remove set but unused variableArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I62b7390c2de244cce169550e9b1fa41af738525d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75037 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-12soc/mediatek/mt8183: Fix set but unused variablesArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I1c995d942fa25a9268fbf716034335937df57714 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75036 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-12soc/qualcomm/sc7180: Fix set but unused variablesArthur Heymans
This fixes clang warnings. Change-Id: I407da6ec05ef646f61bd81e314fee1b5ea659192 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74557 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-12soc/intel/common: Define enum types for MKHI group IDs and ME SKUsSridhar Siricilla
The patch defines enum type for MKHI group IDs and ME SKU types instead of macros. TEST=Build code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I102e802938a6a664a43a362d90a26755cff8f316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Harsha B R <harsha.b.r@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2023-05-12soc/intel/common: Remove superfluous cmos_offset from ramtopSean Rhodes
Having `_cmos_offset` in a CMOS offset is superfluous; remove it so the CMOS entry is just `ramtop`. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibc1e7d78d2e3ae04330d19e64c3437ff07060ea8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-11soc/intel/apollolake: Only use 8 bits for afterg3Sean Rhodes
In GEN_PMCON1 (Offset 1020h), Bit 0 is the "After G3 Enable" (ag3e) (source Intel document #569262). Only use 8 bits, in the same way as most other Intel SOCs do, for pmc_soc_set_afterg3_en. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Idb290d1480b03cb3425edc6ff29b9c78a6545df1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74955 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-11soc/intel/cmn/blk.cse: Fix check condition in store_cse_rw_fw_version()Dinesh Gehlot
The return value of cse_get_bp_info() is an enum integer, where zero means success and non-zero means failure. The function store_cse_rw_fw_version() calls the function cse_get_bp_info() and validates the return value as a boolean causing prematurely returns of the parent API even if cse_get_bp_info() is successful. This patch corrects this logical error by returning only if cse_get_bp_info() fails. TEST=Build and boot google/nivviks and verify that the ISH version info command is only being sent during cold boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ice278e5ac69ff2f2c9f1936b76d71ae9deb6f855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74998 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-05-11soc/intel/common: Fix long delay when ME is disabledSean Rhodes
If the ME is disabled with the `me_state` CMOS setting, boot times are approximately 5 seconds longer: 942:before sending EOP to ME 1,240,773 (5,599) 943:after sending EOP to ME 6,263,951 (5,023,177) Total Time: 6,167,443 This is because the current code only checks if the ME is disabled for CSE LITE SKUs. With this patch, boot times are approximately 5 seconds quicker: Total Time: 1,143,932 Tested on `starbook/adl` and `starbook/tgl`. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I182f30d4fbf43955747c6a7a0b284a43f9c5e4ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/74435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-11soc/intel/meteorlake: Increase pcie snoop/non-snoop latencyRavi Sarawadi
This fixes an issue where pcie was not power gating and blocked S0ix entry. Overwrite pcie max non-snoop and snoop latency tolerance values to 15.73ms as stated in doc #729123 - MTL External Design Specification. BUG=none TEST=Boot google/rex, print/check values. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com> Change-Id: I9dfb9edbac95d28d50653777466ea172be64f612 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68308 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-10soc/intel: Clean up some includesKyösti Mälkki
Change-Id: Ibb680bb8f94fb8a2812f420ac38f15684b5c0b4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-10sb,soc/amd,intel: Sync FADT entries visuallyKyösti Mälkki
Change-Id: I20a66dce1612ab4394c26f9b0943dac14bcdcfc4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-10soc/intel/cmn/pcie: Allow SoC to overwrite snoop/non-snoop latencyBora Guvendik
The Intel SoC Meteor Lake requires a higher pcie max non-snoop and snoop latency tolerance. Add config to let SoC overwrite the common code settings if needed. BUG=none TEST=Boot google/rex and print/check if able to overwrite values. Change-Id: Ic2b9a158d219e6c6e7f6e7f0ae0f093c1183b402 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-10soc/intel/elkhartlake: Make hard drive type for SATA ports configurableMario Scheithauer
Intel's EHL FSP offers the possibility to select the connected hard drive type to SATA ports. One has the option to choose between HDD ('0' - default) and SSD ('1'). This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: Idb03aff5b6c5df592b47e2f4abe4fe58ac7151ba Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74946 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-09mb/google,intel: Use common ChromeEC code for lid shutdownKyösti Mälkki
Change-Id: I4d34e5c094440dad4a6ab9adc67d3da6b71ac2bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74514 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-05-09sb,soc/amd,intel: Apply minor FADT fixesKyösti Mälkki
Change-Id: I27a610255e5680be1b507d45c6695cf9419ee052 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-09soc/intel/xeon_sp/spr: Drop spurious FADT fieldsKyösti Mälkki
Assigning duty_offset while duty_width==0 has no purpose. Under intel/common/block, previous assignment for fadt->gpe0_blk resolves GPE0_STS(0) from xeon_sp/ebg/.../soc_pm.h and also assigns value matching pmbase + 0x60. Change-Id: Iaf688d9471ac527ac20307cf16216abdab731a06 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74827 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-08Revert "soc/amd/cezanne/romstage: Preload fspm.bin"Raul Rangel
This reverts commit d6e0a90aa0bd574b28b6c9b4b46289bf46a208db. Reason for revert: Not ready to land, blocked by ancestor CL Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic14e17db4aed2f998878920c66cdc16362920dcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/75050 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-08soc/amd/cezanne/romstage: Preload fspm.binRaul E Rangel
FSP-M is normally memmapped and then decompressed. The SPI DMA controller can actually read faster than mmap. So by reading the contents into a buffer and then decompressing we reduce boot time. It is interesting that FSP-M takes an additional 8ms to execute. I suspect since we call it 50ms earlier it's having to wait for one of its dependencies. BUG=b:179699789 TEST=Boot guybrush and see 30ms reduction in boot time | 970 - loading FSP-M | 0.316 | 0.997 Δ( 0.68, 0.05%) | | 17 - starting LZ4 decompress (ignore for x86) | 0.026 | 13.874 Δ( 13.85, 0.96%) | | 18 - finished LZ4 decompress (ignore for x86) | 64.361 | 0.337 Δ(-64.02, -4.43%) | | 2 - before RAM initialization | 0.534 | 0.529 Δ( -0.01, -0.00%) | | 950 - calling FspMemoryInit | 1.455 | 1.132 Δ( -0.32, -0.02%) | | 951 - returning from FspMemoryInit | 207.695 | 216.537 Δ( 8.84, 0.61%) | Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I850b1576501753a355e7b23745e04802a0560387 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-05-08soc/amd/phoenix/include/xhci: add USB4 XHCI device pointersFelix Held
Beware that there's no XHCI2 controller and the USB4 controller device pointers were added right after the xhci_0 and xhci_1 controller device pointers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I14725d4b546ffcca42e21bbe7756babaaff8fea3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74658 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-08soc/intel/early_graphics: support to allow early graphics GPIO configTarun Tuli
For early Sign of Life to work, we may need certain pin configurations very early in boot (e.g. HDMI). This may happen before romstage GPIOs are configured, and bootblock is not suitable for field upgrading existing devices. Add a separate GPIO table that can be configured when early graphics is invoked. BUG=b:277861633 BRANCH=firmware-brya-14505.B TEST=Builds and SoL functions on HDMI enabled variants Change-Id: I7b3ce96a4166451e72aa70b3086eff3fb8b082b7 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-05-08soc/amd/*/acpi/northbridge,pci0: don't hide PCI0 root device from OSFelix Held
Return 0xf from PCI0 _STA method so that bit 2 is set which indicates that the device should be shown in the user interface. This ports commit c259d7192806 ("soc/amd/stoney/acpi: Unhide PCI0 root device from OS") forward from Stoneyridge to the newer AMD SoCs. TEST=On Mandolin the PCI Express Root Complex now shows up in the device manager on Windows 10 and when switching the view to 'devices by connection', all PCI(e) devices are shown below it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4155556dc5df8f163fe06aa6719fadbb2684cc19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74949 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-08soc/intel/meteorlake: Apply large cbmem buffer size for FSP debugSubrata Banik
This patch ensures that the PRERAM_CBMEM_CONSOLE_SIZE and CONSOLE_CBMEM_BUFFER_SIZE hold a larger cbmem buffer size to contain the entire FSP debug serial log. The existing implementation was not appropriate, where the larger cbmem size was even applicable for serial AP firmware (w/o FSP debug) image as well. This change is necessary to ensure that the FSP debug serial log is always available, even in cases where the cbmem buffer size is limited. BUG=b:280481298 TEST=Able to build and boot google/rex with non-FSP serial AP image and with FSP serial AP image. Able to see the AP log completely inside the cbmem. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib35780fd558c8b6d9aa2e17241131ea4a58c2b9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-06soc/intel: Do CSE sync in romstage, unless ramstage chooses otherwiseSubrata Banik
This patch makes CSE sync in romstage default enabled unless ramstage config (SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) chooses to override it. TEST=Able to build google/marasov with this change where CSE sync is performed early inside romstage. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3f5017fbcf917201eaf8233089050bd31c3d1917 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-05-05soc/amd/cmn/acpi/sleepstates.asl: Align with sb/amdAngel Pons
Adjust a few things so that the sleepstates.asl file is the same for sb/amd and soc/amd. These adjustments don't have a functional impact. Change-Id: I0cc9462b326cdc371ffdbf5759d8adc42456ce74 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74960 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-05{sb,soc}/amd/cmn/acpi/sleepstates.asl: Hook up configsAngel Pons
Commit cbc5d3f34b87db779829eabc90c32780a3865a56 ("soc/intel: Don't report _S1 state when unsupported") added the `ACPI_S1_NOT_SUPPORTED` option and commit 0eb5974def63a2fc0dce6dfdad62b0b4c6f4b865 ("acpigen: Add a runtime method to override exposed _Sx sleep states") added a mechanism to override the enabled sleep states at runtime. However, these were only hooked up to Intel sleepstates. so the options would not have any effect on AMD platforms. Apply the changes from these two commits to AMD sleepstates so that both options can be used on AMD platforms as well. Change-Id: I7d5ef2361e36659ac5c6f54b2c236d48713a07c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74959 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-05src/soc/intel: Document meaning of variablesMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Iaf88f34cedd09e2461bb05050392e178ec84d5d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-05soc/intel/spr: Fix copy paste issue in error messagesFelix Singer
The commit a0b199c6b483 ("soc/intel/xeon_sp/spr: Add soc set_cmos_mrc_cold_boot_flag") introduced a copy-paste issue in two error messages. The error messages should mention the Intel platform SPR instead of CPX. Fix that. Change-Id: I4de61ec2cf9fbd98263a7a7a588938d548148656 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74956 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-04soc/amd/common/block/lpc/lpc: simplify index handling in read resourcesFelix Held
Now that we don't need to find a specific resource in the set resources function any more, there's no need to use hard-coded indices for the fixed resources. Instead use an index variable that gets incremented after each fixed resource got added. The index now starts at 0 instead of at 1, but now the only requirement is that those indices are unique. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ida5f1f001c622da2e31474b62832782f5f303a32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74849 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-05-03soc/amd/common/block/lpc/lpc: drop custom lpc_set_resourcesFelix Held
Drop the custom lpc_set_resources implementation that does some register access that has no effect and then calls pci_dev_set_resources and use pci_dev_set_resources for set_resources in amd_lpc_ops instead. The SPI controller's base address got configured early in boot in the lpc_set_spibase call and the enable bits got set early in boot in the lpc_enable_spi_rom call. TEST=The contents of the SPI_BASE_ADDRESS_REGISTER at the beginning and at the end of the call stay the same, so it's simply a no-op. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7a5e3e00b2e38eeb3e9dae6d6c83d11ef925ce22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03soc/amd/common/block/lpc/lpc: report HPET MMIOFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I77471d464dddffc63bb2f005fef3a33c84ff5f5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03soc/amd/common/block/lpc/lpc: use mmio_range to report FCH IOAPIC MMIOFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I813a27e392a842188dc474018f82e10309783260 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03soc/amd/common/block/lpc/lpc: report eSPI MMIOFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I63fb70da3e9ded6c05354f94ee69bc6dd04e58f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByteFelix Held
The memory map granularity for those devices is 4kByte. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8806128bdce8988f5cd7c8fa8a342fdb01eb7f42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03soc/amd/common/block/lpc/lpc: report mapped SPI flash as MMIO rangeFelix Held
Since the 16MByte of memory-mapped SPI flash region right below the 4GB boundary is both a fixed region and isn't decoded on a device below the LPC device, but assumed to be decoded by the LPC device itself, it shouldn't be reported as a subtractive resource, but as an MMIO resource instead. TEST=On mandolin the 16MByte MMIO-mapped SPI flash now show up as a reserved region in the e820 memory map which wasn't the case before: 13. 00000000ff000000-00000000ffffffff: RESERVED The Linux kernel doesn't show any new or possibly related errors. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Ib52df2b2d79a1e6213c3499984a5a1e0e25c058a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03soc/amd/phoenix: Add default vBIOS ID and locationMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Iadc32f4dbf8bd48d8666a213d7b5f3ba42175a90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-02soc/intel/alderlake: Disable C1E on RPL CPUsJoey Peng
Since disabling C1E could improve acoustic noise for RPL, add judgement in SOC code to disable C1E on RPL CPUs and enabling it on ADL CPUs . BUG=b:278654939 TEST:emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-05-02soc/intel/alderlake: Select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN configSubrata Banik
At present the problem has only been reported with Alder Lake and Raptor Lake FSP where MultiPhaseSiInit API is unable to return any ERROR status. Hence, this patch ensures to select applicable W/A config to read FSP return status from the FSP Reset HOB. BUG=b:278665768 TEST=Able to select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN for ADL/RPL SoC code and call into this API to know the return status from MultiPhaseSiInit FSP API. Without this patch: IshInit() Start IshDisable() Start IshPerformGlobalReset() .... .... FSP returning control to Bootloader with reset required return status 40000003 FspMultiPhaseSiInit Index-1 returned 0 <-- after control returns into coreboot, the `status` from the FSP API is reset to `0` instead 0x40000003. Hence, coreboot avoid hitting the reset. With this patch: IshInit() Start IshDisable() Start IshPerformGlobalReset() .... .... FSP returning control to Bootloader with reset required return status 40000003 FSP: handling reset type 40000003 <-- coreboot is able to understand the reset request in proper. GLOBAL RESET! global_reset() called! HECI: Global Reset(Type:1) Command Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I18a918cca7e19e03ed6020c55c86c64a94212963 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74785 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-02soc/intel/common: Introduce API to get the FSP Reset StatusSubrata Banik
This patch creates a function to read the FSP API Reset Status. This function relies on the FSP Scheduled Reset HOB which holds the reset type (warm/cold/shutdown) information along with any platform specific reset need (like global reset). Ideally FSP API should be able to return the status (both success and error code) upon exiting the FSP API but unfortunately there are some scenarios in ADL/RPL FSP where MultiPhaseSiInit API is unable to return any ERROR status. Hence, this function provides an additional hook to read the FSP reset status by reading the dedicated HOB without relying on the FSP API exit status code. Additionally, create FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN config option to handle broken FSP API return status issue. Any SoC platform that selects the `FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN` config will call into this newly added API to get the FSP return status from MultiPhaseSiInit. BUG=b:278665768 TEST=Able to select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN for ADL/RPL SoC code and call into this API to know the return status from MultiPhaseSiInit FSP API. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ief5d79736cc11a0a31ca2889128285795f8b5aae Reviewed-on: https://review.coreboot.org/c/coreboot/+/74783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-01soc/intel/adl: Unhide PMC, IOM ACPI devices from OSMatt DeVillier
These were hidden because no Windows drivers existed, but now that they do, the ACPI devices need to be visible in order for the drivers to properly attach. TEST=build google/banshee, boot Windows, verify Windows drivers correctly attach to PCM/IOM devices. Change-Id: Idbbaee29bffb49059d8450abd09e0c3f7b490fae Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74850 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-01soc/intel/tgl: Unhide PMC, IOM ACPI devices from OSMatt DeVillier
These were hidden because no Windows drivers existed, but now that they do, the ACPI devices need to be visible in order for the drivers to properly attach. TEST=build google/drobit, boot Windows, verify Windows drivers correctly attach to PCM/IOM devices. Change-Id: I1520a71e318674baa234fc6a2126d1d17933d983 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-01soc/amd/stoney/acpi: Unhide PCI0 root device from OSMatt DeVillier
In order for Windows to detect/load drivers for any child devices, the PCI0 root device status must be enabled and visible. TEST=build google/liara, boot Windows, verify PCI child devices visible in Device Manager. Change-Id: I3fb1ba11247f0811120a4cf8a4fd99342ae201de Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-01soc/intel/cmn/cse: Decouple ME_RW compression from CSE RW SyncAnil Kumar
The change 'commit Iac37aaa5ede5e1cd ("Add Kconfigs to indicate when CSE FW sync is performed")' adds support to choose CSE FW update to be performed in ROMSTAGE or RAMSTAGE. The patch also introduced a dependency on ME_RW firmware compression. This patch removes the dependency between CSE FW sync in RAMSTAGE and ME_RW firmware compression as these two are not related and should be decoupled to support CSE FW sync in RAMSTAGE without the requirement to compress ME_FW. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I5ca4e4a993e4c4cc98b8829cbefff00b28e31549 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74796 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-04-29sb,soc/amd,intel: Drop include <cpu/x86/smm.h>Kyösti Mälkki
I forgot to remove these in commit 0fe36db154eb ("ACPI: Make FADT entries for SMI architectural"). Change-Id: Ib1bc1dad6053ddb0454d4510917fd2bcf0901f35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74811 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-29ACPI: Make FADT entries for RTC/CMOS architecturalKyösti Mälkki
For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY that points to same offset. Since the century field inside RTC falls within the NVRAM space, and could interfere with OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY. There were no reference for the use of offset 0x48 for century. Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-28soc/amd/phoenix: Populate type 0x63 entry with right MRC CacheFred Reitberger
On boards with RECOVERY_MRC_CACHE FMAP section, populate type 0x63 BIOS directory entry in RO with that section. If the RECOVERY_MRC_CACHE section is not present, then fall back to RW_MRC_CACHE. BUG=b:270569389 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ic5ac87685eaa5fec717e3efa4df7af511b4ce8aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/73257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-04-28soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR windowFelix Held
This ports back commit d75ee46d3ce6 ("soc/amd/picasso/acpi: Change PCI0 BAR window") to Stoneyridge so that the correct end of the non-fixed MMIO region gets reported in PCI0's _CRS method. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/74809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-04-28soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI busesFelix Held
This ports commit 8c28e51a16e1 ("soc/amd/picasso: fix host bridge bus numbers") back to Stoneyridge so that the correct number of PCI buses gets reported from PCI0's _CRS method. The MCFG ACPI table already had the correct last bus number. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I40121ab0e0438281192b6a0bec8dbecdc1749379 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-04-28soc/intel/common/block/pmc: Sort Kconfig in alphabetical orderChristian Walter
Change-Id: I7392ede4226a940896c805fc0b0bc0dd615a964c Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74810 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-28vga: Change the arguments of vga_write_text to support extended ASCIIHsuan Ting Chen
VGA defined the extended ASCII set based on CP437, but the function vga_write_text() accepts a signed char array. This will cause unnecessary confusion that if we want to print u with umlaut (code=129 in CP437), we need to explicitly cast it to -127 in signed char. Since we still want to leverage the built-in string utilities which only accepts const char*, we still need to cast it to signed char while processing, and cast it back to unsigned once we write into the frame buffer. BRANCH=brya BUG=b:264666392 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: If555bbc05f40ce3f02339c0468afff6dda8b7ded Reviewed-on: https://review.coreboot.org/c/coreboot/+/73099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-27soc/amd/mendocino: update FSP parameters for eDP power sequence adjustmentChris Wang
Add UPD parameter for eDP power sequence adjustment. The edp_panel_t9_ms parameter is set for bloff to varybloff. BUG=b:271704149 BRANCH=Skyrim TEST=Build; Verify the UPD was pass to system integrated table. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Id651c9cc4d6f4e27f6c78ca10ca12936d66ef43b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74789 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27soc/amd/mendocino: rename pwr_on_vary_bl_to_blon to edp_panel_t8_msChris Wang
Rename the UPD pwr_on_vary_bl_to_blon to edp_panel_t8_ms to match the eDP sequence timing in milliseconds. BUG=b:271704149 BRANCH=Skyrim Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74787 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-27ACPI: Make FADT entries for SMI architecturalKyösti Mälkki
Change-Id: I80aa71b813ab8e50801a66556d45ff66804ad349 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74600 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-27soc/amd: Drop acpi_fill_madt_irqoverride()Kyösti Mälkki
It is unused. The use of field irq is problematic as it should appear relative to IOAPIC GSI bases in the devicetree. Change-Id: I460fd5fde3a7fba5518ccfc153a266d097a95a39 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-26intel/mtl: Add get_cse_ver_from_cbfs functionAshish Kumar Mishra
This patch implements helper function get_cse_ver_from_cbfs() to retrieve the CSE Lite version from CBFE RW's metadata and calls the helper function from cse_check_update_status() TEST=Verified CSE Lite version in coreboot boot log Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Change-Id: Ie1bf186adfc3f87826a7ce9b0167a6bbe6767299 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74755 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
2023-04-26soc/amd/common/block/gfx: Re-add signature check for vbios cacheMatt DeVillier
Commit c7b8809f155a ("soc/amd/common/block/gfx: Use TPM-stored hash for vbios cache validation") replaced checking the vbios signature (first two bytes) with checking against a TPM-stored hash, but there exists an edge case where the empty cache can be hashed and therefore never updated with the correct vbios data. To mitigate this, re-add the signature check to ensure that an empty cache will never be hashed to TPM. BUG=b:255812886 BRANCH=skyrim TEST=build/boot skyrim w/selective GOP enabled, flash full firmware image, ensure GOP driver is run until cache updated with valid data and hashed to TPM. Change-Id: Id06a8cfaa44d346fb2eece53dcf74ee46f4a5352 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-26soc/intel: Don't report _S1 state when unsupportedArthur Heymans
Since skylake Intel hardware does not support this sleep state. Trying to enter S1 by having the OS enter sleep results in a system hang on at least Alder lake (prodrive/atlas). CONFIG_SOC_INTEL_COMMON_BLOCK_PMC is a good proxy whether devices support 'skylake style' PMC PCI device for ACPI registers. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic9e19410696240755e8714db53a0525284f3a2da Reviewed-on: https://review.coreboot.org/c/coreboot/+/74760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-04-26soc/amd/phoenix/Kconfig: Update commentFred Reitberger
Fix copy-paste comment on closing endif Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9671a9228c304988eb3903391f74a21d80d0a8bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/74734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-26soc/intel/common: Use ACPI_COMMON_MADT_IOAPICKyösti Mälkki
For the first IOAPIC, use the common MADT generator with default IRQ overrides. Change-Id: Ie6e3eae1728a9a94205ec59557d4af1655191166 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26soc/amd: Use ACPI_COMMON_MADT_IOAPICKyösti Mälkki
Change IRQ #0 to GSI #2 override to positive edge trigger from the bus ISA default (positive edge). Change-Id: I2de941071fca6f7208646a065a271fbf47ac2696 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74354 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26soc/intel/baytrail,braswell: Use COMMON_MADT_IOAPICKyösti Mälkki
Change IRQ #0 to GSI #2 override to positive edge trigger from the bus ISA default (positive edge). Change-Id: I3a61a0ceb0e6e4a09570beef6d0170354eb498ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26intel/bd82x6x,broadwell,lynxpoint: Use ACPI_COMMON_MADT_IOAPICKyösti Mälkki
Change IRQ #0 to GSI #2 override to positive edge trigger from the bus ISA default (positive edge). Change-Id: Iab3d38da9610ede1d338440b4a8ec0f1537c17e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26ACPI: Add COMMON_ACPI_MADT_IOAPIC and CUSTOM_ACPI_MADTKyösti Mälkki
Add Kconfig COMMON_ACPI_MADT_IOAPIC to replace platforms' implementations of adding IOAPIC and IRQ override entries for ACPI MADT tables. Platforms that have a more complex MADT may continue to add custom entries using CUSTOM_ACPI_MADT. Change-Id: I0b77769f89cc319ad228eb37bc341e2150b8a892 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74348 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26arch/x86/ioapic: Promote ioapic_get_sci_pin()Kyösti Mälkki
Platform needs to implement this to provide information about SCI IRQ pin and polarity, to be used for filling in ACPI FADT and MADT entries. Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26soc/intel: Introduce ioapic_get_sci_pin()Kyösti Mälkki
According to ACPI Release 6.5 systems supporting PIC (i8259) interrupt mechanism need to report IRQ vector for the SCI_INT field. In PIC mode only IRQ0..15 are allowed hardware vectors. This change should cover section 5.2.9 to not pass SCI_INT larger than IRQ15. Section 5.2.15.5 needs follow-up work. Care should be taken that ioapic_get_sci_pin() is called after platform code has potentially changed the routing from the default. It appears touched all platforms except siemens/mc_aplX currently program SCI as IRQ9. Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-24soc/mediatek/mt8183: Fix set but unused variableArthur Heymans
This fixes a clang warning. Change-Id: I017ed8601e6ec4c66487e9a6f31e93251515e686 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-04-24soc/mediatek/dptx.c: Remove set but unused variablesArthur Heymans
This fixes clang warning about set but unused variables. Change-Id: I3a3345e33380862d6939b61485f6d1eefa3d1815 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74547 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2023-04-23include/cpu/amd/mtrr: fix typo in get_top_of_mem_above_4gbFelix Held
Add the missing 'b' to the 4gb so that get_top_of_mem_above_4gb is in line with get_top_of_mem_below_4gb. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic9170372d8b0c27d7de3bd04d822c95e2015cb10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-22soc/amd/glinda: drop code for non-existing eMMC controllerFelix Held
Glinda doesn't have an eMMC controller and also doesn't have GPIO pins that eMMC signals can be multiplexed on, so drop the eMMC related code from Glinda. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I49ead01075780ea97dae99a36632f7659fd00587 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74662 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-22soc/amd/phoenix: drop defines for non-existing eMMC controllerFelix Held
Phoenix doesn't have an eMMC controller, so remove the remaining eMMC- related defines. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I412c968479d23deb7f2e060b26b4a56ec9c764f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-22soc/amd/mendocino: drop code for non-existing eMMC controllerFelix Held
Mendocino and Rembrandt don't have an eMMC controller and also don't have GPIO pins that eMMC signals can be multiplexed on, so drop the eMMC related code from Mendocino. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib8ec49a7084bdd62e480baee75a280fde8b13d01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-22soc/intel/meteoerlake: set power limits dynamicallySumeet R Pawnikar
Set power limit values dynamically based on Meteor Lake CPU TDP and PCI ID of SKU. BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values for 15W SKU on Rex board Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-22soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllersFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I95916e409b3fbd4941a861054733a34100244da9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-22soc/amd/*/include/pci_devs: fix copy-paste error in PCIE_ABC_C_DEVFNFelix Held
Since it's an internal bus, it's PCIE_ABC_C_DEVFN and not PCIE_GPP_C_DEVFN. This also makes it consistent with the rest of the internal PCI buses. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ica8b666161c3cd3b0b4a29f8a4b0aff473b4d833 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-22soc/amd/phoenix/include/soc/smi: add missing SCI map defines 61-63Felix Held
In the PPRs #57019 Rev 3.03 and #57396 Rev 3.04, SMITYPE_XHC3_PME, SMITYPE_XHC4_PME and SMITYPE_CUR_TEMP_STATUS_5 are defined, so add those defines. When doing the initial update for Phoenix, at least XHC3 and XHC4 PME events were missing from the PPR. Those two are the PME events of the two USB4 controllers. SMITYPE_XHC2_PME doesn't exist on this SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6fff9175b73cc9d0fd324d4a568a5761b92d078 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-22soc/intel/cmn/cse: Make `cse_get_fpt_partition_info()` function staticSubrata Banik
The patch makes `cse_get_fpt_partition_info()` AP local/static as all the references to this function are in local to the cse_lite.c file. BUG=b:273661726 TEST=Able to build and boot google/marasov with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie50453946c8abe55c29e9001263f0264a73c8fac Reviewed-on: https://review.coreboot.org/c/coreboot/+/74388 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-22soc/intel/alderlake: Implement `soc_is_ish_partition_enabled` overrideSubrata Banik
This patch implements `soc_is_ish_partition_enabled()` override to uniquely identify the SKU type between UFS and non-UFS to conclude if ISH partition is enabled and need to retrieve the ISH version from CSE FPT by sending HECI command. TEST=Able to uniquely identify the UFS and non-UFS SKUs while booting to google/marasov. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7771aebb988f11d9d1b2824aa28e6f294fd67c25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74532 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-22mb/google/rex: Enable asynchronous End-Of-PostSubrata Banik
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post right after PCI enumeration and handle the command response at `BS_PAYLOAD_BOOT'. With these settings we have observed a boot time reduction of about 100ms on google/rex. TEST=Tests on google/rex with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post after PCI initialization and EOP message received at `BS_PAYLOAD_BOOT'. Change-Id: I27b540eeddcada521eba91fcc51504831d6dc855 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-21soc/intel/meteorlake: Don't offer D3Cold when it's disabledSean Rhodes
Use D3COLD_SUPPORT Kconfig option to adjust the maximum supported sleep state in ACPI. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifa55a19727e6adb6864158c2c323d08a0c22b996 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-21soc/intel/cmn/cse: Store ISH firmware version into CBMEMSubrata Banik
The patch stores the ISH in the CBMEM table. It verifies CSE has been updated by comparing previous and current CSE versions. If it has, the patch updates the previous CSE version with the current CSE version. It then updates the CBMEM table with the current ISH version. BUG=b:273661726 TEST=The current and old CSE and ISH versions are verified on the google/nissa during cold and warm reboots. Additionally, version updates are verified by a debug patch that purposely updated the stored cse version. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-04-21{commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEMSubrata Banik
The patch implements an API that stores the CSE firmware version in the CBMEM table. The API will be called from RAMSTAGE based on boot state machine BS_PRE_DEVICE/BS_ON_EXIT Additionally, renamed ramstage_cse_fw_sync() to ramstage_cse_misc_ops() in order to add more CSE related operations at ramstage. This patch also adds a configuration option, 'SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION', which enables the storage of firmware version information in CBMEM memory. This information can be used to identify the firmware version that is currently installed on the system. The option depends on the `DRIVERS_INTEL_ISH` config and platform should be flexible enough to opt out from enabling this feature. The cost of sending HECI command to read the CSE FPT is significant (~200ms) hence, the idea is to read the CSE RW version on every cold reset (to cover the CSE update scenarios) and store into CBMEM to avoid the cost of resending the HECI command in all consecutive warm boots. Later boot stages can just read the CBMEM ID to retrieve the ISH version if required. Finally, ensure this feature is platform specific hence, getting enabled for the platform that would like to store the ISH version into the CBMEM and parse to perform some additional work. BUG=b:273661726 TEST=Able to build and boot google/marasov. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-21soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of offMartin Roth
When one of the General-Purpose PCIe bridges is not used, it doesn't show up on the PCI bus at all, so coreboot notes it as an issue in the devicetree. This happens even if the device is marked as off. To solve this, we're marking the GPP bridge devices in devicetree as hidden, so they'll only show up in devicetree if they're actually used on a mainboard. BUG=b:277997811 TEST=Build Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I7b7577baa2dbb0ea7ebbcdb1a8ae81770e61d76f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74527 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21soc/amd/mendocino: Mark PCIe GPP bridges as hidden instead of offMartin Roth
When one of the General-Purpose PCIe bridges is not used, it doesn't show up on the PCI bus at all, so coreboot notes it as an issue in the devicetree. This happens even if the device is marked as off. To solve this, we're marking the GPP bridge devices in devicetree as hidden, so they'll only show up in devicetree if they're actually used on a mainboard. BUG=None TEST=Don't see the "PCI: Leftover static devices:" warning for these in the boot console. BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I517776e4dedc70e957a0c836ab3c2e5d49e156d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74526 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-21soc/intel/meteorlake: Add VPU into the DMAR SATC tablezhaojohn
This change adds the VPU into the DMAR SATC table in order to support the VPU IO virtualization. BUG=None TEST=Enabled the VPU, booted to kernel and verified that DMAR SATC table includeded the VPU entry. Change-Id: I6d4af7c9844e33483a1e616eaee061a90d0be6fc Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-21soc/intel/(adl, cmn, mtl): Refactor cse_fw_sync() functionSubrata Banik
This patch refactors cse_fw_sync() function to include timestamp associated with the CSE sync operation.This effort will ensure the SoC code just makes a call into the cse_fw_sync() without bothering about adding timestamp entries. TEST=Able to build and boot google/marasov. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib5e8fc2b8c3b605103f7b1238df5a8405e363f83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-04-21soc/intel/cmn/cse: Refactor ramstage_cse_fw_sync() functionSubrata Banik
This patch refactors sleep type check inside ramstage_cse_fw_sync() to avoid additional logic while performing cse_fw_sync() operation. TEST=Able to build and boot google/marasov. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7c7a91c81d51dbf6742e12c58a24b9f52fff5630 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-04-21soc/amd/common/cpu/noncar/early_cache: use get_top_of_mem_below_4gbFelix Held
Use get_top_of_mem_below_4gb instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icc9e5ad8954c6203fc4762aa976bba7e8ea16159 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-04-21soc/amd/stoneyridge/memmap: use get_top_of_mem_below_4gbFelix Held
Use get_top_of_mem_below_4gb instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic673deb725a541c7535ae769f589cd82ea42a561 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-21soc/amd/stoneyridge/northbridge: use get_top_of_mem_[below,above]_4gbFelix Held
Use get_top_of_mem_below_4gb and get_top_of_mem_above_4g instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I04f2a3744aee9beedaa97b154a652ce6f0c705c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-21soc/amd/common/block/acpi/tables: use get_top_of_mem_[below,above]_4gbFelix Held
Use get_top_of_mem_below_4gb and get_top_of_mem_above_4g instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I35895340f6e747e2f5e1669d40f40b201d8c1845 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-21Drop unused include <version.h>Kyösti Mälkki
Change-Id: I7d0718b5d2e0dd16eb90f63dd9d33329a2d808ba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-21soc/intel/braswell: Replace <build.h> with <version.h>Kyösti Mälkki
To use generated build.h one should have had a pre-requisite in the Makefile. Reference coreboot_build_date from lib/version.c instead. Change-Id: Icd6fa2ddf8aa584b0f51ba130592f227bbdad975 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-21include/cpu/amd/mtrr: rename functions to get top of memory regionsFelix Held
Rename amd_topmem and amd_topmem2 to get_top_of_mem_below_4gb and get_top_of_mem_above_4g to make it clearer what those functions return. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6e98d94c731af74aea0ce276a9a7e4867e3986f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-21soc/amd/phoenix: Update XHCI eventsJon Murphy
Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI to allow for XHCI events to be logged. BUG=b:277273428 TEST=builds Change-Id: I3ca4f84fb0f1fef8441ab6ef7b6f6348c52b2922 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74280 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fieldsKyösti Mälkki
After the obsoletion of Processor() it is necessary to provide _CST package to define P_LVLx IO addresses for C2/C3 transitions. The latency values from _CST will always replace those in FADT. Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-21soc/amd/phoenix/xhci: Correct counting of xhci_sci_sourcesFred Reitberger
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Iabba97e003d1a5140c98e3fc5a3496f66f8795c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74528 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-20soc/intel/common/block/pcie/rtd3: Fix source clock check condition for PM methodCliff Huang
srcclk_pin is 0-based and '0' is a valid clock source number. If srcclk_pin is set to -1, then the clock will not be disabled in D3. Therefore, clock source gating method should not be generated. BUG=b:271003060 BRANCH=firmware-brya-14505.B TEST=Boot to OS and check that rtd3 ACPI entries are generated as expected. For those PCI devices with RTD3 driver whose srcclk_pin to 0, the RTD3 entries should not be missing due to check error. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia831b8fd17572cc35765bd226d1db470f12ddd41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73889 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-04-20soc/intel/meteorlake: Send CSE EOP Async CMD earlySubrata Banik
This patch sends the CSE EOP command asynchronous implementation early as part of `soc_init_pre_device`. Without this patch the duration between asynchronous CSE EOP send and receive commands is not ample which causes idle delay while waiting for EOP response. The goal of the CSE async implementation is to avoid idle delay while capturing the response from CSE EOP cmd. This patch helps to create ample duration between CSE EOP command being sent and response being captured. TEST=Able to boot google/rex sku to ChromeOS and observed ~100ms of boot time savings (across warm and cold reset scenarios) Change-Id: I91ed38edbd5a31d61d4888e1466169a3494d635a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-20soc/amd/phoenix/include/soc/pci_devs: update defines to match the PPRFelix Held
Parts of this file were still a copy of the file from the Mendocino SoC, so update the file to match the PPR #57019 Rev 3.03 and the chipset devicetree of the Phoenix SoC. Phoenix has 4 GFX/GPP PCIe bridges/ports, the numbering scheme of the GPP PCIe bridges/ports was changed so that the numbers match the device and function numbers, and there are new device functions for the IPU and the USB4 controller and router devices. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie9429c03839bb0199a04cd6cafe9a955ebdacc91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74565 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 19:31:30 +0000