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This node is required so we can add child ACPI nodes.
BUG=b:147042464
TEST=Boot trembyle and confirm Bus A has a firmware node
$ cat /sys/bus/pci/devices/0000\:00\:08.1/firmware_node/path
\_SB_.PCI0.PBRA
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I18144a69ed28a913bc9a2523d69edf84a1402e7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This is a squash of the following commits. The original values were
wrong, and had confusing naming.
soc/amd/picasso: Get rid of *_DEVID from pci_devs.h
Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Change-Id: I203449499840bf0a6df8bd879fb7d2e75a16b284
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153714
src/amd/picasso: Update PCI bridge devices
Orignal-Change-Id: I1fa9d52ce113eacdc5c9ba31ab46b6428a7d6ca9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Zork: Reorganizing ACPI and adding PCI bridge configs
Signed-off-by: Pranay Shoroff <pshoroff@google.com>
Original-Change-Id: I1e2095567525f302dfd0bce8e39001250523180b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2063536
soc/amd/picasso: Fix soc_acpi_name() to use devfn instead of devid
Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Change-Id: I2486e7e0059e0528f53d5a158c9328636563fe93
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153712
BUG=b:147042464
TEST=Build trembyle and boot to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I91bf7f9edcddf03027f8fdcaadf4e290ece10df5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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New information indicates the PSP expects the APOB NV region
populated for all types of boot, and this is not a feature only
used for S3. Switch over to using the MRC_CACHE flash region.
Remove the Kconfig symbols for the APOB_NV base and size. Override
the MRC_CACHE_SETTINGS_CACHE_SIZE to ensure the default maintains the
minimum required size. Use the generated (or mainboard-specified)
fmap.fmd file as an input for amdfwtool and properly match the
flash region.
Change the original naming for the APOB destination, which matched the
PSP spec's field name, to PSP_APOB_DESTINATION. This should be more
intuitive for a source code reader. The APOB address is the location
in DRAM where the PSP puts its output block.
BUG=b:147042464, b:153675914
TEST=Boot trembyle
Original-Change-Id: Ia5ba8646deec2bd282df930f471738723063eef8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2080375
Original-Change-Id: I972d66f1817f86ff0b689f011c0c44c3fe7c8ef7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2053312
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I4550766ece462b65a6bfe6f1b747343e08e53fe5
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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All callers just check for zero/non-zero.
Change-Id: I795763ce882d879d12c97b71e7a0b35423378c36
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Change-Id: I2de16eaa88baace28afa30345b7762353a48ab87
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41558
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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soc/i2c.h gets included indirectly via chip.h and removing the chip.h
in 73716d0e924080ea32274a265a8de04e009c3676 broke the build. chip.h got
added back, but including soc/i2c.h directly fixes the underlying issue.
Change-Id: Ic84f7b6b4447b7c335a51dc604daf8924851e555
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The audio devices are currently set to enable static devices at their
own level, but in order to supported nested SoundWire devices these
drivers must instead use scan_static_bus. Without this change the
device tree code will not look at children of these devices.
After this change the audio device can have nested devices:
device pci 1f.3 on
chip drivers/intel/soundwire
device generic 0 on end
end
end
BUG=b:146482091
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ibb716fbd9ffdc45f2c4bbe5e81f420ec2b13483c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enable DPTF functionality for volteer platform
BRANCH=None
BUG=b:149722146
TEST=Built and tested on volteer system
Change-Id: I385fb409ccd291d97369295ff99f21c9430880f9
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41427
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ACPI device names for TCSS devices which were not already defined
which match those declared in the DSDT at acpi/tcss.asl.
Change-Id: I6a79da7dd78c73345986c12d6ffe467cd4322e05
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The CA vref should alway select range[1]. But in fast calibration flow,
we missed the range selection and caused the CA vref to use the range[0] value.
The DQ vref should select correct range that corresponds to current frequency,
that is for 1600Mbps, 2400Mbps to select range[1], for 3200Mbps and 3600Mbps
to select range[0].
Refer to the 'JESD209-4 - Low Power Double Data Rate 4X(LPDDR4X).pdf',
used MR12 to set Vref(CA) levels, used MR14 to set VREF(DQ) levels.
MR12 range[0] values from 15.0% to 44.9%, range[1] values from 32.9% to 62.9%,
MR14 range[0] and range[1] values same as MR12.
BUG=b:153614919
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: Ie7680b1bf0c29c946d18e3b27626ce6f31c4216b
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40525
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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pmc.c was included in the SMM object, but only needed the one function,
pmc_soc_set_afterg3_en. pmutil.c was already doing power management-
related functionality, and was included in SMM, so moving
pmc_soc_set_afterg3_en to pmutil.c allows pmc.c to be removed from the
SMM build.
Change-Id: I87f65fd10d35f1f75516e804501d5319b81a0383
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41407
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Historically in coreboot, the PMC's fixed PCI resources were described
by the System Agent (the MMIO resource), and eSPI/LPC (the I/O
resource). This patch moves both of those to a new Intel SoC-specific
function, soc_pmc_read_resources(). On TGL, this new function takes care
of providing the MMIO and I/O resources for the PMC.
BUG=b:156388055
TEST=verified on volteer that the resource allocator is aware of and
does not touch these two resources:
("PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0
flags f0000200 index 0
PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff
flags c0000100 index 1")
Also verify that the MEM resource is described in the coreboot table:
("BIOS-e820: [mem 0x00000000fe000000-0x00000000fe00ffff] reserved")
Verified the memory range is also untouchable from Linux:
("system 00:00: [mem 0xfe000000-0xffffffff] could not be reserved")
Change-Id: Ia7c6ae849aefaf549fb682416a87320907fb3fe3
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41385
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update processor power limit configuration parameters based on
common code base support for Intel Tigerlake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on volteer system
Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39345
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove unused processor power limit configuration parameter
and function call based on common code base support for
Intel Icelake SoC based platform.
BRANCH=None
BUG=None
TEST=Built for icelake based dragonegg board.
Change-Id: Id8923f2c176092b6f7acfbfb079587f88258dce8
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41236
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order for the SOC to be able to control the Aux line orientation for
Type-C ports that do not have a retimer, the IomTypeCPortPadCfg UPD needs
to be configurable through devicetree to correctly set the GPIO pins that
the SOC should use to flip orientation.
BUG=b:145220205
BRANCH=NONE
TEST=booted Volteer proto 2 and verified that the AUX channels flip
when the cable is flipped
Change-Id: I2e48adb624c7922170eafb8dfcaed680f008936e
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40244
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add method acpi method GPID to return the GPIO PCR port ID.
This method is further planned to be used for GPIO power
management configuration.
TEST=Build waddledoo board
Change-Id: Ic45b40bbe39e303cddcc82e0e848786b7311ab64
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Remove hardcoded gpio community range, since it might differ across
the SOCs.
Change-Id: I79c10669f6096537d466d1abd356d58a50fcb8f5
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and
1 lock bit. If lock bit is set, then systemagent.asl would end up
reporting the base address of low MMIO incorrectly i.e. off by 1.
This change masks the lower 20 bits of TOLUD and TOM registers when
exposing it in the ACPI tables to ensure that the base address of low
MMIO region is reported correctly.
Change-Id: I11b3ef8deda21930998471ab6e712da4c62f5b02
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This change updates systemagent.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for auron.
Change-Id: I479bb6cb7ed4c9265325c7c8621f03454f21f467
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and
1 lock bit. If lock bit is set, then systemagent.asl would end up
reporting the base address of low MMIO incorrectly i.e. off by 1.
This change masks the lower 20 bits of TOLUD and TOM registers when
exposing it in the ACPI tables to ensure that the base address of low
MMIO region is reported correctly.
Change-Id: I2ff7a30fabb7f77d13acadec1e6e4cb3a45b6139
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This change updates systemagent.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for soraka.
Change-Id: If8d8dd50af9a79d30f54e98f7f2fe7ce49188763
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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CB:41454 updated northbridge.asl to ASL2.0 syntax. During this, GPCL
was incorrectly updated to use << (ShiftLeft) instead of >>
(ShiftRight). This change fixes the error in GPCL by updating it to
use >> (ShiftRight).
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for hatch.
Change-Id: I36469cb3b0bcc595acf0e43808d6a574986cad68
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41519
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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* Declare memory and reserved areas using HOBs for regions above top
of low memory.
* Copy northbridge_fill_ssdt_generator from stoneyridge.
BUG=b:147042464
TEST=Boot trembyle and see PCI resources in the log:
PCI: 00:00.0
PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0
PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2
PCI: 00:00.0 resource base 100000 size cd700000 align 0 gran 0 limit 0 flags e0004200 index 3
PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
PCI: 00:00.0 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 4
PCI: 00:00.0 resource base 100000000 size 12f340000 align 0 gran 0 limit 0 flags e0004200 index 5
PCI: 00:00.0 resource base 22f340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 6
PCI: 00:00.0 resource base cd800000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 7
PCI: 00:00.0 resource base cd7fe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index 8
PCI: 00:00.0 resource base cc7fe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 9
PCI: 00:00.0 resource base 1090000 size b0000 align 0 gran 0 limit 0 flags f0004200 index a
Change-Id: I44a4a97765151fbcfe4c5d8de200e3e015aaaf2e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34424
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add option to change bootloader file.
BUG=b:149934526
TEST=Change option and verify new bootloader file is used. Using the
amd_blobs I can only boot using PspBootLoader_test_RV_dbg.sbin.
Change-Id: Ib6597f7d4ffa0d48aead6974bd7111c987418f20
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2067598
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The PCI interrupt devices were only partially implemented.
* Lacked support for _DIS to disable the bus. Something the kernel does
while booting.
* Lacked support for APIC vs PIC. This means the devices can only be
used when using the PIC. By looking at the PMOD variable we can handle
both PIC and APIC. This means we can stop hard coding the PCI interrupt
numbers in the ACPI tables.
* I removed INT[E-H] since they are not used.
BUG=b:139429446, b:147042464
BRANCH=none
TEST=Boot with both the APIC and PIC and saw that the link devices work
as expected:
PIC MODE:
[ 1.959345] ACPI: PCI Interrupt Link [IRQA] (IRQs 1 3 4 5 *6 7 8 9 10 11 12 14 15)
[ 2.007344] ACPI: PCI Interrupt Link [IRQB] (IRQs 1 3 4 5 *6 7 8 9 10 11 12 14 15)
[ 2.056344] ACPI: PCI Interrupt Link [IRQC] (IRQs 1 3 4 5 6 7 8 9 10 11 12 *14 15)
[ 2.104344] ACPI: PCI Interrupt Link [IRQD] (IRQs 1 3 4 5 6 7 8 9 10 11 12 14 *15)
[ 13.752676] PCI Interrupt Link [IRQA] enabled at IRQ 6
[ 13.816755] PCI Interrupt Link [IRQD] enabled at IRQ 15
[ 27.788798] PCI Interrupt Link [IRQB] enabled at IRQ 6
[ 27.852873] PCI Interrupt Link [IRQC] enabled at IRQ 14
APIC MODE:
[ 19.311764] ACPI: PCI Interrupt Link [IRQA] (IRQs *16 17 18 19 20 21 22 23)
[ 19.374765] ACPI: PCI Interrupt Link [IRQB] (IRQs 16 *17 18 19 20 21 22 23)
[ 19.438770] ACPI: PCI Interrupt Link [IRQC] (IRQs 16 17 *18 19 20 21 22 23)
[ 19.501764] ACPI: PCI Interrupt Link [IRQD] (IRQs 16 17 18 *19 20 21 22 23)
[ 34.719072] PCI Interrupt Link [IRQA] enabled at IRQ 23
[ 34.798994] PCI Interrupt Link [IRQD] enabled at IRQ 22
[ 66.469510] PCI Interrupt Link [IRQB] enabled at IRQ 21
[ 66.542395] PCI Interrupt Link [IRQC] enabled at IRQ 20
Change-Id: I1bb84813b65c89b4b5479602be3e9a9fedb7333d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2095683
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The _PIC method sets the interrupt model (PIC or APIC). It needs to be
defined at the root level for the kernel to find it. Previously this
method was never getting called, so we were always stuck in APIC mode.
BUG=b:139429446, b:147042464
BRANCH=none
TEST=Saw the method getting called
[ 1.251774] ACPI Debug: "PIC MODE: 0000000000000001"
Change-Id: Idd5e9646df8d56e7cbec2be8b4016c36d81e5fb8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2095682
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Remove the Kconfig options for per board socket type selection and use
the runtime detection instead.
Change-Id: I82cf922661c24e2a529fa4927893727b643660e3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41518
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I643a4c5f8a42a5fb0603a1a049545b57d16493a6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41517
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I550599ae5ef9875ce820a4534d21439ff2027585
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Add telemetry setting for SDLE testing
BUG=b:147570294
TEST=Build Morphius and check the setting was been applied
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If4bb75eeaaa68b2c5a6a36c28c34fb338be65851
Reviewed-on: https://chromium-review.googlesource.com/2056885
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I26f15e7bd2f65e94ed1c2771bd8504114bfcda48
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Unused includes found using following commande:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|atol\|strrchr\|skip_atoi\|STRINGIFY' -- src/) |grep -v vendorcode |grep '<'
Change-Id: Ibaeec213b6019dfa9c45e3424b38af0e094d0c51
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
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BUG=b:147042464
TEST=Boot trembyle to OS
Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ife48d5268230f70c6a6f4a56c1f0d05b6c924891
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41381
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iad5540e791075270453a136a058823c28647f93a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
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This adds FSP UPD TcssDma0En and TcssDma1En for configuration.
BUG=:b:146624360
TEST=Built and booted on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I04af970f74ab9dfe84f9c0c09ec2098e0093fa57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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BUG=b:147042464
TEST=build trembyle and boot to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie6ac8b0701ac27733dd9724873664f5f17fcfa29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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No code that was or will be upstreamed uses functionality from soc_util
in romstage, so only compile and link it for ramstage.
This also allows to fix the SoC type detection in a follow-up patch
using information that FPS-M will be providing in a HOB.
BUG=b:153779573
Change-Id: If96e53608eadd562f6de5a0c370b89e84e43d049
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Update processor power limit configuration parameters based on
common code base support for Intel Broadwell SoC based platforms.
BRANCH=None
BUG=None
TEST=Build for broadwell based platform
Change-Id: I97e38a533e74a122b6809e20a10f6e425827ab9c
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add function to display ME Host Firmware Status registers. Make use of
print_me_fw_version() from CSE lib to print ME firmware version information.
Add manufacturing mode field in HFSTS1 register for JSL in place of,
spi_protection_mode in TGL.
BUG=None
BRANCH=None
TEST=Build and boot jslrvp. In coreboot logs, ME info can be seen.
ME: Version: 13.5.0.7049
ME: HFSTS1 : 0x90006255
ME: HFSTS2 : 0x82100136
ME: HFSTS3 : 0x00000020
ME: HFSTS4 : 0x00004800
ME: HFSTS5 : 0x00000000
ME: HFSTS6 : 0x00400006
ME: Manufacturing Mode : YES
ME: FW Partition Table : OK
ME: Bringup Loader Failure : NO
ME: Firmware Init Complete : YES
ME: Boot Options Present : NO
ME: Update In Progress : NO
ME: D0i3 Support : YES
ME: Low Power State Enabled : NO
ME: CPU Replaced : YES
ME: CPU Replacement Valid : YES
ME: Current Working State : 5
ME: Current Operation State : 1
ME: Current Operation Mode : 0
ME: Error Code : 6
ME: CPU Debug Disabled : YES
ME: TXT Support : NO
Change-Id: Ic6b1c9410db8f06ac24fd997772b2ede04264bee
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This is a missing config override in fspm_upd.
iDisplay Audio Codec disconnection
0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
BUG=b:156447983
TEST=None
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifbbc22d14e06713009c550cbe8a7292de64e1fdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41394
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update processor power limit configuration parameters based on
common code base support for Intel Skylake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on nami system
Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I96dfa5b531842afcf774dd33c2dfa532b5d329c6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Reading the SPD using the SMBUS routines takes a long time because each
byte or word is access seperately.
Allow using the i2c read eeprom routines to read the SPD. By doing this
the start address is only sent once per page.
The time required to read a DDR4 SPD is reduced from 200 msec to 50
msec.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I44e18b8ba72e1b2321f83402a6a055e2be6f940c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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If panel has too small hfp or hbp, hfp_byte or hbp_byte may become
very small value or negative value. When very small value or
negative value is used, the panel will be scrolling or distorted.
This patch adjusts their values so that they are greater than
the minimum value and keep total of them unchanged.
DSI transfer HBP or HFP, There are some extra packet. ex. packet
header(4byte) and eof(2byte) and (next)hs packet header(4 byte).
the hfp_byte = HFP * BPP - packet header(4byte) and eof(2byte)
and (next)hs packet header(4 byte). So the min hfp_byte is 2 when
HFP = 4.
This is equivalent to the Linux kernel DSI change in:
https://chromium-review.googlesource.com/c/chromiumos/third_party/
kernel/+/2186872
BUG=b:144824303
BRANCH=kukui
TEST=boot damu board with panel CMN N120ACA-EA1 (12" panel and its
hbp only 6), the panel can display without scrolling or
distortions.
Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com>
Change-Id: I608c01d41ae93c8d5094647bbf3e0ae4a23d814c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41163
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update processor power limit configuration parameters based on
common code base support for Intel Jasperlake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built for jasperlake system
Change-Id: I9b725d041dcb8847f83ec103e58b9571b4c596ac
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add processor power limits control support under common code.
BRANCH=None
BUG=None
TEST=Built and checked this entry on Volteer system,
cat /sys/class/powercap/intel-rapl/intel-rapl\:0/*
Change-Id: I41fd95949aa2b02828aa2d13d29b962cb579904a
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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By default ROMSTAGE_ADDR and VERSTAGE_ADDR are set to 0x2000000. This
causes problems in a non-xip environment because when verstage loads
romstage, it overrides it's memory. So pick a different offset for
verstage.
BUG=b:147042464
TEST=Boot verstage on trembyle and see OS boot.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2464db6f3769bd23d250588b341d1c9e44f10d21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41367
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CPU to PCH method refers to PCH ACPI operation region which was wrongly
defined as SystemIO. This causes ACPI AE_LIMIT error from PM _DSW
method. Change the operation region from SystemIO to SystemMemory to
resolve this execution failure.
BUG=b:140290596
TEST=Built and booted to kernel. _DSW method executes successfully without
ACPI AE_LIMIT error.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I3965c3d891f7d3cf4a448edc0c3f7e7749a905a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
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Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rename cse_is_hfs3_fw_sku_custom() to cse_is_hfs3_fw_sku_lite() and
rename custom_bp.c to cse_lite.c. Also, rename all CSE Custom SKU
references to CSE Lite SKU.
TEST=Verified on hatch
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I20654bc14f0da8d21e31a4183df7a2e34394f34e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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Lower 20bits of TOLUD register include 19 reserved bits and 1 lock
bit. If lock bit is set, then northbridge.asl was reporting the base
address of low MMIO incorrectly i.e. off by 1. This resulted in Linux
kernel complaining that the MMIO window allocated to the device at the
base of low MMIO is incorrect:
pci 0000:00:1c.0: can't claim BAR 8 [mem 0x7fc00000-0x7fcfffff]: no compatible brw
pci 0000:00:1c.0: [mem 0x7fc00000-0x7fcfffff] clipped to [mem 0x7fc00001-0x7fcfff]
pci 0000:00:1c.0: bridge window [mem 0x7fc00001-0x7fcfffff]
This change masks the lower 20 bits of TOLUD register when exposing it
in the ACPI tables to ensure that the base address of low MMIO region
is reported correctly.
TEST=Verified that kernel dmesg no longer complains about the BAR at
base of low MMIO.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4849367d5fa03d70c50dc97c7e84454a65d1887a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41455
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This change updates northbridge.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: If8eabb6b934b74e69cdf4e18981082028399244d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Correct comment on HMRFPO_ENABLE flow for CSE Lite SKU. In order to place
CSE into SECOVER_MEI_MSG mode, below procedure has to be followed.
1. Ensure CSE boots from RO(BP1).
- Set CSE's next boot partition to RO
- Issue GLOBAL_RESET HECI command to reset the system
2. Send HMRFPO_ENABLE command to CSE. Further, no reset is required.
TEST=Verified on hatch
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I213e02ba3898194fa6c8fe38fab34b5c19f25aa1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41340
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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The chipset code was incorrectly adding memory resources
to the domain device after resource allocation occurred.
It's not possible to get the correct view of the address space,
and it's generally incorrect to not add resources during
read_resources(). This change fixes the order by adding resources in
read_resources().
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I49ce6ac88c4cb7cd05ff9d78133593ce97304596
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41374
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The chipset code was incorrectly adding memory resources
to the domain device after resource allocation occurred.
It's not possible to get the correct view of the address space,
and it's generally incorrect to not add resources during
read_resources(). This change fixes the order by adding resources in
read_resources().
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I419be7edf289636b24b9a7d6c390866ade638de3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The chipset code was incorrectly adding memory resources
to the domain device after resource allocation occurred.
It's not possible to get the correct view of the address space,
and it's generally incorrect to not add resources during
read_resources(). This change fixes the order by adding resources in
read_resources().
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I16f0439679471366723a0084918a20cd95834831
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41372
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The chipset code was incorrectly adding memory resources
to the domain device after resource allocation occurred.
It's not possible to get the correct view of the address space,
and it's generally incorrect to not add resources during
read_resources(). This change fixes the order by adding resources
during read_resources().
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I532f508936d5ec154cbcb3538949316ae4851105
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change uses cpu_phys_address_size() to calculate the size of high
MMIO region instead of a macro for each SoC. This ensures that the
entire range above TOUUD that can be addressed by the CPU is used for
MMIO above 4G boundary.
Change-Id: I01a1a86c0c65856f9f35185c2f233c58f18f5dfe
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
There should be no harm in advertising the MMIO window above 4G in
ACPI tables unconditionally. OS can decide whether or not to use the
window. This change removes the config option enable_above_4GB_mmio
and instead adds the correct MMIO window (above 4G) details to ACPI
tables always.
Change-Id: Ie728f6ee7f396918e61b29ade862b57dac36cb08
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41276
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change sets the base for MMIO above 4G to TOUDD. It matches what
is used by resource allocator if MMIO resources are allocated above 4G
and also matches the expectation in northbridge.asl. This change
also gets rid of the macro ABOVE_4GB_MEM_BASE_ADDRESS since it is now
unused.
BUG=b:149186922
TEST=Verified that kernel does not complain about MMIO windows above
4G.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ibbbfbdad867735a43cf57c256bf206a3f040f383
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41155
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This patch adds the get_spd_sn function. It's for reading SODIMM serial
number. In spd_cache implementation it can use to get serial number
before reading whole SPD by smbus.
BUG=b:146457985
BRANCH=None
TEST=Wrote sample code to get the serial number and ran on puff.
It can get the serial number correctly.
Change-Id: I406bba7cc56debbd9851d430f069e4fb96ec937c
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40414
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Found using following commande:
diff <(git grep -l '#include <stdlib.h>' -- src/) <(git grep -l '
memalign\|malloc\|free' -- src/) |grep -v vendorcode |grep '<'
Change-Id: Ib2ee840a10de5c10d57aa7a75b805ef69dc8da84
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41241
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Unused includes found using following commande:
diff <(git grep -l '#include <stddef.h>' -- src/) <(git grep -l
'size_t\|ssize_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\
|MAYBE_STATIC_NONZERO\|MAYBE_STATIC_BSS\|zeroptr' -- src/)|grep '<'
|grep -v vendor |grep -vF '.h'
Change-Id: Ic54b1db995fe7c61b416fa5e1c4022238e4a6ad5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41150
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
unused includes of <stdin.h> found using following commande:
diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l
'int8_t\|uint8_t\|int16_t\|uint16_t\|int32_t\|uint32_t\|int64_t\|
uint64_t\|intptr_t\|uintptr_t\|intmax_t\|uintmax_t\|s8\|u8\|s16\|
u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|UINT8_MAX\|INT16_MIN\
|INT16_MAX\|UINT16_MAX\|INT32_MIN\|INT32_MAX\|UINT32_MAX\|INT64_MIN\
|INT64_MAX\|UINT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|UINTMAX_MAX' -- src/)
|grep '<' |grep -v vendor |grep -vF '.h'
Change-Id: Icb9b54c6abfb18d1e263665981968a4d7cccabeb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41148
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change selects SOC_AMD_COMMON_BLOCK_HAS_ESPI which enables
the capability for using eSPI on Picasso.
Additionally, it also calls espi_setup() and espi_configure_decodes()
if mainboard enables use of eSPI and skips LPC decodes in that case.
BUG=b:153675913,b:154445472
Change-Id: I4876f1bff4305a23e8ccc48a2d0d3b64cdc9703d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This change uses lpc_early_init() for enabling and configuring LPC
using the common block LPC driver.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I65784b481ae598bf3a85392ae4fe281aac974097
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41273
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds a helper function espi_setup() which allows SoCs to
configure connection to slave. Most of the configuration is dependent
upon mainboard settings in espi_config done as part of the device
tree. The general flow for setup involves the following steps:
1. Set initial configuration (lowest operating frequency and single mode).
2. Perform in-band reset and set initial configuration since the
settings would be lost by the reset.
3. Read slave capabilities.
4. Set slave configuration based on mainboard settings.
5. Perform eSPI host controller configuration to match the slave
configuration and set polarities for VW interrupts.
6. Perform VW channel setup and deassert PLTRST#.
7. Perform peripheral channel setup.
8. Perform OOB channel setup.
9. Perform flash channel setup.
10. Enable subtractive decoding if requested by mainboard.
BUG=b:153675913
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I872ec09cd92e9bb53f22e38d2773f3491355279e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41272
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To change frequency, the SOC PLL team suggests procedure below:
First, we need to enable the intermediate clock and
switch the ca53 clock source to the intermediate clock.
Second, disable the armpll_ll clock output.
Third, raise armpll_ll frequency and enable the clock output.
The last, switch the ca53 clock source back to armpll_ll and
disable the intermediate clock.
BUG=b:154451241
BRANCH=jacuzzi
TEST=Boots correctly on Jacuzzi.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ib9556ba340da272fb62588f45851c93373cfa919
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41077
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CB:41194 got rid of "this file is part of" lines. However, there are
some changes that landed right around the same time including those
lines. This change uses the following command to drop the lines from
new files:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic3c1d717416f6b7e946f84748e2b260552c06a1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41342
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Immediately following FSP-S, update the data fabric routing
registers to make the region between HPET and LAPIC as non-posted.
If AGESA is modified to do this, we can delete data_fabric_util.c. If
AGESA is modified to not program the registers, then we can simplify
data_fabric_set_mmio_np().
BUG=b:147042464, b:156296146
TEST=boot trembyle
Change-Id: Idbafaac158f5a4c533d2d88db79bb4d6244e5355
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41268
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The device ids are already defined in include/device/pci_ids.h as
PCI_DEVICE_ID_AMD_FAM17H_DF*.
BUG=b:147042464
TEST=Build trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic68a1067e5976af972592d7352c40a5c66dbeb8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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These are used to setup the data fabric.
Definitions came from 55570-B1 Rev 3.14 - PPR for AMD Family 17h Model 18h
BUG=b:147042464
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib51f6e2fd304da9948d6625608af71f25b974854
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41266
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Family 17h devices are designed with a new internal architecture,
frequently referred to as the data fabric. Although designed to
behave somewhat like the older integrated northbridge designs,
the D18Fx definitions are completely new.
The previous northbridge.c was copied from stoneyridge which is
completely different.
Change-Id: Id70cbda99657249179fb8cf5e461dd6a37ec9153
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41265
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These are not northbridge functions.
BUG=b:147042464
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia9e7d4c7554788a9fdbfdb90e6ead60060cc4c30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41264
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a device specific register, not a northbridge register.
BUG=b:147042464
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I97b63571e336f541dcb274e4c8c608f6fc59ff42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41263
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move this with the other acpi functions.
BUG=b:147042464
TEST=build trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I24bd5c7d7c90968759ac745012e7bbc47f0ef6a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41262
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:147042464
TEST=Build trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5df618f69a7dcca47b9733efb3699b37fd171e90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41261
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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fch_spi_ctrl.c uses read*()/write*() functions which are declared in
arch/mmio.h. This change includes the file arch/mmio.h in
fch_spi_ctrl.c.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I6540004512af1f59f5fb300a3a4818b87ad94bfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This change adds a helper function lpc_early_init() which does the
following things:
1. Enables LPC controller
2. Disables any LPC decodes (These can be set up later by SoC or
mainboard as required).
3. Sets SPI base so that MMIO base for SPI and eSPI controllers is
initialized.
BUG=b:153675913
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I016f29339466c3fee92fe9b62a13d72297c29b8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The default setting of the root port ASPM configuration can be
overridden from the device tree by using a non zero value.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I85c545d5eacb10f43b94228f1caf1163028645e0
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Current Interrupt setting use 2nd parameters as device function number.
- Correct as interrupt pin number according to _PRT package format.
{Address, pin, Source, Source index}
- Use irq number directly rather than irq definition as its number
is not for PCI device.
The issue found while enabling GBE and GBE interrupt is not working
without this change.
Reference
- ACPI spec 6.2.13 _PRT
- FSP reference code:
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/
ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/
PeiItssPolicyLibVer2.c
- BIOS reference code:
https://github.com/otcshare/CCG-TGL-Generic-Full/blob/master/
TigerLakeBoardPkg/Acpi/AcpiTables/Dsdt/PciTree.asl
TEST=boot to OS with GBE enabled and check GBE interrupt
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I8084b30c668c155ebabbee90b5f70054813b328e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41153
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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pci_domain_set_resources is duplicated in all the SOCs. This change
promotes the duplicated function.
Picasso was adding it again in the northbridge patch. I decided to
promote the function instead of duplicating it.
BUG=b:147042464
TEST=Build and boot trembyle.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iba9661ac2c3a1803783d5aa32404143c9144aea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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IedSize and EnableC6Dram are removed in JSL FSP v2114 so
remove them from 'fsp_params.c'.
BUG=155054804
BRANCH=None
TEST=Build and boot JSLRVP
Change-Id: I47bd3f87bdb59625098c0d734695f02d738f8bbd
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41239
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch control SATA related UPDs based on the devicetree
configuration as per each board's requirement.
BUG=b:155595624
BRANCH=None
TEST=Build, boot JSLRVP, Verified UPD values from FSP log
Change-Id: I4f7e7508b8cd483508293ee3e7b760574d8f025f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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This change updates lpc_enable_children_resources() to configure IO
and MMIO resources differently depending upon whether the mainboard
wants to setup decode windows for LPC or eSPI.
BUG=b:154445472,b:153675913
Change-Id: Ie8803e934f39388aeb6e3cbd7157664cb357ab23
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This change provides a helper function espi_update_static_bar() that
informs the eSPI common driver about the static BAR to use for eSPI
controller instead of reading the SPIBASE. This is required to support
the case of verstage running on PSP.
BUG=b:153675913
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I1f11bb2e29ea0acd71ba6984e42573cfe914e5d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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FSP provides the UPD's for SATA and DMI power optimization.
In this patch we are adding the soc's config support to set
those power optimization bits in FSP. By default those
optimizations are enabled. To disable those we need to set
the DmiPwrOptimizeDisable and SataPwrOptimizeDisable to 1
in devicetree.
BUG=b:151162424
BRANCH=None
TEST=Build and boot volteer and TGL RVP.
Change-Id: Iefc5e7e48d69dccae43dc595dff2f824e53f5749
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This change adds the following helper functions for eSPI decode:
1. espi_open_io_window() - Open generic IO window decoded by eSPI
2. espi_open_mmio_window() - Open generic MMIO window decoded by eSPI
3. espi_configure_decodes() - Configures standard and generic I/O
windows using the espi configuration provided by mainboard in device tree.
BUG=b:153675913,b:154445472
Change-Id: Idb49ef0477280eb46ecad65131d4cd7357618941
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41073
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds eSPI register definitions for I/O and MMIO decode
using eSPI on AMD SoCs. Additionally, it also adds a macro to define
the offset of ESPI MMIO base from SPI MMIO base.
BUG=b:153675913
Change-Id: Ifb70ae0c63cc823334a1d851faf4dda6d1c1fc1a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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decodes
This change sets LPC_IO_PORT_DECODE_ENABLE to 0 as part of
lpc_disable_decodes() to ensure that the I/O port decodes are also disabled.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I1474f561997f2ee1231bd0fcaab4d4d4e98ff923
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change switches to using the common block SPI driver for
performing early SPI initialization and for re-configuring SPI speed
and mode after FSP-S has run.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ia3186ce59b66c2f44522a94fa52659b4942649b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This change adds support for using common SoC configuration by adding
soc_amd_common_config to soc_amd_picasso_config and helper function to
return pointer to the structure to amd common block code.
Change-Id: I8bd4eac3b19c9ded2d9a3e95ac077f014730f9d1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change adds support for following SPI configuration functions to
common block SPI driver and exposes them to be used by SoC:
1. fch_spi_early_init(): Sets up SPI ROM base, enables SPI ROM,
enables prefetching, disables 4dw burst mode and sets SPI speed and mode.
2. fch_spi_config_modes(): This allows SoC to configure SPI speed and
mode. It uses SPI settings from soc_amd_common_config to configure the
speed and mode.
These functions expect SoC to include soc_amd_common_config in SoC
chip config and mainboard to configure these settings in device tree.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ia4f231bab69e8450005dd6abe7a8e014d5eb7261
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41248
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We should not need that.
Change-Id: Ic0181a300670ed7ee999dafedac79f3f89bfbee9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner
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This change splits lpc_set_spibase() into two separate functions:
lpc_set_spibase() - Sets MMIO base address for SPI controller and eSPI
controller (if supported by platforms)
lpc_enable_spi_rom() - Enables SPI ROM
This split is done to allow setting of MMIO base independent of ROM
enable bits. On platforms like Picasso, eSPI base is determined by the
same register and hence eSPI can set the BAR without having to touch
the enable bits.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I3f270ba1745b4bb8a403f00cd069a02e21d444be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This change adds support for struct soc_amd_common_config that allows
multiple AMD SoCs to share common configuration. This can then be used
by common/block drivers to get the required configuration from device
tree. It also provides function declaration for
soc_get_common_config() that needs to be provided by SoCs making use
of the common configuration structure.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Idb0d797525414c99894a8e4ede65469381db7794
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41246
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support to configure the Silver and L3 PLLs and switch the APSS
GFMUX to use the PLL to speed up the boot cores.
Tested: CPU speed frequency validated for speed bump
Change-Id: Iafd3b618fb72e0e8cc8dd297e4a3e16b83550883
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Update memory regions, etc.
Change-Id: If852fe4465fb431809570be6cdccff3ad9d9f4f0
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39362
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
Change-Id: I63f35c94bc6c60934ace5fe0fd9176443059b354
Signed-off-by: Ashwin Kumar <ashk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36518
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Transfer sequence used by SPI-Flash application present in CB/DC.
1. Assert CS through GPIO
2. Data transfer through QSPI (involves construction of command
descriptor for multiple read/write transfers)
3. De-assert CS through GPIO.
With above sequence, in DMA mode we dont have the support for read
transfers that are not preceded by write transfer in QSPI controller.
Ex: "write read read read" sequence results in hang during DMA transfer,
where as "write read write read" sequence has no issue.
As we have application controlling CS through GPIO, we are making
fragment bit "set" for all transfers, which keeps CS in asserted
state although the ideal way to operate CS is through QSPI controller.
Change-Id: Ia45ab793ad05861b88e99a320b1ee9f10707def7
Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39807
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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