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2020-05-05soc/intel/jasperlake: Correct the EMMC PCR Port IDRonak Kanabar
Updating EMMC PCR PID from 0x52 to 0x51 for Jasperlake BUG=b:155595624 BRANCH=None TEST=Build, boot JSLRVP from emmc Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Change-Id: I17d4e7b7e0fe5e0b18867b6481b5bc9227ae19e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-05-05soc/intel/jasperlake: Allow SD card power enable polarity configurationRonak Kanabar
SdCardPowerEnableActiveHigh is a UPD which controls polarity of SD card power enable pin. Setting it 1 will set polarity of this pin as Active high. This patch will allow to control it from devicetree so that it can be set as per each board's requirement. BUG=b:155595624 BRANCH=None TEST=Build, boot JSLRVP, Verified UPD value from FSP log Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Change-Id: Id777a262651689952a217875e6606f67855fc2f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41027 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-05soc/intel/tigerlake: Add PMC mux controlJohn Zhao
PMC supports messages that can be used for configuring the USB Type-C Multiplexer/Demultiplexer. BUG=b:151646486 TEST=Booted to kernel on volteer board and verified PMC and Mux agent devices identification. Change-Id: I00c5f929b2eea5de3f8eba794dbe9b36c8083c52 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-05soc/amd/picasso: add Kconfig option to disable rom sharingAaron Durbin
Add a knob for mainboards to request disablement of the SPI flash ROM sharing in the chipset. The chipset allows the board to share the SPI flash bus and needs a pin to perform the request. If the board design does not employ SPI flash ROM sharing then it's imperative to ensure this option is selected, especially if the pin is being utilized by something else in the board design. BUG=b:153502861 Change-Id: I60ba852070dd218c4ac071b6c1cfcde2df8e5dce Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146445 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Aaron Durbin <adurbin@google.com> Tested-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-05soc/amd/common/block/lpc: Add lpc_disable_spi_rom_sharingRaul E Rangel
If a Picasso platform wants to use GPIO 67 it must disable ROM sharing. Otherwise ROM access is incredibly slow. BUG=b:153502861 TEST=Build trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia9ab3803a2f56f68c1164bd241fc3917a3ffcf2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-04soc/intel/tigerlake: Update interrupt settingWonkyu Kim
Update interrupt setting based on latest FSP(3163.01) Reference: https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/ ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/ PeiItssPolicyLibVer2.c BUG=b:155315876 BRANCH=none TEST=Build with new FSP(3163.01) and boot OS and login OS console in ripto/volteer. Without this change, we can't login due to mismatch interrupt setting between asl and fsp setting. Cq-Depend: chrome-internal:2944102 Cq-Depend: chrome-internal:2939733 Cq-Depend: chrome-internal:2943140 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ibf70974b8c4f63184d576be3edd290960b023b1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40872 Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04src/soc/tigerlake: Update SerialIoDebugMode UPD in FSP-MSrinidhi N Kaushik
Due to refactoring of Serial IO code in FSP v3163 onwards we need to set SerialIoUartDebugMode UPD in FSP-M to SkipInit so that SerialIoUart initialization is skipped in FSP. This makes sure that SerialIo initialization in coreboot is not changed by FSP. BUG=b:155315876 BRANCH=none TEST=build and boot tglrvp/ripto/volteer and check UART debug logs Cq-Depend: chrome-internal:2944102 Cq-Depend: chrome-internal:2939733 Cq-Depend: chrome-internal:2943140 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I8ba4b9015fa25a84b6b99419ce4d413c9d9daa44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40899 Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04soc/intel/skl: always enable SataPwrOptEnableMichael Niewöhner
For unknown reasons FSP skips a whole bunch of SIR (SATA Initialization Registers) when SataPwrOptEnable=0, which currently is the default in coreboot and FSP. Even if FSP's default was 1, coreboot would reset it. This can lead to all sorts of problems and errors, for example: - links get lost - only 1.5 or 3 Gbps instead of 6 Gbps - "unaligned write" errors in Linux - ... At least on two boards (supermicro/x11-lga1151-series/x11ssm-f and purism/librem13v2) SATA is not working correctly and showing such symptoms. To let FSP correctly initialize the SATA controller, enable the option SataPwrOptEnable statically. There is no valid reason to disable it, which might break SATA, anyway. Currently, there are no reported issues on CML and CNL, so a change there could not be tested reliably. SKL/KBL was tested successfully without any noticable downsides. Thus, only SKL gets changed for now. Change-Id: I8531ba9743453a3118b389565517eb769b5e7929 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40877 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04soc/intel/cannonlake: Add DisableHeciRetry to configChristian Walter
Add DisableHeciRetry to the chip config and parse it in romstage. Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-05-04soc/intel/common/block/cse: Add boot partition related APIsSridhar Siricilla
In CSE Firmware Custom SKU, CSE region is logically divided into 2 boot partitions. These boot partitions are represented by BP1(RO), BP2(RW). With CSE Firmware Custom SKU, CSE can boot from either RO(BP1) or RW(BP2). The CSE Firmware Custom SKU layout appears as below: ------------- -------------------- --------------------- |CSE REGION | => | RO | RW | DATA | => | BP1 | BP2 | DATA | ------------- -------------------- --------------------- In order to support CSE FW update to RW region, below APIs help coreboot to get info about the boot partitions, and allows coreboot to set CSE to boot from required boot partition (either RO(BP1) or RW(BP2)). GET_BOOT_PARTITION_INFO - Provides info on available partitions in the CSE region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets CSE's next boot partition to boot from. With the HECI API, firmware can notify CSE to boot from RO(BP1) or RW(BP2) on next boot. As system having CSE Firmware Custom SKU, boots from RO(BP1) after G3, so coreboot sets CSE to boot from RW(BP2) in normal mode and further, coreboot ensure CSE to boot from whichever is selected boot partition if system is in recovery mode. BUG=b:145809764 TEST=Verified on hatch Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-02soc/amd/picasso: Select CHROMEOS_RAMOOPS_DYNAMICFurquan Shaikh
For boards that select CHROMEOS, select CHROMEOS_RAMOOPS_DYNAMIC by default. BUG=b:155345589 Change-Id: Id215f3a2c8d1e9e713a628283af9586a1f117ef4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40949 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-01soc/amd/picasso: add sd/emmc0 configuration to chip.hAaron Durbin
In order to isolate mainboard code from direct FSPS manipulation allow sd/emmc0 configuration to be supplied by devicetree.cb. BUG=b:153502861 Change-Id: I2569ccccd638faaf2c9ac68fe582ecb9fa967d9f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146439 Commit-Queue: Aaron Durbin <adurbin@google.com> Tested-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-01soc/amd/picasso: Add FSP support for including AGESAMarshall Dawson
AMD has rewritten AGESA (now at v9) for direct inclusion into UEFI build environments. Therefore, unlike the previous Arch2008 (a.k.a. v5), it can't be built without additional source, e.g. by combining with EDK II, and it has no entry points for easily building it into a legacy BIOS. AGESA in coreboot now relies on the FSP 2.0 framework published by Intel and uses the existing fsp2_0 driver. * Add fsp_memory_init() to romstage.c. Although Picasso comes out of reset with DRAM alive, this call is added to maximize compatibility and facilitate internal development. Future work may look at removing it. AGESA reports the memory map to coreboot via HOBs returned from fsp_memory_init(). * AGESA currently sets up MTRRs, as in most older generations. Take ownership back immediately before running ramstage. * Remove cbmem initialization, as the FSP driver handles this. * Add chipset_handle_reset() for compatibility. * Top of memory is determined by the FSP driver checking the HOBs passed from AGESA. Note that relying on the TOM register happens to be misleading when UMA is below 4GB. BUG=b:147042464 TEST=Boot trembyle to payload Change-Id: Iecb3a3f2599a8ccbc168b1d26a0271f51b71dcf0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34423 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01src/soc/amd/picasso: Add methods to save and restore MTRRsRaul E Rangel
FSP AGESA overrides the MTRRs that coreboot set up. Until this is fixed we need to save and restore the MTRRs to undo what AGESA did. Once AGESA is fixed, we can delete these files. BUG=b:155426691, b:147042464 TEST=Boot trembyle and see MTRRs being modified Saving Variable MTRR 0: Base: 0x00000000 0xff000005, Mask: 0x0000ffff 0xff000800 Saving Variable MTRR 1: Base: 0x00000000 0x08070006, Mask: 0x0000ffff 0xffff0800 Saving Variable MTRR 2: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 3: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 4: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 5: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 6: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 7: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Fixed MTRR 0: 0x00000000 0x00000000 Saving Fixed MTRR 1: 0x00000000 0x00000000 Saving Fixed MTRR 2: 0x00000000 0x00000000 Saving Fixed MTRR 3: 0x00000000 0x00000000 Saving Fixed MTRR 4: 0x00000000 0x00000000 Saving Fixed MTRR 5: 0x00000000 0x00000000 Saving Fixed MTRR 6: 0x00000000 0x00000000 Saving Fixed MTRR 7: 0x00000000 0x00000000 Saving Fixed MTRR 8: 0x00000000 0x00000000 Saving Fixed MTRR 9: 0x00000000 0x00000000 Saving Fixed MTRR 10: 0x00000000 0x00000000 Saving Default Type MTRR: 0x00000000 0x00000800 Saving SYS_CFG: 0x00000000 0x00000800 ... MSR 0x200 was modified: 0x00000000 0x00000006 MSR 0x201 was modified: 0x0000ffff 0x80000800 MSR 0x202 was modified: 0x00000000 0x80000006 MSR 0x203 was modified: 0x0000ffff 0xc0000800 MSR 0x204 was modified: 0x00000000 0xc0000006 MSR 0x205 was modified: 0x0000ffff 0xf0000800 MSR 0x250 was modified: 0x06060606 0x06060606 MSR 0x258 was modified: 0x06060606 0x06060606 SYS_CFG was modified: 0x00000000 0x00740000 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6048b25bd8a32904031ca23953f9726754b5a294 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40922 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01soc/intel/xeon_sp/cpx: Implement hide/unhide P2SB traditional danceAndrey Petrov
Perform the P2SB hide/unhide trick. This is needed so that BAR0 (0xfd000000) is not reclaimed by resource allocator, since it can not deal with a device that does not exist (hidden). Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I5db0ae4e31d72ba86efba5728b2afc68d3180d5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/40921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-05-01soc/intel/xeon_sp/cpx: Enable common P2SBAndrey Petrov
Use common P2SB driver. This is needed to address a problem when enumerator does not see p2sb device (since it is hidden) but it is active and BAR is decoded. Change-Id: I9cb821a5684f15f1e1486872bf806a6ee3d0676f Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40920 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01soc/intel/xeon_sp: Add C620 p2sb.hAndrey Petrov
Add p2sb.h that is shared by all currently supported Xeon SP CPUs. Change-Id: Idcbff7ad587cb116897a953c079fb0a8b86cc2ed Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40919 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01xeon_sp, ocp/tiogapass: remove unused FSP-style GPIO defsMaxim Polyakov
Change-Id: I8599dca99c1f34e3937c5b77b3505815ce625b46 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I9b15b5458bb8140fa9bb6b0ffb6b9c78e8d8a93b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I353daf35c843521b089ff8411a9ba8c801605ff9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01soc/intel/braswell: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: Ie213b8c08e2d2b33a1dc1fda632163160d1cd70e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01soc/intel/cannonlake: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: If7e2c84c39039e0dc6811f247390f856fc634b33 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01soc/intel/common: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I09cc69a20dc67c0f48b35bfd2afeaba9e2ee5064 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01soc/intel/broadwell: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I0fd1a758d8838b3eea5640b41eee6a6893360aa3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01soc/amd/picasso: initialize i2c controllers in SoC flowAaron Durbin
BUG=b:153642124 TEST=Saw I2C communication Change-Id: I31f8b97d1ff7b687d7e078d5b594d1ad73c815e7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145457 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-01soc/amd/picasso/bootblock: Remove duplicate sb_reset_i2c_slavesRaul E Rangel
sb_reset_i2c_slaves is called in fch_pre_init. BUG=b:153675916 TEST=Builds on trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I157e473984257d633ceb3ef9df45c71a31c5c00b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-01soc/amd/picasso/bootblock/bootblock: Remove duplicate i2c initRaul E Rangel
fch_early_init already calls i2c_soc_early_init(). BUG=b:153675916 TEST=Boot trembyle and only see 1 i2c initialization message Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I689616fb617904df1781be3abe9d1dc580608173 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-01soc/amd/picasso: Allow mainboard to provide pci ddi descriptorsAaron Durbin
Mainboards must provide their DDI descriptors. BUG=b:153502861 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146443 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146439 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146438 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145453 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145454 Change-Id: Ib3f115711e74d0e6eb5b063b3dccb36b265779af Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40875 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better ↵Subrata Banik
understanding BIT 1 -> DEBUG_INTERFACE_UART_8250IO BIT 4 -> DEBUG_INTERFACE_LPSS_SERIAL_IO Change-Id: I566b9dc82b2289af42e58705ebeee51179886f1f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-01soc/intel/jasperlake: fix args of dimm_info_fill() for dram_part_numMarco Chen
BUG=b:152019429 BRANCH=None TEST=1. provision dram_part_num field of CBI 2. modify mainboard - dedede to report DRAM part number from CBI 3. check DRAM part number is correct in SMBIOS for memory device Change-Id: I509d06a81bd005c5afe6e74a2da2ca408dee7b29 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01soc/intel/cannonlake/bootblock: Fix FSP CARPatrick Rudolph
Fix FSP CAR on platforms that have ROM_SIZE of 32MiB. CodeRegionSize must be smaller than or equal to 16MiB to not overlap with LAPIC or the CAR area at 0xfef00000. Tested on Intel CFL, the new code allows to boot using FSP-T. Change-Id: I4dfee230c3cc883fad0cb92977c8f5570e1a927c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01soc/amd/common/block/graphics/graphics: Add missing const to fill_ssdtRaul E Rangel
BUG=none TEST=Made sure trembyle builds Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9df70fd5c41a9a68edc7be3c2e920c4dc94d5af9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40871 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01soc/amd/picasso: Enable cache in bootblockFelix Held
Unlike prior AMD devices, picasso cannot rely on the cache-as-RAM setup code to properly enable MTRRs. Add that capability to the bootblock_c_entry() function. In addition, enable an MTRR to cache (WP) the flash boot device and another for WB of the non-XIP bootblock running in DRAM. BUG=b:147042464 TEST=Boot trembyle to payload and make sure bootblock isn't abnormally slow. Change-Id: I5615ff60ca196e622a939b46276a4a0940076ebe Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38691 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetreeMeera Ravindranath
This CL adds support to fill PcieRpClkReqDetect UPD from devicetree. Filling this UPD will allow FSP to enable proper clksrc gpio configuration. BUG=None BRANCH=None TEST=Build and boot tglrvp. Change-Id: Iad0ba94fea019623a5b98fff0cb4a2cd1d2a7bd7 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-05-01soc/amd/stoneyridge: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I7b39e895501c3bc672a9dffec06b7969dc2f911f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-05-01soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetreeMeera Ravindranath
This CL adds support to fill PcieRpClkReqDetect UPD from devicetree. Filling this UPD will allow FSP to enable proper clksrc gpio configuration. BUG=None BRANCH=None TEST=Build and boot jslrvp with NVMe Change-Id: Iad0b394fea019223a5b98fff0cb4a2bd1d2a7bd7 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-05-01src: Remove not used 'include <smbios.h>'Elyes HAOUAS
Change-Id: I12345a5b6c9ce94ca9f8b555154b2278a8ff97bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01src: Remove unused 'include <cpu/x86/cache.h>'Elyes HAOUAS
Change-Id: I2bf1eb87bb5476dd77b5a56dfe8846e82d414523 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40666 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01soc/intel/jasperlake: Add support to generate ACPI GPIO operationsKarthikeyan Ramasubramanian
Add support to generate ACPI operations to get/set/clear RX/TX GPIOs. BUG=b:152936541 TEST=Build and boot the mainboard. Ensure that there are no errors in the coreboot logs regarding unsupported ACPI GPIO operations. Change-Id: Ibc4846fbd9baf4f22c48c82acefed960669ed7d4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-30soc/amd/picasso: Add support for em100Furquan Shaikh
This change enables support for em100 for Picasso platform. Since em100 requires lower SPI speed, this change configures speed in all modes as 16MHz. BUG=b:147758054,b:153675510 BRANCH=trembyle-bringup TEST=Verified that em100 works fine on trembyle. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib5ea1fe094fda9b8dba63e94b37e61791629564f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40825 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30soc/amd/picasso: Allow mainboard to configure SPI settingsFurquan Shaikh
This change adds options to allow mainboard to configure SPI speed for different modes as well as the SPI read mode. BUG=b:153675510,b:147758054 BRANCH=trembyle-bringup TEST=Verified that SPI settings are configured correctly for trembyle. Change-Id: I24c27ec39101c7c07bedc27056f690cf2cc54951 Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Rob Barnes <robbarnes@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40421 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30soc/amd/picasso: Move SPI init calls into sb_spi_init()Furquan Shaikh
This change adds a helper sb_spi_init() that makes all the required calls for configuring SPI to ROM. BUG=b:147758054,b:153675510 BRANCH=trembyle-bringup TEST=Verified that SPI configuration is correct for trembyle. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ic5b395a8d3bdab449c24b05d1b6b8777e128b5e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40824 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30soc/amd/picasso: Introduce enums for SPI read mode and speedFurquan Shaikh
This change adds enums for spi_read_mode and spi100_speed in preparation for adding these to chip.h in follow-up CLs. This makes it easier to reference what the mainboard is expected to set for these SPI configs. BUG=b:147758054,b:153675510 BRANCH=trembyle-bringup TEST=Verified that SPI configuration is correct for trembyle. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I7f9778b41bd059a50f20993415ebd8702a1ad58e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40823 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30soc/amd/picasso: Get rid of chip.h inclusion from southbridge.hFurquan Shaikh
southbridge.h does not really need chip.h. So, this change removes the inclusion of chip.h from it. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I09c87b975ecd5f7798da8dd858be0c729aef42de Reviewed-on: https://review.coreboot.org/c/coreboot/+/40822 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30soc/amd/common/block/smbus: Include acpimmio_map.h in sm.cFurquan Shaikh
sm.c requires acpimmio_map.h for ACPIMMIO_* macros. This change includes acpimmio_map.h in sm.c Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ia049254fa389a76bcf6538c0449229b4d856086e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40821 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30Revert "soc/mediatek/mt8183: Force retraining memory if requested"Julius Werner
This reverts commit 285975dbba8c7f3bbb9f9950e79a30bb983d5123. Reason for revert: VB2_RECOVERY_TRAIN_AND_REBOOT was never meant to have any special effect on memory training behavior. It was just supposed to be a "reboot automatically after reaching kernel verification" recovery reason. On x86 devices this was used to prime the separate recovery MRC cache in the factory (make sure it is initialized before shipping). This isn't used on Kukui anyway, but in order to make sure nobody copies this code and keep the behavior consistent between platforms, let's remove it. Change-Id: I5df5e00526e90cb573131de3c8bac9f85f4e3a5f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40623 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30sc7180: Increase SPI flash frequency to 37.5MHzJulius Werner
It seems that all SC7180 boards we have can well handle 37.5MHz of SPI flash speed, so bump that up from the current 25MHz so that we don't leave boot speed on the table. (The next step would be 50MHz which currently doesn't work on all boards so we're not going there yet.) BUG=b:117440651 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Id6e98fcbc89f5f3bfa408c7e8bbc90b4c92ceeea Reviewed-on: https://review.coreboot.org/c/coreboot/+/40874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-04-29soc/intel/tigerlake: Check SPD is not NULL before printEric Lai
Check SPD is not NULL before print. This can prevent the system from hanging up. BUG=b:154445630 TEST=Check NULL SPD is not print. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Iccd9fce99eda7ae2b8fb1b4f3c2e635c2a428f04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40560 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Enable secure debug unlock conditionallyFurquan Shaikh
This change adds a Kconfig option PSP_UNLOCK_SECURE_DEBUG which when enabled includes secure debug unlock blobs and sets the required softfuses and options for amdfwtool. By default this is set to 'N'. BUG=b:154880818 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I47d8af67989b06242d662c77b7d9db97f624edd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-04-29soc/amd/picasso: Use a helper to set bits in PSP_SOFTFUSEFurquan Shaikh
This change updates Makefile.inc to use a helper function set-bit to set a bit for the soft fuses. It gets rid of the different checks that were done to set soft fuses to magic values in different places. This is still not the best way to handle the fuses and instead this logic should be embedded within the amdfwtool by making it aware of specific platforms. But until that happens, we want to avoid having to add PSP_SOFTFUSE setting in various places with different values. BUG=b:154880818 TEST=Verified that the softfuse values are same with and without this change. Change-Id: I73887eb9c56ca5bb1c08d298fa818d698da1080b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40700 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Drop prompts from some Kconfig optionsFurquan Shaikh
Some of the PSP Kconfig options that are prompted to the user should really be selected by mainboard. This change updates such options to not make them user-visible any more. BUG=b:154880818 Change-Id: Iaff02fb1e720e0562b740799593322e59b022212 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-29soc/amd/picasso: Fix comment about SMU firmware2 typeFurquan Shaikh
SMU firmware2 has type 0x12 i.e. decimal 18 and not 0x18. This change updates the comment for SMU firmware2 type. Change-Id: Ia2e35aff3e460a3423f90d6ecdbe2362331391f3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-04-29soc/amd/picasso: Drop addition of PSPTRUSTLETS_FILEFurquan Shaikh
PSPTRUSTLETS_FILE was including a binary for fTPM which according to BIOS architecture design guide is the firmware enabled TPM. Chrome OS does not really use firmware enabled TPM. Also, this is an option which is mainboard dependent. This change drops the addition of PSPTRUSTLETS_FILE to PSP directory. If this is something that is required by any mainboard, there should be a separate Kconfig to include the required files. BUG=b:154880818 TEST=Verified that trembyle still boots Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Iaa2126c879986d00c921c85fb5cb5257c7065006 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-04-29soc/amd/picasso: Drop unused OPT_PSPNVRAM_FILEFurquan Shaikh
This change drops unused option OPT_PSPNVRAM_FILE from picasso Makefile. BUG=b:154880818 TEST=Verified that trembyle still boots to OS. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I64b328a92f5ee76e198a2ad3ec72d2cc4aeb9e91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40684 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Drop addition of PUBSIGNEDKEY_FILEFurquan Shaikh
This change drops the addition of PUBSIGNEDKEY_FILE to PSP directory. This file is used to add OEM key for BIOS, however this is currently unused for upcoming zork board. In the future, if any mainboard needs this, it can be added based on some Kconfig selection. BUG=b:154880818 TEST=Verified that trembyle still boots up fine. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Icd97856a94a100898678702d99bbe29b82956004 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40682 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Disable inclusion of S0i3 firmware by defaultFurquan Shaikh
Enabling of S0i3 is a mainboard decision. This change sets the option to include S0i3 firmware by default to 'n'. BUG=b:154880818 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I5d533e317535b01efe9dd32272483296bf4fafab Reviewed-on: https://review.coreboot.org/c/coreboot/+/40681 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Disable MP2 FW inclusion by defaultFurquan Shaikh
Inclusion of MP2 firmware is optional and dependent on mainboard. Set default option for including MP2 firmware in PSP directory to 'n'. BUG=b:154880818 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I1ff7527a409d8ac7f4d30e69eafc53975b63e49b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-04-29soc/amd/hda: Move HDA PCI device from DSDT to SSDTFurquan Shaikh
This change adds support in common block HDA driver to add a PCI device for HDA in SSDT and removes the HDA device from DSDT for Stoneyridge and Picasso. _INI method is still retained in stoneyridge since I am unsure why it was added. In order to support the _INI method, HDA driver makes a callback hda_soc_ssdt_quirks() to allow SoCs to add any quirks required for the HDA device. This callback is implemented by Stoneyridge to provide the _INI method which retains the same functionality for HDA device. This makes it easier to ensure that we don't accidentally make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and scope. BUG=b:153858769,b:155132752 TEST=Verified that audio still works fine on Trembyle. Change-Id: I89dc46b92fdcb785bd37e18f0456935c0e57eff5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40785 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Drop _INI method and OperationRegion for AZHD deviceFurquan Shaikh
_INI method for AZHD device for Picasso family was just copied from Stoneyridge as part of initial change. There is no evidence that this is required for Picasso. Also, removing the _INI method works perfectly fine. Thus, this change drops the _INI method for AZHD device on Picasso. Since the _INI method was the only entity using the OperationRegion fields, this change also drops the operation region. BUG=b:155132752 TEST=Verified that audio still works on Trembyle Change-Id: If42abf91ee5cd47a881b0a3b4ca1916ea5169261 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40782 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/hda: Add .acpi_name() callback to HDA driverFurquan Shaikh
This change adds .acpi_name() callback to HDA driver that returns "AZHD" as the ACPI device name for HDA controller. Since this is now done by the common HDA driver, this change also removes the HDA device name returned by stoneyridge in chip.c. BUG=b:153858769 Change-Id: I89eaa799518572f3c46c7ce9ef8dd3f85daa12bb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40781 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/common/block/hda: Use tabs instead of spaces in hda.cFurquan Shaikh
This is a cosmetic change to use tabs to align hda_audio_ops and hdaaudio_driver entries. Change-Id: I8e398706cbe7087d0178b2433606f8984651c0d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40780 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/common/block/hda: Use default pci_dev_ops_pciFurquan Shaikh
This change sets ops_pci for hda_audio_ops to default pci_dev_ops_pci and removes the custom lops_pci since the driver does not really need a custom ops_pci. BUG=b:153858769 Change-Id: I4b46e22ef556c0f49152c41a07f3c54c513ae37a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40779 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/common/block/hda: Drop PCI_DEVICE_ID_AMD_FAM17H_HDA0Furquan Shaikh
PCI device PCI_DEVICE_ID_AMD_FAM17H_HDA0 does not really use the same vendor ID as PCI_VENDOR_ID_AMD. Thus, drop this device from the list of pci_device_ids[] that are supported by the common hda driver. BUG=b:153858769 Change-Id: If41dc7179e1e5b476878ee24c8a355b1cde762eb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40778 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Add bootblock supportFelix Held
The original plan for Picasso was to combine the features of bootblock with romstage due to its unique way of coming out of reset. Early in development, all bootblock support was removed from the directory. All Picasso designs will now use a bootblock as their first stage. The reason being that it requires less invasive changes than using a hybrid romstage. Add a basic bootblock back to the directory, and compatible with the design of lib/bootblock.c. The files support RESET_VECTOR_IN_RAM and add appropriate settings in Kconfig. Make Makefile.inc calculates the size and base of bootblock from known parameters. * Future work may attempt to streamline this further, in conjunction with changes in amdfwtool. See b/154957411. BUG=b:147042464, b:153675909 Change-Id: I1d0784025f2b39f140b16f37726d4a7f36df6c6c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37490 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/intel/tigerlake: Add method to look up GPIO com ID for an indexVenkata Krishna Nimmagadda
This patch adds GPID, a helper method to look up GPIO community ID for an index. This patch also includes Intel's common GPIO ASL code. CGPM method in the common code uses the GPID method introduced in this patch. BUG=b:148892882 BRANCH=none TEST="BUILD volteer and ripto" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Id6a00fb8adef0285d6bbc35cd5a44539bd3be6b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40478 Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/intel/common: Add method to modify GPIO community PM configVenkata Krishna Nimmagadda
This patch adds CGPM, a helper method to configure GPIO power management bits that are part of miscellaneous config. This is needed for configuration of these bits on S0ix entry and exit. BUG=b:148892882 BRANCH=none TEST="BUILD volteer and ripto" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Iac3a269d3071eb5d4100d516249eeb5ce23c02fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/40260 Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/common/block/sata: Add missing .ops_pci memberFurquan Shaikh
This change sets .ops_pci for sata device_operations to default pci_dev_ops_pci. It is required to set the subsystem IDs making the behavior consistent with default_pci_ops_dev. BUG=b:153858769 Change-Id: I695ac8961c92a3061beca890f5d47413b251e22b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40777 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/picasso: Use AMD common SATA driverFurquan Shaikh
This change enables the use of AMD common block SATA driver for Picasso. Since the common driver provides ACPI device name and PCI device for SATA in SSDT, these are removed from picasso chip.c and sb_pci0_fch.asl. BUG=b:153858769 TEST=Verified that "STCR" device is correctly reported on trembyle in SSDT. Change-Id: Icfdcf9f5e08820b565aa9fcdd0cdc7b5c9eadcd5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40770 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/sata: Move SATA PCI device from DSDT to SSDTFurquan Shaikh
This change adds support in common block SATA driver to add a PCI device for SATA in SSDT and removes the SATA device from DSDT. This makes it easier to ensure that we don't accidentally make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and scope. BUG=b:153858769 Change-Id: I16ac36d997496ff33c5b44ec9bd2731b2b8799eb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40769 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/sata: Add .acpi_name() callback to SATA driverFurquan Shaikh
This change adds .acpi_name() callback to SATA driver that returns "STCR" as the ACPI device name for SATA. Since this is now done by the common SATA driver, this change also removes the SATA device name returned by stoneyridge in chip.c. BUG=b:153858769 Change-Id: I5e0998be3016febbb3b0e91940750a38edb6a9e7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40768 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/common/block/sata: Use tabs instead of spaces in sata.cFurquan Shaikh
This is a cosmetic change to use tabs to align sata_ops and sata0_driver entries. Change-Id: Ia9eabd0cd64ecc9cbff0d4c3e3c6b71bbf29e3a9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40767 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/common/block/sata: Fix the condition to include sata.cFurquan Shaikh
sata.c was being added to ramstage based on the selection of CONFIG_SOC_AMD_COMMON_BLOCK_HDA which is not correct. This change fixes the error by including sata.c based on selection of CONFIG_SOC_AMD_COMMON_BLOCK_SATA. BUG=b:153858769 Change-Id: I5d23e5817872ddbb3d8d4f7dcabbaafcee4d51f4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40766 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/picasso: Add UPD settings to chip.hMarshall Dawson
Add values that align with UPD settings. BUG=b:153675909 TEST=Trembyle builds and boots to payload Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I6bce44a43e57ba00d2b29cfa6249cef51e9ceabb Reviewed-on: https://review.coreboot.org/c/coreboot/+/38699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-28soc/intel/tigerlake: fix call to print_spd_info()Nick Vaccaro
Pointer passed to print_spd_info() from meminit.c needs to be dereferenced first, so this change dereferences it. BUG=b:154352883 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, login to kernel and execute the following cbmem command: localhost ~ # cbmem -c | grep LPDDR4X and verify it returns "SPD: module type is LPDDR4X" Change-Id: I5ff64121f0d50947c4946e9e02460dfb7319d01a Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-04-28device: Constify struct device * parameter to acpi_inject_dsdtFurquan Shaikh
.acpi_inject_dsdt() does not need to modify the device structure. Hence, this change makes the struct device * parameter to acpi_inject_dsdt as const. Change-Id: I3b096d9a5a9d649193e32ea686d5de9f78124997 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40711 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to acpi_fill_ssdt()Furquan Shaikh
.acpi_fill_ssdt() does not need to modify the device structure. This change makes the struct device * parameter to acpi_fill_ssdt() as const. Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/intel: Constify struct device * parameter to intel_igd_get_controller_infoFurquan Shaikh
intel_igd_get_controller_info() does not need to modify the device structure. Hence, this change makes the struct device * parameter to intel_igd_get_controller_info() as const. Change-Id: Ic044a80e3e2c45af6824a23f3cd0b08b94c0f279 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-28soc/intel: Constify struct device *param to sd_fill_soc_gpio_infoFurquan Shaikh
sd_fill_soc_gpio_info() does not need to modify device structure. Hence, this change makes the struct device * parameter to this function as const. Change-Id: I237ee9640ec64061aa9ed7c65ea21740c40b6ae2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-28i2c/designware: Constify struct device * parameter to dw_i2c_soc_dev_to_busFurquan Shaikh
dw_i2c_soc_dev_to_bus() does not need to modify the device structure. Thus, this change makes the struct device * parameter to dw_i2c_soc_dev_to_bus as const. Change-Id: Ibf5c8d8127dff2ab2ccbd1f6b4f553e98e81955f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40704 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to write_acpi_tablesFurquan Shaikh
.write_acpi_tables() should not be updating the device structure. This change makes the struct device * argument to it as const. Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28soc/amd/{common,picasso}: Move GFX device from static ASL to SSDTFurquan Shaikh
This change: 1. Adds PCI device for graphics controller in ACPI SSDT tables using acpi_device_write_pci_dev(). 2. Gets rid of IGFX device from picasso acpi/northbridge.asl. This makes it easier to ensure that we don't accidentally make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and scope. BUG=b:153858769 Change-Id: I3a967cdc43b74f786e645d3fb666506070851a99 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-28soc/amd/picasso: Use common block graphics driverFurquan Shaikh
This change selects common block graphics driver for Picasso and also adds PCI ID for Family 17h graphics controller to the graphics driver. Since the common driver provides .acpi_name() callback for graphics device, soc_acpi_name() no longer needs to provide the ACPI name for graphics device. BUG=b:153858769 Change-Id: Id3ffcb05d8f8a253a0b27407d52d7907c507cabb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-28soc/amd/common: Add a common graphics block device driver for AMD SoCsFurquan Shaikh
This change adds a common graphics block device driver for AMD SoCs. In follow-up CLs, this driver will be utilized for Picasso. This driver is added to enable ACPI name and SSDT generation for graphics controller. BUG=b:153858769 Change-Id: I45e2b98fede41e49158d9ff9f93785a34c392c22 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28amd/family17h: Add PCI device IDs for all controllers in AMD Family17hFurquan Shaikh
This change adds all the missing PCI device IDs for AMD Family 17h. IDs that were already present are updated to include _FAM17H_ in the name instead of _PCO_ and _DALI_. This ensures that the PCI IDs match the family and models as per the PPR. In cases where the controller is present only on certain models, _MODEL##H_ is also included in the name. BUG=b:153858769 BRANCH=None TEST=Verified that trembyle and dalboz still build. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ia767d32ec22f5e58827e7531c0d3d3bac90d3425 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28soc/amd: Update macro name for IOMMU on AMD Family 17hFurquan Shaikh
IOMMU for AMD Family 17h Model 10-20h uses the same PCI device ID 0x15D1. This change updates the name to indicate that the PCI device ID is supported for FP5(Model 18h) and FT5(Model 20h). BUG=b:153858769 BRANCH=None TEST=Trembyle and dalboz still build. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I17c782000ed525075a3e438ed820a22d9af61a26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28soc/intel/common/block/smbus: Set SPD array NULL if no DIMM presentEric Lai
Set SPD array NULL if no DIMM present. do_smbus_read_byte returns negative value if SMBus transaction fails. BUG=b:154445630,b:151702387 TEST=Check SPD is NULL if no DIMM in the slot. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie81adbfab5bb1d5c557fe549a158cb68e26b1162 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-28soc/intel/cannonlake: Report driver strength by _DSM in eMMC ACPI deviceKane Chen
According to doc 621880, it suggests setting 40 ohm in byte 185 in extCSD. This commit provides _DSM method for driver to query driving strength. TEST=mmc extcsd read |grep HS_TIMING and found bit[7:4] is set to 4 BUG=b:154159888 Signed-off-by: Kane Chen <kane.chen@intel.com> Change-Id: I1b4df8b0d1d2cad3a7f521ad47ee5a4b3320c767 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-28soc/intel/cometlake: Add ucode from repoFelix Singer
On Comet Lake, add the following microcode updates from the 3rdparty repository: - 06-8e-0c (CPUID signature: 0x806ec) - 06-a6-00 (CPUID signature: 0xa0660) Tested with Clevo N141CU. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Id10b013df8ce98a4e9830782570e20fbcfad05c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-04-28soc/intel/jasperlake: Add new MCH device idsMaulik V Vaghela
Add new MCH device-ids for jasperlake. Reference is taken from jasperlake EDS volume 1 chapter 13.3. BUG=None BRANCH=None TEST=code compiles and able to boot the platform. Change-Id: I38e09579c9a3681e9168c66085cbb3a092dc30cc Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-04-28soc/baytrail/raminit: Populate SMBIOS type 17 tablesMatt DeVillier
Populate SMBIOS type 17 tables using data from SPD and read via IOSF. Refactor print_dram_info() to pass thru SPD data and channel/speed info. Move call to print_dram_info() after cbmem initialization so the SMBIOS data has somewhere to go. Test: build/boot google/swanky, verify via dmidecode. Change-Id: I1c12b539c78d095713421b93115a4095f3d4278d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-26soc/intel/apollolake: Avoid CONFIG_PCIEX_LENGTH_256MB selectionSubrata Banik
This patch removes APL SoC selecting CONFIG_PCIEX_LENGTH_256MB Kconfig as default configuration for CONFIG_SA_PCIEX_LENGTH_MIB is 256MB. TEST=Able to build and boot APL platform. Change-Id: I61249f0adff5e03c07a568556e1ff76b27c6d368 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40378 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-25soc/intel/tigerlake: Fix FSP SPD index for DDR4Furquan Shaikh
For DDR4, FSP expects channel 0 to set SPD for index 0 and channel 1 to set SPD for index 4. This change adds a helper macro to translate DDR4 channel # to the index # that the FSP expects. BUG=b:154445630 TEST=Verified that memory initialization for DDR4 is successful. Change-Id: I2b6ea2433453a574970c1c33ff629fd54ff5d508 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-24soc/intel/xeon_sp/cpx: Calculate number of threads based on socketsAndrey Petrov
Assuming given system is populated with multiple CPUs of same SKUs, calculate number of threads based on MAX_SOCKET. This is a stop gap solution until proper way of identifying total number of sockets is determined. Change-Id: I7ebad3d57c47b9eeb7d727ffb21bc0a1a84734fd Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-04-24soc/intel/xeon_sp/cpx: Bump MAX_CPUSAndrey Petrov
Some dual-socket socket systems offer over 100 threads available. Other multi-socket configurations potentially offer even greater numbers of CPUs (over 9000!). Bump MAX_CPUS to 255. Change-Id: I50a181b89f40777a9f7b3881280c7bacf1b947cb Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-24soc/intel/xeon_sp/cpx: Work around FSP-M issuesAndrey Petrov
Currently FSP-M does not implement the spec completely, e.g it is unable to use user-provided heap location in CAR. While this is being resolved, this workaround is a stop-gap solution that allows multi-socket usage. TEST=tested on OCP Sonora Pass EVT and Intel Cedar Island CRB Change-Id: Ia2529526a8724cf54377b0bd2339b04fa900815a Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40555 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-24soc/intel/xeon_sp/cpx: Allow motherboards to set FSP-M parametersAndrey Petrov
We need to allow motherboards to configure certain parameters that are specific to it. Hence, invoke this function. Also, provide a weak motherboard implementation that does nothing. Change-Id: Ifa2824811273236a66e742404856fbe17d4cf496 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40552 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-24soc/amd/picasso/i2c: don't initialize I2C4 as master and refactor codeMartin Roth
I2C0&1 are either not available or not functional. Add place holders instead, so that the array index matches the I2C controller number. I2C4 is slave device only, so do not initialize it as I2C host controller. Also do some slight refactoring. BUG=b:153152871 BUG=b:153675916 Change-Id: I397b074ef9c14bf6a4f6680696582f5173a5d0d3 Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1897071 Reviewed-on: https://chromium-review.googlesource.com/2057468 Reviewed-on: https://chromium-review.googlesource.com/2094855 Reviewed-on: https://chromium-review.googlesource.com/2149870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40247 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-24soc/intel/tigerlake: Add ACPI GPIO opAlex Levin
Add acpigen methods which generate operations to get/set/clear RX/TX GPIOs. Verify it matches https://doc.coreboot.org/acpi/gpio.html. BUG=b:149588766 TEST=confirmed with touchscreen gpios. Signed-off-by: Alex Levin <levinale@chromium.org> Change-Id: Id9fe26f14a606ceedb9db02d76fe8d466d3a21af Reviewed-on: https://review.coreboot.org/c/coreboot/+/40550 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jes Klinke <jbk@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-23rules.h: Rename ENV_VERSTAGE to ENV_SEPARATE_VERSTAGEJulius Werner
When CONFIG_SEPARATE_VERSTAGE=n, all verstage code gets linked into the appropriate calling stage (bootblock or romstage). This means that ENV_VERSTAGE is actually 0, and instead ENV_BOOTBLOCK or ENV_ROMSTAGE are 1. This keeps tripping up people who are just trying to write a simple "are we in verstage (i.e. wherever the vboot init logic runs)" check, e.g. for TPM init functions which may run in "verstage" or ramstage depending on whether vboot is enabled. Those checks will not work as intended for CONFIG_SEPARATE_VERSTAGE=n. This patch renames ENV_VERSTAGE to ENV_SEPARATE_VERSTAGE to try to clarify that this macro can really only be used to check whether code is running in a *separate* verstage, and clue people in that they may need to cover the linked-in verstage case as well. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I2ff3a3c3513b3db44b3cff3d93398330cd3632ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/40582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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