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2024-03-23soc/amd/genoa_poc/domain: refactor read_soc_memmap_resourcesFelix Held
To bring genoa_poc more in line with the other AMD SoCs, move the reporting of the memory map up to cbmem_top from the openSIL-specific add_opensil_memmap function to read_soc_memmap_resources. This is a preparation for making this code common for all newer AMD SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic06282baa3bb9a65d297b5717697a12d08605d2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/81388 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-23src: Add missing SPDX license headersNicholas Chin
Other files in the commits that added these files were licensed under GPL-2.0-only, and the project as a whole is GPL-2.0-only, so use that as the license. Change-Id: I6c1a7ba582f61f98069ebf3857a8b5bdc8588c3e Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81421 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22arch/riscv: add Kconfig variable RISCV_SOC_HAS_MENVCFGRonald G Minnich
Older parts do not have the menvcfg csr. Provide a Kconfig variable, default y, to enable it. Check the variable in the payload code, when coreboot SBI is used, and print out if it is enabled. The SiFive FU540 and FU740 do not support this register; set the variable to n for those parts. Add constants for this new CSR. Change-Id: I6ea302a5acd98f6941bf314da89dd003ab20b596 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81425 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-22vc/amd/opensil/genoa_poc/mpio: move PCIe port function below mpio chipFelix Held
Move the gpp_bridge_* device functions that are bridges to the external PCIe ports below the corresponding mpio chip. This avoids the need for dummy devices and does things in a slightly more coreboot-native way. TEST=PCIe lane config reported by openSIL is identical Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: I7e39bf68d30d7d00b16f943953e8207d6fe9ef41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81340 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22soc/intel/xeon_sp: Include soc_util.h in Xeon-SP common codesShuo Liu
Different SoC generations might have different FSP header files. It is recommended to put these uncommon header files in soc_util.h so that Xeon-SP codes refer to soc_util.h to include them in a clean way. TEST=intel/archercity CRB Change-Id: Icfc20921efe00bc69b0c16c665f65f5baae4c309 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81229 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22soc/intel/alderlake: select UDK_202111_BINDING for ADL-NRonak Kanabar
ADL-N FSP uses 202111 Edk2. select UDK_202111_BINDING Kconfig for ADL-N SoC. BUG=b:296433836 TEST=Able to build and boot google/crassk. Change-Id: If277ede4307515035389cd0e9d34c15cc80f278c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80274 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-21soc/intel/adl: Guard TWL SoC missing UPDs for build integritySubrata Banik
Adds config-based guards for Usb4CmMode and CnviWifiCore UPDs, specific to Twin Lake SoCs (SOC_INTEL_TWINLAKE). Prevents compilation errors due to missing UPD definitions. BUG=b:330654700 TEST=Able to build google/tivviks. Change-Id: I6e0a9a7536df6295e23bf06003539e56bb98a311 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81376 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-20soc/intel/elkhartlake/Kconfig: Rename FSPRel.bin to FSP.fdMario Scheithauer
With the last FSP submodule update for Elkhart Lake commit f8df905e7baf ("3rdparty/fsp: Update submodule to upstream master"), the binary name was changed to FSP.fd. Change-Id: Ibc87ea2744e971d58e9a402f7cf04ef3f316f3b8 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-19soc/intel/xeon_sp: Drop RMRR entry for USBPatrick Rudolph
Drop RMRR entry for XHCI controller since it's not under BIOS control. There's no USB-PS/2 emulation done in SMM, hence it's not needed. TEST=intel/archercity CRB Change-Id: I5afd68371d71a00988fe0f8a6045ec5ce2adc6a1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81297 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-19soc/intel/xeon_sp: Drop uncore_fill_ssdtPatrick Rudolph
Let ACPI DSDT figure out by itself if a stack is enabled. Allows to drop uncore_fill_ssdt() on all platforms. TEST=intel/archercity CRB Change-Id: Ib9051d608147f2de228509ff6b13871ca3183979 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81273 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-19soc/intel/xeon_sp/spr: Enable 512 MMCONF buses by defaultPatrick Rudolph
As of now coreboot only supported one PCI segment group and thus the MMCONF size had to be limited to 256 buses on ibm/sbp1. Since the default FSP doesn't allow to disable unused IIO stacks a patched version had to be used. Those unused IIO stacks consume lots of PCI bus ranges, leaving no free buses for the secondary side behind PCI bridges. The IIO disable mechanism doesn't work after ACPI G3 exit and thus requires multiple reboots when the previous state was G3. Since coreboot now supports multi PCI segment groups enable 512 MMCONF buses on 4S platforms by default and drop the IIO stack disable UPDs on ibm/sbp1. This allows to boot faster without the need for a patched FSP. The use of multiple PCI segment groups might prevent legacy software from working properly, however the only board where multiple PCI segment groups are used uses u-root as default payload. TEST=Booted on ibm/sbp1 to ubuntu22.04 using two PCI segment groups. TEST=intel/archercity CRB Change-Id: I4e6e5eca1196d4ab50e43b4b58d24eca444ab519 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-19soc/intel/xeon_sp: Initial support for PCI multi segment groupsPatrick Rudolph
Add PCI enumeration support by reading the PCIeSegment reported in the FSP HOB and add it when creating the PCI domain for each stack. The PCI enumeration will be able to scan the additional PCI segment groups and properly handle those devices. TEST=Booted on ibm/sbp1 with multiple PCI segment groups enabled to ubuntu 22.04. TEST=intel/archercity CRB Change-Id: I0ba5e426123234979d746d3bdfc1ddfbd71c3447 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79878 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-19soc/intel/xeon_sp: Add SATC PCI segment group supportPatrick Rudolph
For every PCI segment group generate a new SATC header. Allows to generate proper ACPI code when multiple PCI segment groups are enabled. TEST=Booted on ibm/sbp1 with multiple PCI segment groups. Properly generates multiple SATC headers. TEST=intel/archercity CRB Change-Id: I93b8ee05a7e6798e034f7a5da2c6883f0ee7a0e5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-18soc/intel/xeon_sp/uncore_acpi: Fix debug printPatrick Rudolph
The DMAR entries of type "PCI" have no "Enumeration ID" and thus there's no need to print it. Drop all unused Enumeration IDs to simplify the code and debug prints. Document ID: Intel Virtualization Technology for Directed I/O Architecture Specification, Rev. 4.0, Order Number: D51397-015 TEST=intel/archercity CRB Change-Id: I009fbfb9f9d62855d351c5db2d3d88722b5dbfa2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81186 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17soc/amd/phoenix: make openSIL stub optionalMarshall Dawson
Convert the 'select SOC_AMD_OPENSIL_STUB' statement to a config option and give it a prompt. This allows for internal development of openSIL and corresponding coreboot source, and controllable using a defconfig. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I2b48e2bbf71cd94ac7ecec13834ba36aa6c241ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/81188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-17soc/intel/mtl: Enable RAMTOP caching at SoC level for MTL devicesSubrata Banik
This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` configuration at the SoC level for all MTL devices. This change streamlines the configuration process, avoiding redundant selections on individual mainboards. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot functionality on google/ovis and google/rex. Change-Id: I3aa3a83c190d0a0e93c267222a9dca0ac7651f9c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-03-17soc/intel/cmn/ramtop: Refactor MTRR handling for RAMTOP rangeSubrata Banik
This patch refactors RAMTOP MTRR type selection to address a critical NEM logic bug on SoCs with non-power-of-two cache sets. This bug can cause runtime hangs when Write Back (WB) caching is enabled. Workaround: Force MTRR type to WC (Write Combining) on affected SoCs when the cache set count is not a power of two. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot on google/ovis and google/rex (including Ovis with non-power-of-two cache configuration). Change-Id: Ia9a8f0d37d581b05c19ea7f9b1a07933caa956d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81269 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-15treewide: Move stdlib.h to commonlibMaximilian Brune
This patch moves commonlib/stdlib.h -> commonlib/bsd/stdlib.h, since all code is BSD licensed anyway. It also moves some code from libpayloads stdlib.h to commonlib/bsd/stdlib.h so that it can be shared with coreboot. This is useful for a subsequent commit that adds devicetree.c into commonlib. Also we don't support DMA on arm platforms in coreboot (only libpayload) therefore `dma_malloc()` has been removed and `dma_coherent()` has been moved to architecture specific functions. Any architecture that tries to use `dma_coherent()` now will get a compile time error. In order to not break current platforms like mb/google/herobrine which make use of the commonlib/storage/sdhci.c controller which in turn uses `dma_coherent` a stub has been added to arch/arm64/dma.c. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I3a7ab0d1ddcc7ce9af121a61b4d4eafc9e563a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-03-14soc/intel/xeon_sp: Rewrite acpi_fill_dmarShuo Liu
Rewrite the function by iterating IOMMU (Input/Output Memory Management Unit) devices instead of iterating socket and stacks, which is more aligned to coreboot infrastructure. TEST=intel/archercity CRB coreboot DRHD generation is compared, the order of sections are changed as expected but the content is kept equvalient. Change-Id: I700513e05181303cf3f4effc793a872eb23340cb Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81228 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14soc/intel/xeon_sp: Rewrite acpi_create_drhdShuo Liu
Obtain IOMMU (Input/Output Memory Management Unit) info and enumerate devices using device utils instead of FSP HOB interface, which might change across SoC generations and no ambiguity across multiple PCIe segments. TEST=intel/archercity CRB coreboot DRHD generation log no changes before and after Change-Id: Ic5c404899172a0e4fba2721b8e8ca6c1f0856698 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81227 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14intelblocks/pmc: Assign initial values to pmc_gpe_init variablesGang Chen
pmc_gpe_init uses soc_get_gpi_gpe_configs to initialize dw0, dw1 and dw2. dw0, dw1 and dw2 are uninitialized before calling soc_get_gpi_gpe_configs. This is error prone for some soc implementations where soc_get_gpi_gpe_configs does nothing. This patch is simple, just to assign zero values to dw0, dw1 and dw0, to enhance the code robustness. TEST=intel/archercity CRB Signed-off-by: Gang Chen <gang.c.chen@intel.com> Change-Id: I8a710a2ac1482eed8c11977d51b187d834122d26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81210 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14soc/intel/xeon_sp: Add utils to detect domain0 and stack0Shuo Liu
In Xeon-SP, the domain0, which is located at stack0, usually needs special handling due to the compatible devices on it (HEPT, IO-APIC and legacy IOs). This patch adds util function detect whether a give domain or stack is with such a role. TEST=intel/archercity CRB Change-Id: I2f26b4ac54091c24c554f17964502c364288aa40 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-14soc/intel/xeon_sp: Add domain role checking utilsShuo Liu
For Xeon-SP, there are 4 main domain roles (PCIe/CXL/IOAT/UBOX). This patch adds util function to check whether a given domain belongs to one of these roles, or a give device belongs to a domain of the specific role. TEST=intel/archercity CRB Change-Id: I6b31c29564c774c27e86f55749ca9eca057a0cfe Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-14soc/intel/xeon_sp: Use common _CRS code generationPatrick Rudolph
Drop SoC specific code and use generic implementation provided by pci_domain_fill_ssdt. TEST=Booted on IBM/SBP1 to Ubuntu 22.04. TEST=intel/archercity CRB Change-Id: I8b0bc2eb02569b5d74f8521d79e0af8fee880c80 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80796 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-14soc/intel/xeon_sp: Drop IIO_UDS argumentPatrick Rudolph
Use CONFIG_MAX_SOCKET instead of the IIO_UDS hob. Allows to drop the argument in Xeon-SP common layer. TEST=intel/archercity CRB Change-Id: I05ec127f2bf84d3c242c3b0bca9709a0a7a4b52b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81181 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-14vendorcode/edk2-stable202302: Remove wchar_t assertsArthur Heymans
Remove those MSVC compiler defaults checks so that the GCC defaults for wchar_t can be used. The FSP interface does not depend on wchar_t. TEST: the resulting binaries are the same for intel/mtlrvp Change-Id: I0ee1abc7e9ba46665838b63a6cfe0f4aa300114c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-03-13Revert "soc/intel/xeon_sp: Rewrite acpi_create_drhd"Martin L Roth
This reverts commit 6995efbd1b986d0426ca513fd2e56771dd489f16. Reason for revert: Submitted out of order and broke the coreboot build: src/soc/intel/xeon_sp/uncore_acpi.c:275:6: error: call to undeclared function 'is_dev_on_domain0'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 275 | if (is_dev_on_domain0(iommu)) { | ^ src/soc/intel/xeon_sp/uncore_acpi.c:343:35: error: call to undeclared function 'is_dev_on_ioat_domain'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 343 | if (CONFIG(HAVE_IOAT_DOMAINS) && is_dev_on_ioat_domain(iommu)) { | ^ src/soc/intel/xeon_sp/uncore_acpi.c:423:4: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference] 423 | assert(vtd_mmio_cap != 0xffffffffffffffff); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^~~~~~~~~~~~~~~~~ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^~~~~~~~~~~~~~~~ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^~~~~~~~~~~~~~~~~~~~~ src/soc/intel/xeon_sp/uncore_acpi.c:423:4: note: consider using __builtin_trap() or qualifying pointer with 'volatile' src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^ src/soc/intel/xeon_sp/uncore_acpi.c:455:3: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference] 455 | assert(ptr); | ^~~~~~~~~~~ src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^~~~~~~~~~~~~~~~~ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^~~~~~~~~~~~~~~~ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^~~~~~~~~~~~~~~~~~~~~ src/soc/intel/xeon_sp/uncore_acpi.c:455:3: note: consider using __builtin_trap() or qualifying pointer with 'volatile' src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^ src/soc/intel/xeon_sp/uncore_acpi.c:540:7: error: call to undeclared function 'is_domain0'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 540 | if (is_domain0(dev_get_pci_domain(dev))) { | ^ src/soc/intel/xeon_sp/uncore_acpi.c:546:2: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference] 546 | assert(iommu0); | ^~~~~~~~~~~~~~ src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^~~~~~~~~~~~~~~~~ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^~~~~~~~~~~~~~~~ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^~~~~~~~~~~~~~~~~~~~~ src/soc/intel/xeon_sp/uncore_acpi.c:546:2: note: consider using __builtin_trap() or qualifying pointer with 'volatile' src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^ Change-Id: I8b66177119ea5f55913a16aae06a3dcb807c2c64 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-13Revert "soc/intel/xeon_sp: Rewrite acpi_fill_dmar"Martin L Roth
This reverts commit 6833e8c01afc2827f150135f3805dc71820ddaa4. Reason for revert: Submitted out of order and broke the coreboot build. src/soc/intel/xeon_sp/uncore_acpi.c:275:6: error: call to undeclared function 'is_dev_on_domain0'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 275 | if (is_dev_on_domain0(iommu)) { | ^ src/soc/intel/xeon_sp/uncore_acpi.c:343:35: error: call to undeclared function 'is_dev_on_ioat_domain'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 343 | if (CONFIG(HAVE_IOAT_DOMAINS) && is_dev_on_ioat_domain(iommu)) { | ^ src/soc/intel/xeon_sp/uncore_acpi.c:423:4: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference] 423 | assert(vtd_mmio_cap != 0xffffffffffffffff); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^~~~~~~~~~~~~~~~~ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^~~~~~~~~~~~~~~~ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^~~~~~~~~~~~~~~~~~~~~ src/soc/intel/xeon_sp/uncore_acpi.c:423:4: note: consider using __builtin_trap() or qualifying pointer with 'volatile' src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^ src/soc/intel/xeon_sp/uncore_acpi.c:455:3: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference] 455 | assert(ptr); | ^~~~~~~~~~~ src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^~~~~~~~~~~~~~~~~ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^~~~~~~~~~~~~~~~ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^~~~~~~~~~~~~~~~~~~~~ src/soc/intel/xeon_sp/uncore_acpi.c:455:3: note: consider using __builtin_trap() or qualifying pointer with 'volatile' src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^ src/soc/intel/xeon_sp/uncore_acpi.c:540:7: error: call to undeclared function 'is_domain0'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 540 | if (is_domain0(dev_get_pci_domain(dev))) { | ^ src/soc/intel/xeon_sp/uncore_acpi.c:546:2: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference] 546 | assert(iommu0); | ^~~~~~~~~~~~~~ src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^~~~~~~~~~~~~~~~~ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^~~~~~~~~~~~~~~~ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^~~~~~~~~~~~~~~~~~~~~ src/soc/intel/xeon_sp/uncore_acpi.c:546:2: note: consider using __builtin_trap() or qualifying pointer with 'volatile' src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^ Change-Id: If919d6fa578a82fbb6bc5e1fd2adf4e9f59cab95 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81232 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-13soc/intel/xeon_sp: Rewrite acpi_fill_dmarShuo Liu
Rewrite the function by iterating IOMMU (Input/Output Memory Management Unit) devices instead of iterating socket and stacks, which is more aligned to coreboot infrastructure. TEST=intel/archercity CRB coreboot DRHD generation is compared, the order of sections are changed as expected but the content is kept equvalient. Change-Id: I4c1cbf8d8fc93f746640efc3a82c539dcb3fdee2 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-13soc/intel/xeon_sp: Rewrite acpi_create_drhdShuo Liu
Obtain IOMMU (Input/Output Memory Management Unit) info and enumerate devices using device utils instead of FSP HOB interface, which might change across SoC generations and no ambiguity across multiple PCIe segments. TEST=intel/archercity CRB coreboot DRHD generation log no changes before and after Change-Id: Idcfa899c764ffe51db5ed202ead07ad7b6868864 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81048 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-13soc/intel/mtl: Improve functions in soc_info.cTyler Wang
Remove debug message since it's static information. Remove additional uint_8 varience and return below settings directly: 1. CONFIG_SOC_INTEL_USB2_DEV_MAX 2. CONFIG_SOC_INTEL_USB3_DEV_MAX 3. MAX_TYPE_C_PORTS 4. CONFIG_MAX_TBT_ROOT_PORTS 5. CONFIG_MAX_ROOT_PORTS 6. CONFIG_MAX_PCIE_CLOCK_SRC 7. CONFIG_SOC_INTEL_UART_DEV_MAX 8. CONFIG_SOC_INTEL_I2C_DEV_MAX 9. CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX BUG=none TEST=Build and test on rex/karis, system can boot to OS Change-Id: I26e882d2d9dcbef84718924aaab3864d89c58f39 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-03-13soc/intel/xeon_sp: Add device find utilsShuo Liu
For Xeon-SP, it's common pattern to find devices under specific socket, stack and domain. This patch adds util function for these operations. TEST=intel/archercity CRB Change-Id: I163eacae363334919fd66d571b7e0415e77bd52d Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-12soc/intel/common/block: Add support for watchdogMarek Maslanka
Implement watchdog for intel based platform by filling ACPI Watchdog Action Table (WDAT) table. The WDAT ACPI table encompasses essential watchdog functions, including: - Setting and retrieving countdown/timeout values - Starting and stopping the watchdog - Pinging the watchdog - Retrieving the cause of the last reboot, whether it was triggered by the watchdog or another reason The general purpose register TCO_MESSAGE1 stores the reason for the most recent reboot rather than the original register TCO2_STS. This is because the firmware must clear TCO2_STS, and it can't be reused for storing this information for the operating system. The watchdog is designed for use by the OS through certain defined actions in the WDAT table. It relies on the ACPI Power Management Timer, which may result in an increase in power consumption. BUG=b:314260167 TEST=Enable CONFIG_ACPI_WDAT_WDT and CONFIG_USE_PM_ACPI_TIMER in the config. Enable CONFIG_WDAT_WDT in the kernel config. Build and deploy both firmware and kernel to the device. Trigger the watchdog by performing the command: “cat > /dev/watchdog”. Wait approximately 30 seconds for the watchdog to reset the device. Change-Id: Iaf7971f8407920a553fd91d2ed04193c882e08f1 Signed-off-by: Marek Maslanka <mmaslanka@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-12soc/intel/xeon_sp: Rewrite acpi_create_satcShuo Liu
SATC is for RCiEPs (Root Complex Integrated EndPoints) but not limited to IOAT domains. Rewrite the func by iterating all domains and its RCiEPs. Currently the codes only support 1 PCIe segment. TEST=intel/archercity CRB coreboot SATC generation logs are unchanged before and after. Change-Id: I1dfc56ccf279b77cfab4ae3457aa8799d2d57a34 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81049 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-12soc/intel/xeon_sp: Create CXL domainsShuo Liu
SPR CXL IIO stack is divided into 2 PCI domains. The 1st domain is a PCI domain with single bus number and PCIe RCiEPs (Root Complex Integrated End Points) on it. The 2nd domain is a CXL domain with remaining buses for CXL 1.0/1.1 end points and possible SR-IOV (Single Root IO Virtualizaton) VFs (Virtual Function) if any. TEST=intel/archercity CRB P.S. The SUT is not with CXL cards however we hope this refactor could be integrated first as an improvement of the design. Change-Id: I643bcfbae7b6e8cfe11c147cc89374bc6b4d5a80 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81099 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09soc/intel/common/mp_init: Fix USE_INTEL_FSP_MP_INIT use-caseJeremy Compostella
Commit 829e8e65b939 ("soc/intel: Use common codeflow for MP init") brokes `USE_INTEL_FSP_MP_INIT' by making `init_cpus' function static. This function needs to be accessible from src/drivers/intel/fsp2_0/fsp_mpinit.c. TEST=Verified on Meteor Lake rex board Change-Id: Idb8cdfef7b4279da2c7dff344c95fe446a605934 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-09soc/intel/alderlake: Add Raptor Lake System Agent Device IDsLean Sheng Tan
Add System Agent IDs for Raptor Lake SKUs based on RPL Datasheet (Doc ID: 743844) & EDS Vol 1 (Doc ID: 640555). Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I805040c65852742f1bbc43b443e115bcb0a930aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/81115 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09soc/intel/xeon_sp: Further share domain creation logics in Xeon-SPShuo Liu
With this patch, all domain creation logics are moved into the scope of attach_iio_stack/chip_common.c for the ease of maintenance and future SoC integration where the domain creation process for specific stack types might be overridden. TEST=intel/archercity CRB 1. Boot to CentOS 9 Stream Cloud. 2. Compare PCIe enumeration and ACPI table generation logs before and and after this patch, no changes. Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81098 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09soc/intel/alderlake: Remove the guard for CnviWifiCoreSean Rhodes
The CnviWifiCore UPD exists for ADL (version 4263) and RPL (version 4415). Remove the guard so it is set correctly. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9943ee43a442a43d75e78d1551e46dcea39db357 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81079 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-08drivers/intel/fsp2_0: Add "silicon" to the multiphase callback nameJeremy Compostella
The `platform_fsp_multi_phase_init_cb' callback is specific to FSP-S, let's rename it 'platform_fsp_silicon_multi_phase_init_cb' to avoid any confusion. Change-Id: I86b69e2069f08023e6f48464f6df4593710aa9ee Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-07soc/intel/xeon_sp/spr: Fix IOAT resourcesPatrick Rudolph
Do not generate empty mem32 resources for CPMx or HQMx stacks. Switch existing arguments to make sure that base is bigger than limit to indicate that the resource is invalid. Change-Id: I679563e97c33c7ee35d402674972e55f521eafa8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80793 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-07soc/intel/xeon_sp: Share numa.c among Xeon-SP platformsShuo Liu
NUMA will be supported by SPR and future generations. TEST=intel/archercity CRB Change-Id: I0d494f8e560059d9c8d5338cef9a6ffe34e59e26 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-07soc/intel/xeon_sp: Unshare UDK binding among Xeon-SP platformsJincheng Li
TEST=intel/archercity CRB Change-Id: I285549daad87fe1ad6e8a94853e0a92cd5930e04 Signed-off-by: Li, Jincheng <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81041 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-07soc/intel/xeon_sp: Add memory type check utilsShuo Liu
FSP memory type representations change across Xeon-SP SoCs. This patch adds type check utils to abstract the differences. TEST=intel/archercity CRB Change-Id: I2f5f3c0f16dc50bc739146e46afce2e5fbf4f62c Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-06soc/intel/xeon_sp: Add ACPI namesPatrick Rudolph
Set the unused 'name' property of the domain device and store the ACPI name. Every IIO stack can have multiple domain devices, each owning a subset of the available bus range within the stack. The name will be used in future changes to generate ACPI names in SSDT code generation. It can also be used to identify the domain type by looking at the first two characters of the name. Change-Id: Ic4cc81d198fb88300394055682a3954bf22db570 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80792 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-05soc/intel: Add definition of D0 stepping for TigerLake HaloAlicja Michalska
Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Signed-off-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-05soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E portsAlicja Michalska
ACPI _PRT method was missing from PEG (SoC PCI-E) links, resulting in OS complaining about interrupt routing. 'pcieport 0000:00:06.0: can't derive routing for PCI INT A' 'nvme 0000:04:00.0: PCI INT A: not connected' 'Interrupt: pin A routed to IRQ -2147483648' TEST=Boot Linux and Windows 10 on TGL-H platform with PEG0/PEG1 populated with PCI-E devices - Radeon RX 7800XT and Kingston KC3000 NVME SSD. Check logs and stability while running 3D application and disk benchmark at the same time. Change-Id: If102522efa1a67b362b14d859d9e27a37bad85a4 Signed-off-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80848 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-05soc/intel/xeon_sp: Move MEM_ADDR_64MB_SHIFT_BITS to Xeon-SPShuo Liu
Move MEM_ADDR_64MB_SHIFT_BITS from FSP headers to Xeon-SP common layer to reduce the dependency. TEST=intel/archercity CRB Change-Id: I4e1a652ad58233f7514cb9b23813d75144b8d435 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-05drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bugArthur Heymans
Starting with Intel CPX there is a bug in the reference code during the Pipe init. This code synchronises the CAR between sockets in FSP-M. This code implicitly assumes that the FSP heap is right above the RC heap, where both of them are located at the bottom part of CAR. Work around this issue by making that implicit assumption done in FSP explicit in the coreboot linker script and allocation. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80579 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-05soc/intel/xeon_sp: Drop unused helper functionsPatrick Rudolph
Change-Id: Ib319643f6b0b91d8c5854da531e035d333f04d75 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80143 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-05soc/intel/xeon_sp: Drop code to locate the UBOX busPatrick Rudolph
Drop the code to retrieve the UBOX bus numbers. Only keep a minial function that works when called from socket0 to retrieve the bus for UBOX(1). Change-Id: I2b18f02f62b69ec7c73cd5665102cb6bfc6e64b5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80102 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-05soc/intel/xeon_sp/util: Enhance lock_pam0123Patrick Rudolph
- Only compile code in ramstage - Lock PAM on all sockets - Instead of manually crafting S:B:D:F numbers for each PCI device search for the devices by PCI vendor and device ID. This adds PCI multi-segment support without any further code modifications, since the correct PCI segment will be stored in the devicetree. Change-Id: Ic8b3bfee8f0d02790620280b30a9dc9a05da1be8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-05soc/intel/cmn/cse: Deprecate CONFIG_SOC_INTEL_CSE_RW_VERSIONSubrata Banik
This patch marks CONFIG_SOC_INTEL_CSE_RW_VERSION as deprecated, as future platforms will automatically determine the CSE RW version using CSE RW partition. BUG=b:327842062 TEST=CSE RW update successful on Screebo. Change-Id: I8c3e5c759e4d9a43c3bce3a0c032086f17592a67 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80924 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2024-03-04soc/intel/cmn/cse: Use CSE RW partition version directly for CBFS entrySubrata Banik
This patch automates the process of determining the CSE RW version used for the CBFS entry, eliminating the need for manual configuration in CONFIG_SOC_INTEL_CSE_RW_VERSION. How to get CSE RW Version: 1. Open CSE RW file as per CONFIG_SOC_INTEL_CSE_RW_FILE 2. Read offset 16 (0x10) to know the CSE version 3. Format: - CSE_VERSION_MAJOR : offset 16-17 - CSE_VERSION_MINOR : offset 18-19 - CSE_VERSION_HOTFIX: offset 20-21 - CSE_VERSION_HOTFIX: offset 22-23 Benefits: - Removes error-prone manual version updates. - Prevents boot loops due to mismatched CSE RW versions (actual vs config) - Eliminates the need for SKU-specific CSE version limitations. BUG=b:327842062 TEST=CSE RW update successful on Screebo with this patch. Example Debug Output: [DEBUG] cse_lite: RO version = 18.0.5.2066 [DEBUG] cse_lite: RW version = 18.0.5.2107 Change-Id: I0165d81b0e4b38e0e097956f250bb7484d774145 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80923 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-03soc/sifive/fu740: Add FU740 SOCMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I4a8fe02ef0adcb939aa65377a35874715c5ee58a Reviewed-on: https://review.coreboot.org/c/coreboot/+/76689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2024-03-01soc/intel/meteorlake: Select MRC_CACHE_USING_MRC_VERSIONJincheng Li
MRC_CACHE_USING_MRC_VERSION is irrelevant to the EDK2 binding version and should not be enabled under specific version conditions, so select this at SoC level. Change-Id: I10594df7c8fdc5cfe9b68975e01ae65859735544 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80728 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-29soc/amd: move common pci_domain_fill_ssdt implementation to acpi/Felix Held
Even though it has an 'amd_' prefix, the amd_pci_domain_fill_ssdt implementation doesn't contain any AMD-specific code and can also be used by other SoCs. So factor it out, move the implementation to src/acpi/acpigen_pci_root_resource_producer.c, and rename it to pci_domain_fill_ssdt. When a SoC now assigns pci_domain_fill_ssdt to its domain operation's acpi_fill_ssdt function pointer, the PCI domain resource producer information will be added to the SSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7bd8568cf0b7051c74adbedfe0e416a0938ccb99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80464 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-28soc/intel/xeon_sp/util: Locate PCU by PCI device IDPatrick Rudolph
Instead of manually crafting S:B:D:F numbers for each PCI device search for the devices by PCI vendor and device ID. This adds PCI multi-segment support without any further code modifications, since the correct PCI segment will be stored in the devicetree. Change-Id: I1dcad4ba3fbc0295d74e1bf832cce95f014fd7bf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80095 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-28soc/intel/xeon_sp: Locate PCU by PCI device IDPatrick Rudolph
Instead of manually crafting S:B:D:F numbers for each PCI device search for the devices by PCI vendor and device ID. This adds PCI multi-segment support without any further code modifications, since the correct PCI segment will be stored in the devicetree. Intel Document-ID: 735086 Intel Document-ID: 612246 Tested: On SPR 4S all PCU on all 4 sockets could be found and locked. Change-Id: I06694715cba76b101165f1cef66d161b0f896b26 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80093 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-27soc/intel/tigerlake: Remove IOM Mctp command from TCSS ASLCoolStar
Port fix from Alder Lake to not set/reset IOM MCTP during D3 cold entry or exit. Ports 5008d340033d ("soc/intel/adl: Remove IOM Mctp command from TCSS ASL"): > Recently as part of s0ix hang issue, it was found that sending IOM > MCTP command as part of TCSS D3 Cold enter-exit sequence created an > issue. > We discovered that due to change in hardware sequence, ADL should not > set/reset IOM MCTP during D3 cold entry or exit. This patch removes > the bit setting from ASL file to prevent hang in the system. > This patch also removes obsolete Pcode mailbox communication which > is no longer required for ADL. > BUG=b:220796339 > BRANCH=firmware-brya-14505.B > TEST=Check if hang issue is resolved with the CL and no other > regression > observed > https://review.coreboot.org/c/coreboot/+/62861 Test: build/boot drobit to Win11. Verify TCSS XHCI power management working and USB Root Hub doesn't Code 43 in device manager Change-Id: I40a537fd2b0c821caf282f52aaff1874f54325f1 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80719 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-27soc/intel/tigerlake: Fix processor hang while plug unplug of TBT deviceCoolStar
Port 9c348a7b7ea3 ("soc/intel/alderlake: Fix processor hang while plug unplug of TBT device") from Alder Lake to fix a similar issue present on Tiger Lake: > Processor hang is observed while hot plug unplug of TBT device. BIOS > should execute TBT PCIe RP RTD3 flow based on the value of > TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if > BIT30 in TBT FW version is not set. > BUG=b:194880254 > https://review.coreboot.org/c/coreboot/+/56503 Change-Id: Ie5409111d4239be86c0b153f01b4fe5fc6af352c Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80718 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-27soc/intel/common/lpc: Don't open a window for unassigned resourcesMatt DeVillier
Don't attempt to open a PMIO window for a resource which doesn't have the IORESOURCE_ASSIGNED flag set, since there is no point in doing so and there's a high likelihood that the base address is 0, which will throw an error. TEST=build/boot purism/librem_cnl (Mini v2), ensure no errors in cbmem log for attempting to open a PMIO window for unaassigned resources with base address 0. Change-Id: Ifba14a8f134ba12d5f5e9fdbac775d4f82b4c4de Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-26util/amdfwtool: build amdfwtool only for all tools or AMD CPUsMartin Roth
When we're building non-AMD processors, don't bother building amdfwtool unless we're specifically building all of the tools like for abuild. Change-Id: I9021674a06d65a79e24020790d317ab947c505fe Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80714 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-26soc/mediatek: Add `MEDIATEK_DRAM_ADAPTIVE` config to support dram adaptiveYidi Lin
Starting from MT8195, MediaTek platform supports "dram adaptive" to automatically detect dram information, including channel, rank, die size..., and can automatically configure EMI settings. So we can just pass a placeholder param blob to `mt_mem_init_run` by enabling this option. Platforms (MT8173, MT8183, MT8192) which do not support "dram adaptive" need to implement `get_sdram_config` to get onboard DRAM configuration info. TEST=emerge-geralt coreboot && emerge-asurada coreboot TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is set to y on geralt TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is no set on asurada Change-Id: I05a01b1ab13fbf19b2a908c48a540a5c2e1ccbdc Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-02-26soc/intel/alderlake: Add kconfig for Twin LakeKapil Porwal
Mainboards using Intel Twin Lake (TWL) SoC shall select SOC_INTEL_TWINLAKE. BUG=none BRANCH=firmware-nissa-15217.B TEST=Build and boot Google/Yaviks with Twin Lake kconfig enabled Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ie4c5d137ee54512313344f853e7ca66d1fd25003 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80688 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-24soc/amd/glinda: Update GPP_CLK_OUTPUT_AVAILABLE to 7Varshit Pandya
Glinda started as a copy of mendocino and GPP_CLK_OUTPUT_AVAILABLE was not updated. GPP_CLK_OUTPUT_AVAILABLE should be 7 as per Processor Programming Reference (PPR) (#57254), table "GPP ClkREQB Mapping". Change-Id: I26e9dea58b2ddf5cbedbcccb8bcbc5f9efab3165 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80701 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-23soc/amd/common/acp: use clrsetbits32p to avoid need for castsFelix Held
Use clrsetbits32p instead of clrsetbits32 to not need to cast the uintptr_t address to void * in the function call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic29bf04866a7e1d5c831422f31803a724a41069b Reviewed-on: https://review.coreboot.org/c/coreboot/+/80700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-02-23soc/amd/glinda: Use gpp_clk_setup_common functionVarshit Pandya
In follow up to commit 0452d0939e7d ("soc/amd: Factor out gpp_clk_setup function") use gpp_clk_setup_common for glinda as well. Change-Id: If0c1cda0d36de48c7f7315a1b8203b0e53f63f75 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80699 Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-02-23arch/x86/ioapic: use uintptr_t for IOAPIC base addressFelix Held
Use uintptr_t for the IOAPIC base parameter of the various IOAPIC- related functions to avoid needing type casts in the callers. This also allows dropping the VIO_APIC_VADDR define and consistently use the IO_APIC_ADDR define instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I912943e923ff092708e90138caa5e1daf269a69f Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-02-23soc/amd/glinda: Use pcie_gpp_dxio_update_clk_req_configVarshit Pandya
This function turns off gpp_clk for the devices which are disabled, and adds the code to fix up the clock configuration depending on dxio descriptors. Also this brings glinda in line with cezanne, mendocino, phoenix and picasso. This also prepares glinda to use the common function gpp_clk_setup_common. Change-Id: Id66d1b7f0d8ec9a7cbd378ad6ad7d68eeab531f0 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80415 Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-23soc/intel/adl: Set slp-s0 counter frequencyMarx Wang
System sleep time (SLP_S0 signal asserted) is measured in ticks, for Alder Lake soc in 122us (i.e. ~8197Hz) granularity/ticks. BUG=b:301854636 TEST=/sys/devices/system/cpu/cpuidle/ low_power_idle_system_residency_us" will show system idle residency time Change-Id: I449f7ed0d9ef891ae5266e8fd784a063a75e38eb Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-23soc/intel/xeon_sp: Locate PCI devices by Ven/Dev IDPatrick Rudolph
Since the ACPI code is looking for VtdBars, that only appear on Vtd devices, search for the Vtd device in devicetree. With the previous commit the VtdBar is now exposed as a resource on the Vtd device and thus can easily be accessed and used. Drop the FSP HOB parsing and just use coreboot native functions. Allows the code to work with multiple PCI segment groups. Change-Id: I2c752dc595ac4c901f2b3a96718e256e413c76a7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-02-23soc/intel/xeon_sp: Add helper functionsPatrick Rudolph
Provide a helper function to locate PCI devices on a given socket by their PCI vendor and device IDs and functions to return information about the current device, like the corresponding stack and socket. In addition add functions to return "location" information, like stack and socket affiliation. This becomes handy when locating devices and generating ACPI code. Change-Id: I266360588548ba579f46b228c4d5b3ae6e39a029 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80094 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-02-23soc/intel/xeon_sp/uncore: Read VtdBarPatrick Rudolph
Read the VtdBar and add it to the resources of the host bridge PCI device. The BAR is already marked as PciResourceMem32 in the parent PCI domain. This allows easy probing for VTD devices with enabled VtdBars in the next commit, without the need to look up the stack HOB. Change-Id: Id579a94e653473f3dd0dccea6e33dc64f792d028 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-22soc/intel/common/lpc: Skip setting resources for disabled devicesMatt DeVillier
If a downstream LPC device (eg, SIO function) is disabled, we shouldn't attempt to open PMIO windows for it, as those functions often have unset IO bases (which default to 0), resulting in false errors like: [ERROR] LPC IO decode base 0! TEST=build/boot purism/librem_cnl (Mini v2), verify no LPC IO errors in cbmem log for disabled SIO functions. Change-Id: I92c79fc01be21466976f3056242f6d1824878eab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-22soc/intel/braswell/gpio_support: drop unused get_gpioFelix Held
The get_gpio function in this file is both unused and it shouldn't use a signed int to pass in the MMIO base address and offset. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3b08bad040ad175b37175ef21d0a0a29525c4478 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-02-22soc/intel/xeon_sp: Print device path when reporting resourcesPatrick Rudolph
As there are multiple Vtd devices, print the path of each when reporting resource registers. Change-Id: I5d3a6484ed7c7b9760fce0f3a02a15ca26c2cbd2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80549 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-02-22soc/intel/xeon_sp: Align resources to 4KPatrick Rudolph
The lower bit of the BAR might be used for something else, like enable bits, so mask the lower 12 bits and align all base address to 4K. Confirmed that all BARs have a minimum alignment of 4K, so that masking the lower bits doesn't change the reported address. The alignment of the VTD BARs is: - VTD_MMCFG_BASE_CSR 64 MiB - VTD_MMIOL_CSR 1 MiB - VTD_NCMEM_BASE_CSR 64 MiB - VTD_TSEG_BASE_CSR 1 MiB - VTD_BAR_CSR 4 KiB Change-Id: I9a7b963c0074246616968dd15c147f4916297d59 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-22soc/intel/xeon_sp: Refactor IOAT compiler optimization outsShuo Liu
IOAT logics are optimized out for non-IOAT platforms where CONFIG(HAVE_IOAT_DOMAINS) as false. This patch puts CONFIG(HAVE_IOAT_DOMAINS) check together ahead of is_ioat_iio_stack_res() check in the corresponding if statement to fulfill the optimization outs. TEST=intel/archercity CRB Change-Id: I2d16c6ff5320bc9195a1033b6d55e3d997b19b88 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80683 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-22soc/intel/alderlake: Remove Alder Lake M SKUSean Rhodes
ADL-M is not commercially available, so it can be removed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If769989f7a0434e32ebbcc8eac9b965b70ca71ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/80614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-22soc/intel/alderlake: Sync UPD Usb4CmMode with KconfigSean Rhodes
The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set the UPD to match this to avoid the connection type being mismatched. If it's mismatched, the TBT port will time out. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8a99db165301ce08caf55aac0e33ca1994559d62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80486 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-21mb/ocp/*: Remove unused ACPI opregionArthur Heymans
The base for this region is a magic number and none for the fields are used, which likely means this was simply copied from a different firmware. Change-Id: I217bbd0b098cd15ef296854cc6262d651f11d10e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73183 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-21soc/intel/alderlake: Include ADL-N ID 5Sean Rhodes
This patch adds support for using ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7b9fc64ccf8e2401dcd55607e8f09b348efb3182 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80166 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-20soc/intel/xeon_sp: Put SRAT util macros into Xeon-SP ACPI headerShuo Liu
Macros MAX_ACPI_MEMORY_AFFINITY_COUNT and MAX_SRAT_MEM_ENTRIES_PER_IMC are ACPI table specific, and could be used across Xeon-SP SoCs. This patch moves their definition from FSP header to Xeon-SP layer ACPI header. TEST=intel/archercity CRB Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: I6c3a84b04a452bc8d4217947a7d12f050c94b56b Reviewed-on: https://review.coreboot.org/c/coreboot/+/80629 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-20soc/intel/xeon_sp: Use ACPI common flags in SRAT generationShuo Liu
Move the definition of SRAT memory flags (SRAT_ACPI_MEMORY_ENABLED and SRAT_ACPI_MEMORY_NONVOLATILE) from FSP header to ACPI common codes. TEST=intel/archercity CRB Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: I6aa5c20c9556fd5d680406518d19a83801b0852c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-02-20soc/intel/xeon_sp: Add support for is_ioat_iio_stack_resShuo Liu
IOAT is the term for the on-chip accelerator technology of Xeon-SP. In CPX and SPR, IOAT stack is also named as DINO stack. Different SoC has different check criteria for IOAT stacks, this patch introduces an util function to abstract these differences as well as cleaning up the usage of names. TEST=intel/archercity CRB Change-Id: I376928ad89b68b294734000678dad6f070d3c97d Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80578 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-19soc/intel/cannonlake: select SOC_INTEL_COMMON_BLOCK_DTTMatt DeVillier
Select this at the SoC level (like other modern Intel SoCs), and drop it from individual boards which selected it. Change-Id: I838ada7dfe948c58a5bb9805ade289b07368aa63 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-19soc/intel/alderlake: Include ADL-N ID 5 0x4618Sean Rhodes
This patch adds support for using ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3e4855ce93666c54ab35def9b58e4b13bc9a8672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-19soc/intel/common: Add ADL_N ID 5 0x4618Sean Rhodes
This patch adds ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I47bd8fa991a48d30be4975b7965f2c3c859836dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/80487 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-19soc/intel/tigerlake: Drop redundant PcieRpEnableNico Huber
The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79920 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-19soc/intel/jasperlake: Drop redundant PcieRpEnableNico Huber
The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18soc/intel/xeon_sp/spr: Don't leak memoryPatrick Rudolph
Only call fill_pds() once to prevent leaking memory. Previously it was called for every active stack on every socket. Only call dump_pds() once to prevent spamming the console with the same information. Drop the return value since it's always returning success. Change-Id: Ifa9609e9da086dc9731556014ea9b320b270d776 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-18soc/intel/xeon_sp/uncore: Don't print uninitialized memoryPatrick Rudolph
The struct map_entry has two zero'd entries due to the ifdef being used. Do not read those entries and do not print those entries. Fixes a NULL string being printed along as the vendor and device ID of the PCI device. Change-Id: Id87ced76af552c0d064538f8140d1b78724fb833 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80546 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-18soc/intel/mtl: Skip RW CBFS ucode update if RO is lockedSubrata Banik
This patch eliminates coreboot from loading microcode from RW CBFS (when the RO descriptor is locked, which indicates a fixed RO image) because the kernel can already patch the microcode on BSPs and APs while booting to OS. This may be a chance to lower the burden on the AP FW side because patching microcode on in-field devices is subject to firmware updates, which are rarely published and, if required, must go through the firmware qualification testing procedure (which is costly, unlike kernel updates for ucode updates). 1. The FIT loads the necessary microcode from the RO during reset. 2. Reloading microcode from RW CBFS impacts boot time (~60ms, core-dependent). 3. The kernel can still load microcode updates. ChromeOS devices leverage RO+RW-A/RW-B booting. The RO's microcode is sufficient for initial boot, and the kernel can apply updates later. BUG=none TEST=Verified boot optimization; in-field devices skip RW-CBFS microcode loading when RO is locked. Change-Id: Ia859809970406fca3fa14e6fa8e766ab16d94c8a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
2024-02-18soc/intel/jasperlake: select SOC_INTEL_COMMON_BLOCK_DTTMatt DeVillier
Select this at the SoC level (like other modern Intel SoCs), and drop it from individual boards which selected it. Change-Id: I8ebb915fbc21f82e39304473b0fcaa620559b5d5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80558 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18soc/intel/common/block/dtt: Add ACPI stub for TCPU deviceMatt DeVillier
Add an ACPI stub containing the TCPU device in proper scope, along with the device status, on boards not using the DPTF driver, so that there exists an ACPI device to be referenced from the PEPD LPI constraint list. Adding the stub fixes an AE_NOT_FOUND ACPI error under Linux for _SB.PCI0.TCPU on boards with the SA thermal device enabled but which do not use the Intel DPTF driver. TEST=build/boot Linux,Win11 on purism/librem_cnl (Librem Mini v2). Change-Id: I926d0461e5e0dfaf606102575c2be555a6bfb695 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-18soc/intel/alderlake/acpi: Drop ACPI stub for SATA deviceMatt DeVillier
This is now generated by acpigen in the common/block/sata module. Change-Id: Ic45a059f47a090aa1993e83884408a82826b30cf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-18soc/intel/common/block/sata: Fix scope for SATA ACPI deviceMatt DeVillier
acpi_device_path() includes the device name, so we end up with: Scope (\_SB.PCI0.SATA) { Device (SATA) { ... Fix this by using acpi_device_scope() instead. TEST=build/boot purism librem_cml (Mini v2), dump ACPI and verify SATA device scope correct. Change-Id: Ibbc8890d93b22f0ecba4b3a9b0531994574b3d55 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80554 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-18soc: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-17intelblocks/systemagent: Add missing N6005 Jasper Lake SKU to PCI ID listMichał Żygowski
Change-Id: I3fb4c6cfe24290c34682ff1c3396540465048727 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 10:19:04 +0000