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2022-12-22soc/intel/xeon_sp: Move codes to support new PCHTim Chu
Different PCHs have different definitions for registers. Here create a lbg folder and move lbg specific codes to this folder so that we can add new PCH code under xeon_sp folder. * Create lbg folder and move lbg specific codes from pch.c to soc_pch.c under lbg folder. * Rename lewisburg_pch_gpio_defs.h to gpio_soc_defs.h and move to lbg folder. * Rename gpio.c to soc_gpio.c and move to lbg folder. * Move pcr_ids.h to lbg folder. * Move lbg specific codes from pmutil.c to soc_pmutil.c under lbg folder. * Create and revise makefile for files under lbg folder. TEST=Can boot into OS on OCP Delta Lake. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I06555ed6612c632ea2ce1938d81781cd9348017a Reviewed-on: https://review.coreboot.org/c/coreboot/+/70009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22soc/intel/meteorlake: Add ASPM setting in pcie_rp_configDinesh Gehlot
This change provides config for devicetree to control ASPM per port TEST=Build and Boot verified on google/rex Port of 'commit 6e52c1da4a22 ("soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config)' Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I284bf51628193aa5f82f21fbf29c57a6ea5f9cd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70661 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22soc/intel/xeon_sp: Lock down LPC configurationJonathan Zhang
For LPC, set BIOS interface lock. Also set the LPC BIOS control to match the SPI BIOS control settings. BIOS control EISS and WPD are set when the BOOTMEDIA_SMM_BWP config option is set. Change-Id: I3e3edc63c0d43b11b0999239ea49304772a05275 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2022-12-22soc/intel/alderlake: Add Raptor Lake device IDsMarx Wang
Add system agent ID for RPL QDF#Q2MB/Q2PS TEST=able to build coreboot successfully Signed-off-by: Marx Wang <marx.wang@intel.com> Change-Id: I169c8bc51cdf7fbfcdb1996d93afa4a352e2fddf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71121 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-22soc/intel/meteorlake: Disable L1 substates for PCIe compliance test modeSubrata Banik
Disable L1 substates for PCIe compliance test mode in order to get continuous clock output. This patch is backported from commit 8c46232005767ecbdebb7290f15cacf2756c9586 (soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I490a3e8158472fdd3bbc1aec74b2658b0fab56e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71169 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-22soc/intel: Set `use_eisa_hids` based on `DPTF_USE_EISA_HID` configSubrata Banik
This patch avoids hardcoding to the `use_eisa_hids` variable instead relying on the SoC config to choose if the SoC platform supports EISA HID. If any SoC platform has the support then the `use_eisa_hids` variable would be set to `true` based on the selection of `DPTF_USE_EISA_HID` config. Note: Prior to Tiger Lake, all DPTF devices used 7-character EISA IDs. If selected, the 7-character _HIDs will be emitted, otherwise, it will use the "new" style, which are regular 8-character _HIDs. Ideally, the platform prior to Tiger Lake would set `use_eisa_hids` to `true` and platform posts that would set `use_eisa_hids` to `false`. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I869bebc8e17c1e65979ca3431308d69771a34fa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71110 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/{apl,cnl,jsl}: Enable EISA HID support for DPTFSubrata Banik
This patch selects `HAVE_DPTF_EISA_HID` config for APL, CNL and JSL platform. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ice01c5720ba7f15861899d89981225cb76f9fcd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71109 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/tigerlake: Move DPTF ACPI Device IDs into header fileSubrata Banik
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h) so that upcoming patches in this patch train can achieve more common code. TEST=Able to build and boot Google/Volteer. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I111fa9b2672ad01268bb2620b47a53a7a5b00f3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71107 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/jasperlake: Move DPTF ACPI Device IDs into header fileSubrata Banik
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h) so that upcoming patches in this patch train can achieve more common code. TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibb31ab29c803dde70ef9ccf2b7c7c2ca0845b568 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71106 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/cannonlake: Move DPTF ACPI Device IDs into header fileSubrata Banik
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h) so that upcoming patches in this patch train can achieve more common code. TEST=Able to build and boot Google/Hatch. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7a9218a41825d2fa40a1c1b96a333465b7f617c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71105 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/apollolake: Move DPTF ACPI Device IDs into header fileSubrata Banik
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h) so that upcoming patches in this patch train can achieve more common code. TEST=Able to build and boot Google/Reef. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0ce956351afc06871c465b67f51cba8786ce52db Reviewed-on: https://review.coreboot.org/c/coreboot/+/71104 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/alderlake: Move DPTF ACPI Device IDs into header fileSubrata Banik
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h) so that upcoming patches in this patch train can achieve more common code. TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ied32eb301b0702ad7cf12b662886c9060415eb72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71103 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/elkhartlake: Add DPTF ACPI Device IDs into header fileSubrata Banik
This patch adds DPTF ACPI Device IDs into the header file (soc/dptf.h) so that upcoming patches in this patch train can achieve more common code. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia4c3f1dbca2c0099cbf00137008c1aa1bcb196b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71125 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22drivers/intel/dptf: Add `soc_` prefix for `get_dptf_platform_info()`Subrata Banik
This patch makes the SoC specific callback code more readable by adding `soc_` prefix into the `get_dptf_platform_info()`. In nutshell this patch renames `get_dptf_platform_info()` to `soc_get_dptf_platform_info()`. TEST=Able to build Google/Rex without any compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I27d6a146d5928e1742f82f85f51ad42656f46344 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-12-22soc/intel/meteorlake: Update scaling factor MTL big coreSridhar Siricilla
The patch updates the scaling factor for MTL big core. TEST=Build the Rex code Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ife069fb29f4e913c5ef1af1f719b3392a70c55c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70355 Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22soc/mediatek: Move dapc_init to commonYidi Lin
dapc_init flow is the same on MT8186, MT8188 and MT8195. So move this function to common/devapc.c TEST=emerge-corsola coreboot; emerge-cherry coreboot; emerge-geralt coreboot TEST=devapc log is shown as expected and the system boots to kernel Change-Id: I979c3a3721a82d40c9e2db7fbe62e14a9bbd53d8 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71137 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-21soc/intel/meteorlake: Select INTEL_GMA_OPREGION_2_1Dinesh Gehlot
Meteor Lake supports IGD Opregion version 2.1. BUG=b:190019970 (for alderlake) BRANCH=None TEST=Build and Boot verified on google/rex Port of 'commit 81d367feee13 ("soc/intel/alderlake: Select INTEL_GMA_OPREGION_2_1")' Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I89e42b481834ed5ab35909b31b76215eaf8c7b36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-21treewide: Remove duplicated includesElyes Haouas
<types.h> provides <commonlib/bsd/cb_err.h>, <stdint.h> and <stddef.h>. Change-Id: I966303336e604b1b945df77e5d4c3cccbf045c56 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-12-21soc/intel/skl; mb/google/eve,poppy: Update NHLT methodsMatt DeVillier
Adapted from WIP (and now abandoned) patches CB:25334, 26308, 26309. Update the nhlt_soc_add_*() methods for max98373, max98927, and rt5514 codecs to program the render and feedback slot numbers as appropriate. TEST=boot Windows on google/eve, atlas, nocturne, and rammus. Verify audio functional with both Google project campfire drivers as well as coolstar's AVS audio drivers. Change-Id: Ib8c6e24ba539e205bd5bbd856ecff43b2c016c2e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com>
2022-12-21lib/nhlt, soc/intel/skl: Update NHLT to program feedback configMatt DeVillier
Adapted from WIP (and abandoned) patch CB:25334, this patch: 1. Ensures SSP endpoint InstanceId is 0 2. Adds capability_size parameter at the end of the nhlt 3. Adsd more config_type enum values to accommodate feedback stream 4. Programs virtual_slot values for max98373, max98927, and rt5514 nhlt files 5. Adds NHLT feedback_config parameters Default feedback configs are added here to the max98373, max98927, and rt5514 codecs; in a follow-on patch, these will be overridden at the board level. TEST=tested with subsequent patch Change-Id: I59285e332de09bb448b0d67ad56c72a208588d47 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com>
2022-12-21soc/amd/common/psp_verstage: Report previous boot statusKarthikeyan Ramasubramanian
Add support to report previous PSP boot failure to verified boot. This is required specifically on mainboards where the signed AMDFW blobs are excluded from vboot verification. BUG=b:242825052 TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Corrupt either one of SIGNED_AMDFW_A/B sections or both the sections to ensure that the appropriate FW slot is chosen. Cq-Depend: chromium:4064425 Change-Id: Iada0ec7c373db75765ba42cb531b16c2236b6cc3 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70382 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21vc/amd,soc/amd/mendocino: Add SVC_CMD_GET_PREV_BOOT_STATUSKarthikeyan Ramasubramanian
Add an SVC command to get the previous boot status. If there is any pre-x86 boot failure in the previous boot cycle, PSP stores it in warm reset persistent register and triggers a warm reset. PSP verstage on the subsequent boot gets the previous boot status and reports any failure to the vboot before a FW slot is selected. BUG=b:242825052 TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Trigger a failure scenario by corrupting certain firmware blobs and observe that PSP reports the failure boot status. On a normal boot, observed that PSP reports successful boot. Change-Id: I440deee560b72c80491bfdd7fda38a1c3a4299e5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70381 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21soc/intel/meteorlake/romstage: Rewrite the if conditionSridhar Siricilla
The patch rewrites `if` condition by connecting two different conditions using the logical and(&&) operator without changing the semantics to improve the code readability. TEST=Build the code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I8c912f694d801768b1553f33de78f01215be7f0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/70479 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2022-12-21soc/intel/{adl,mtl,tgl}: Drop unnecessary `dptf.asl`Subrata Banik
This patch drops unused `dptf.asl` from the latest IA SoC platforms as DPTF ACPI code generation is now relies on runtime aka SSDT rather than having fixed dptf.asl files to include inside the mainboard dsdt.asl. TEST=Able to build Google/Kano without any compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I30a53eace89bf5324d7c2f15c6c2d2218f90eaf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71087 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-20soc/amd/mendocino: add dptc tablet mode supportChris.Wang
add dptc support for different power parameter on tablet/clamshell mode. BUG=b:257187831 BRANCH=none TEST=validate the parameter change for each mode by AGT. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I96e04d113d18b42f3457056a5e4fa311ceccffb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-12-20soc/intel/xeon_sp: Set IA32_SMRR_PHYSMASK lock bitJohnny Lin
smm_relocation_handler is run for each thread but IA32_SMRR_PHYS_BASE and IA32_SMRR_PHYS_MASK are core scope, need to avoid writing the same MSR that has been locked by another thread. Tested=On OCP Crater Lake, rdmsr -a 0x1f3 can see all cores set the lock bit. Change-Id: I9cf5a6761c9a9e1578c6132ef83e288540d41176 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-12-20soc/intel/cmn/block/cnvi: Add missing CNVI IDs for ADLKapil Porwal
Add missing CNVI IDs for ADL - ADL-P: 0x51f2, 0x51f3 ADL-S: 0x7af1, 0x7af2, 0x7af3 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I189be9a8c8895a93d98886e6591e771bbce5f564 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-12-20soc/intel/*/crashlog.[ch]: Remove unused includesElyes Haouas
Change-Id: I126d49c27302e1ed2e00ff491d59cadda7101d12 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70924 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20src/soc: Remove unneeded <assert.h>Elyes Haouas
As _Static_assert() is a compiler built-in, <assert.h> is not needed. Change-Id: I578b4bf286538d0606569d19ec760a1846c8145b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-19tree: Replace LAnd(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LAnd (a, b)` with `a && b`. Change-Id: I6b7b958e2d2a43926663a8dc8755613abb07e949 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70844 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-19soc/intel/meteorlake: Remove dependency of FSP-S CpuMpPei ModuleSubrata Banik
This patch fixes a hidden issue present inside FSP-S while coreboot decides to skip performing MP initialization by overriding FSP-S UPDs as below: 1. CpuMpPpi ------> Passing `NULL` as coreboot assume FSP don't need to use coreboot wrapper for performing any operation over APs. 2. SkipMpInit -----> Set `1` to let FSP know that coreboot decided to skip FSP running CPU feature programming. Unfortunately, the assumption of coreboot is not aligned with FSP when it comes to the behaviour of `CpuMpPpi` UPD. FSP assumes ownership of the APs (Application Processors) upon passing `NULL` pointer to the `CpuMpPpi` FSP-S UPD. FSP-S creates its own infrastructure code after seeing the CpuMpPpi UPD is set to `NULL`. FSP requires the CpuMpPei module, file name `UefiCpuPkg/CpuMpPei/CpuMpPei.c`, function name `InitializeCpuMpWorker` to perform those additional initialization which is not relevant for the coreboot upon selecting the SkipMpInit UPD to 1 (a.k.a avoid running CPU feature programming on APs). Additionally, FSP-S binary size has increased by ~30KB (irrespective of being compressed) with the inclusion of the CpuMpPei module, which is eventually not meaningful for coreboot. Hence, this patch selects `MP_SERVICES_PPI_V2_NOOP` config unconditionally to ensure pass a valid pointer to the `CpuMpPpi` UPD and avoid APs getting hijacked by FSP while coreboot decides to set SkipMpInit UPD. Ideally, FSP should have avoided all AP related operations when coreboot requested FSP to skip MP init by overriding required UPDs. TEST=Able to drop CpuMpPei Module from FSP and boot to Chrome OS on Google/Redrix, Kano, Taeko devices with SkipMpInit=1. Without this patch: Here is the CPU AP logs coming from the EDK2 (open-source) [UefiCpuPkg/CpuMpPei/CpuMpPei.c] when coreboot sets `NULL` to the CpuMpPpi UPD. [SPEW ] Loading PEIM EDADEB9D-DDBA-48BD-9D22-C1C169C8C5C6 [SPEW ] Loading PEIM at 0x00076F9A000 EntryPoint=0x00076FA24E2 CpuMpPei.efi PROGRESS CODE: V03020002 I0 [SPEW ] Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE [SPEW ] Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 76FA0239 AP Loop Mode is 2 GetMicrocodePatchInfoFromHob: Microcode patch cache HOB is not found. CPU[0000]: Microcode revision = 00000000, expected = 00000000 [SPEW ] Register PPI Notify: 8F9D4825-797D-48FC-8471-845025792EF6 Does not find any stored CPU BIST information from PPI! APICID - 0x00000000, BIST - 0x00000000 [SPEW ] Install PPI: 9E9F374B-8F16-4230-9824-5846EE766A97 [SPEW ] Install PPI: 5CB9CB3D-31A4-480C-9498-29D269BACFBA [SPEW ] Install PPI: EE16160A-E8BE-47A6-820A-C6900DB0250A PROGRESS CODE: V03020003 I0 With this patch: No instance of `CpuMpPei` has been found in the AP UART log with FSP debug enabled. This patch is backported from commit 8409f156d588e74932924ae8aac69478a4b6388e (soc/intel/alderlake: Remove dependency of FSP-S CpuMpPei Module) Change-Id: I7d9fb37ca1cd4bf325edc951ee7293e459fa2ea4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70600 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-19soc/intel/meteorlake: Implement MultiPhase SI Init Index 2 callbackSubrata Banik
The details about how the CPU multiprocessor init (MP) has migrated from coreboot to FSP can be found in https://doc.coreboot.org/soc/intel/mp_init/mp_init.html. The major reason behind this migration is to support the Intel proprietary and restricted CPU feature programming which can't be performed if coreboot sets the BIOS_DONE or BIOS Reset CPL as part of coreboot MP Init flow (prior to calling FSP-S). Hence, the new flow introduced with Tiger Lake platform forced having monolithic MP Init peformed by FSP (using coreboot MP PPI wrapper code). The last 3-4 years of FSP doing MP Init has demonstrated ample issues during platform bringup which is specific to UEFI MP Service implementation and not relevant to open source coreboot. This new flow makes the debug and validation aspect complicated where any FSP MP Init code changes should have been validated with coreboot MP PPI wrapper else might cause some failure, unfortunately, the validation commitment has never been met, hence, issue debugging is the only solution that remains in practice. Most importantly, the restricted feature programming which demanded closed source MP Init (for features like SGX and C6DRAM) has never been enabled in coreboot (starting with Alder Lake, the SGX feature has been dropped). This patch attempts to decouple FSP-S doing MP Init from the rest of the FSP-S silicon init and introduces 2nd MultiPhase SI init which allows bootloader to perform the mandatory SoC programming before FSP-S has done with PM programming (a.k.a set the reset CPL). The core/uncore BWG suggests the minimum SoC programming before BIOS Reset CPL is set. coreboot uses the MultiPhaseSI Init Index 2 to perform the required CPU programming before enabling the BIOS Reset CPL. This implementation would allow us to get rid of FSP running CPU feature programming and additionally make several EDK2 MP service modules optional (those are packed to create FSP-S blob). In summary, this change would allow coreboot to utilize open source MP init without running into FSP-S related code blocks. Note: At present, Intel Meteor Lake FSP doesn't have support for MultiPhase SI Init, Index 2 (submitted a FSP code changes over chrome-internal to enable this feature to decouple MP Init from FSP-S init). This patch is backported from commit b6c3a0325b9b0462cca81ea4134efb6b73756577 (soc/intel/alderlake: Implement MultiPhase SI Init Index 2 callback). BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Perform several thousands cycles of suspend test and power cycle without running into any issue. Change-Id: I2ea1a8bb2b142e39c2bc9d248b7fd0041366c0db Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70558 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-17soc/intel/cmn: Clear interrupt status after HECI-1 has been receivedJohnny Lin
According to Intel doc#630774, BIOS should clear Host Interrupt Status if it has read all the slots of the message from the ME circular buffer. Since this is not found in client ME document, add a Kconfig SOC_INTEL_CSE_SERVER_SKU that only clears interrupt status for Server ME SKU. On SPR-SP, if mainboard calls get_me_fw_version via HECI-1, with the change can avoid seeing below Linux warning during boot with Linux v5.12: [ 17.868929] irq 16: nobody cared (try booting with the "irqpoll" option) [ 17.883819] CPU: 10 PID: 0 Comm: swapper/10 Not tainted 5.12.0 [ 17.902412] Hardware name: Wiwynn Crater Lake EVT2/Crater Lake-Class1 [ 17.922327] Call Trace: [ 17.927780] <IRQ> [ 17.932253] dump_stack+0x64/0x7c [ 17.939640] __report_bad_irq+0x37/0xb1 [ 17.948206] note_interrupt.cold.11+0xa/0x63 [ 17.957713] handle_irq_event_percpu+0x6a/0x80 [ 17.967626] handle_irq_event+0x2a/0x50 [ 17.976163] handle_fasteoi_irq+0x9e/0x140 [ 17.985305] __common_interrupt+0x38/0x90 [ 17.994255] common_interrupt+0x7a/0xa0 [ 18.002821] </IRQ> [ 18.007514] asm_common_interrupt+0x1e/0x40 Change-Id: I1cf21112870e53a11134d43e461b735ead239717 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-17soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE for ADL-NReka Norman
On nissa, sending EOP late improves boot time by about 57ms. Before (SOC_INTEL_CSE_SEND_EOP_EARLY): 943:after sending EOP to ME 931,206 (58,431) 943:after sending EOP to ME 932,911 (58,427) 943:after sending EOP to ME 930,908 (58,429) 943:after sending EOP to ME 941,357 (61,748) 943:after sending EOP to ME 933,289 (62,050) 943:after sending EOP to ME 939,578 (62,453) 943:after sending EOP to ME 932,491 (62,050) 943:after sending EOP to ME 929,693 (62,655) 943:after sending EOP to ME 942,247 (62,654) 943:after sending EOP to ME 936,984 (61,751) After (SOC_INTEL_CSE_SEND_EOP_LATE): 943:after sending EOP to ME 1,107,816 (3,498) 943:after sending EOP to ME 1,053,286 (25,212) 943:after sending EOP to ME 1,124,095 (3,511) 943:after sending EOP to ME 1,098,591 (3,498) 943:after sending EOP to ME 1,107,772 (3,499) 943:after sending EOP to ME 1,080,008 (45,969) 943:after sending EOP to ME 1,081,754 (8,024) 943:after sending EOP to ME 1,109,193 (4,102) 943:after sending EOP to ME 1,088,866 (4,201) 943:after sending EOP to ME 1,081,684 (4,203) BUG=b:247902068 TEST=EOP time is improved on nissa (measurements above). Change-Id: I2389831b4ab62f247193b5b0c5ec201e12eaa3db Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70849 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17soc/intel/common: Remove read-only from chip_get_common_soc_structureSean Rhodes
Remove the `const` property from chip_get_common_soc_structure so that the returned values can be overwritten as required. Cc: th3fanbus@gmail.com Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7d3db0bc119cd9b9b276abd68754e750e06a788c Reviewed-on: https://review.coreboot.org/c/coreboot/+/70774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-17soc/intel/skylake/irq.c: Fix undefined `memcpy()`Angel Pons
The original value of the `DevIntConfigPtr` is unknown, and there's no way to be absolutely certain that it actually points to usable memory. Instead of copying the data, update the pointer's address to reference the global variable directly. It is assumed that FSP does not write to the memory pointed by `DevIntConfigPtr`. Confirming this assumption is pointless; one might as well reimplement FSP instead. Change-Id: I90594cc09e3fa2aef98658441c323a44a869635b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65217 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-12-16cpu/intel: Fix clearing MTRR for clang 64bitArthur Heymans
Clang generates R_X86_64_32S symbols that get truncated. TESTED: - prodrive/hermes boots with GCC and clang - MTRR are properly cleared (tested by filling in both MTRR_FIX_64K_00000 and MTRR_FIX_4K_F8000 before clearing) Change-Id: I6a5139f7029b6f35b44377f105dded06f6d9cbf9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-16soc/intel/common: Drop unreferenced DP related macrosSridhar Siricilla
The patch drops the unreferenced DP related timeout macros. TEST=Build code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I3f4c7733a92d1b7cb107410fedaca20ede040050 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-16soc/amd/common/block/i2c: don't call die() when MMIO address is NULLFelix Held
There's no need to call die() in the case that the MMIO address of the I2C controller is NULL, so handle this case by returning a failure instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12c143916ad551c56cc4ff75ae23754018817505 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-16soc/intel/apollolake/acpi/northbridge.asl: Fix commentElyes Haouas
This fixes the following error: In file included from src/mainboard/siemens/mc_apl1/dsdt.asl:21: src/soc/intel/apollolake/acpi/northbridge.asl:15:12: warning: '/*' within block comment [-Wcomment] PXEN, 1, /* Enable */ ^ Change-Id: I1173eed69847f4c3b307ce96d76fb7185dc2f85c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70767 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-12-15soc/intel/{adl, common}: provide a list of D-states to enter LPMEran Mitrani
This was done previously for ADL. moving the code to common so it can be leveraged for other platforms (e.g. MTL) TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-15treewide: Remove unused 'include <arch/io.h>'Elyes Haouas
Change-Id: I6f1d7625eb457084ba893b25518fdfdb59cf64db Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-15soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitionsSubrata Banik
As per PCI Express Base Specification 5.0 section 5.4.1.3 ASPM Configuration +-----------------------+-------------------------------+ | Field Description | ASPM Support | +-----------------------+-------------------------------+ | 00b | No ASPM support | +-----------------------+-------------------------------+ | 01b | L0s Supported | +-----------------------+-------------------------------+ | 10b | L1 Supported | +-----------------------+-------------------------------+ | 11b | L0s and L1 Supported | +-----------------------+-------------------------------+ 100b aka 0x4 is added by FSP to allow auto configuration (to avoid conflicting with the PCI specification defined values). Additionally, changed enum definition which is now meeting the FSP expectations better. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8c9055f721e144f2ff5055e5f99ea641efc4d268 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70719 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-15soc/intel/alderlake: Disable L1 substates for PCIe compliance test modeBora Guvendik
Disable L1 substates for PCIe compliance test mode in order to get continuous clock output. BUG=b:235863379 TEST=Boot in compliance mode, check FSP settings Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com> Change-Id: I2a3b313425e00fe11f616d964f825baaef463c71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70165 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-14soc/amd/morgana/Kconfig: Remove TODO after reviewFred Reitberger
Remove more TODO comments after reviwing against morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I7fd9666a69d9a2b0902fa28ab0af0187198297ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/70466 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14soc/amd/common/block/espi_util: drop unneeded check in espi_get_configFelix Held
Since soc_get_common_config will either return a valid pointer or cause a linking error, this function will also return a valid pointer or cause a linking error, so no need for additional runtime checks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I99661247b9f8f47a708e3a6ff3f9e5359b505509 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70739 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-14soc/amd/*/config: drop invalid commentFelix Held
Since commit 28e61f16341f ("device: Use __pci_0_00_0_config in config_of_soc()") config_of_soc() was changed form being an actual function to a macro for the __pci_0_00_0_config struct pointer generated by util/sconfig. This change didn't only improve linker optimizations, but also turned runtime errors into link-time errors, so it's guaranteed that __pci_0_00_0_config won't be NULL and config_of_soc() won't "return" NULL. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id99ceaa9f7a70788da3f3068fb3da92d34fb6361 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70732 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-14soc/amd/common/block/espi_util: make espi_set_initial_config non-fatalFelix Held
Improve the espi_set_initial_config implementation so that a failure in there due to an invalid configuration won't call die() and stop booting at this point, but return an error to the caller so that the rest of the eSPI configuration will be skipped. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97f730778a190c4485c4ffe93edf19bcbaa45392 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-14soc/amd/common/block/lpc/espi_util: make eSPI pin setup failure nonfatalFelix Held
Improve the eSPI pin configuration setup so that a failure in there won't call die() and stop booting at this point, but return an error to the caller so that the rest of the eSPI configuration will be skipped. This will prevent an early boot failure if the EC is missing or the eSPI interface is in a non-functional state. Also slightly shorten the function names so that the code still fits into 96 chars. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ice2d3a791d6a464eff4fb69d02aeca0bfe580be2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70730 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-12-14soc/intel/common: Add helper function to get DP modeSridhar Siricilla
The patch adds helper function to get the DP mode. TEST=Build the code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I02ed1f818e77c37ead8ce962fa12fddfdc8efeb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-14soc/intel/alderlake: Utilize `CPU_BCLK_MHZ` over dedicated macroSubrata Banik
This patch drops the redundant macro to define CPU BCLK and instead uses `CPU_BCLK_MHZ` config to calculate the `smbios_cpu_get_max_speed_mhz`. TEST=Able to see max cpu speed is correct in smbios table while trying on Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5167f3a513c074b9e6986c960e1bcced65f1264c Reviewed-on: https://review.coreboot.org/c/coreboot/+/70676 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Drop NEM supportSubrata Banik
This patch drops NEM support from MTL and enables eNEM support. BUG=b:217130861 TEST=Able to build and boot Google/Rex in eNEM mode. Change-Id: I6ef915ec0caf0d95b488602950b0b25958ec4cbd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70673 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-14soc/intel/meteorlake: Add required configs to enable eNEMSubrata Banik
This patch combines all required configs under one umbrella config named `METEORLAKE_CAR_ENHANCED_NEM`. MTL SoC to select this config if default NEM (INTEL_CAR_NEM) is not selected. BUG=b:217130861 TEST=Able to build and boot Google/Rex. Change-Id: Iceab7cdf2973f3858d4aa83fb431ba832c0868d6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70672 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-14soc/intel/meteorlake: Reorg TCSS related configsSubrata Banik
This patch moves all required TCSS related configs under one umbrella config named `SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT`. This effort will help in future to deselect the TCSS support for MTL SoC SKUs. TEST=Able to build and boot Google/Rex. Change-Id: Id86e52842d2f8ab4dbec4a8776791e1266b94298 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70671 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14soc/intel/meteorlake: Fill ucode loading UPD if USE_FSP_MP_INIT enableSubrata Banik
This patch calls into a helper function to fill `2nd microcode loading FSP UPD` if FSP is running CPU feature programming. This patch is backported from commit fad1cb062e29c5e3a5bcfb6b67c3ce01ed765254 (soc/intel/alderlake: Fill ucode loading UPD if USE_FSP_MP_INIT enable). Change-Id: Id8c8bfd844b3213cc260df20c359b0b1437e3e28 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70599 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Remove `FIXME` as SkipMpInit UPD has deprecatedSubrata Banik
This patch drops deprecated FSP UPD `SkipMpInit` as Intel MTL FSP doesn't like to allow an option for boot firmware to perform CPU feature programming being independent of FSP. Change-Id: I6447937838ab91551d172936cbb4201ea86a614b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70557 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Drop enable_bios_reset_cpl() functionSubrata Banik
This patch drops enable_bios_reset_cpl() as FSP sets the BIOS Reset CPL before performing Graphics PM init (as part of FSP-S), hence, enable_bios_reset_cpl() function getting called inside systemagent.c is meaningless. Also, drop 1ms delay after setting the BIOS reset CPL. This patch is backported from commit 3f980ca7be36339ad2cb5700bad0658643966cf2 (soc/intel/alderlake: Drop enable_bios_reset_cpl() function). Change-Id: Ia31867153b3b5f132c393a605c44616acfd7a34b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70556 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Enable VMX and VTDSubrata Banik
Drops the `FIXME` comment and relevant code as this patch enables VMX and VTD. This patch also fixes the problem of additional reboot on every warm boot due to overriding the CPU soft-strap. TEST=No extra reboot seen while issuing warm reset from kernel console. without this patch: 950:calling FspMemoryInit 1,225,259 (20,537) 951:returning from FspMemoryInit 10,334,707 (9, 109,447) with this patch: 950:calling FspMemoryInit 1,225,259 (20,537) 951:returning from FspMemoryInit 1,334,707 (109,447) Change-Id: Ib130698e7255876c5a12abc93dd7d8a34dfae968 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70553 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14soc/intel/braswell/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I2dd154c3d4e152a14783ea82e08a7d1257abebc3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14soc/intel/cannonlake/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I9ddb71d93781c813a69dc72ce0589ffaea7b64c7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14soc/intel/icelake/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I12560d151d26186e1f4eb0165aa8cef33b7a16aa Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14soc/intel/baytrail/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: Ic171f3343bb35e43be5fdb50c5c926eede6a1d93 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-13soc/amd/morgana: Enable GPP clk req disablingFred Reitberger
Enable GPP clk req disabling on morgana after reviewing against morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id2502137486df7a8b0ac6a4b3e061b25b23e2e51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70465 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13soc/intel/common/block: add definition of GPIO configurationJeff Li
Add two macros: - PAD_CFG_NF_OWNERSHIP() - PAD_CFG_GPIO_OWNERSHIP() to support setting the Host Software Ownership (own) fields. Signed-off-by: lichenchen.carl <lichenchen.carl@bytedance.com> Change-Id: Ia3f2ad8658b751156456b69366fa4b1badb8b595 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70421 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-12-13soc/amd/morgana: Update pci int defsFred Reitberger
Update pci int defs per preview of next ppr after rev 1.52, #57396 Update birman and mayan mainboards to remove deleted PIRQs. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I10e13784761f0b9245f0ca10e3cd07d396ec4224 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70379 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13soc/intel/cmn/tcss: Skip sending CONN IPC command during S3 resumeSubrata Banik
This patch skips sending CONN IPC command to PMC if system is resuming from S3. Sending CONN IPC command as part of `tcss_configure_dp_mode()` function results into ERROR while system is resuming from S3. Additionally, skip `configure_aux_bias_pads()` during S3 resume. BUG=b:260984500 TEST=Able to test on Google/Rex. Without this patch: [ERROR] pmc_send_ipc_cmd status: fatal [ERROR] Port 1 connect request failed [SPEW ] [TCSS] TcssInit() - End With this patch: No error seen during S3 resume. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1dab7dc8b4ad76ca0c9630456803c1b9a320fe40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-13soc/qualcomm/sc7280: Add API to differentiate PRO and NON_PRO SKUsSudheer Kumar Amrabadi
The API socinfo_pro_part() returns 1 for Pro and 0 for NON_PRO SKUs. To reduce the binary footprint for chipinfo structure, change its members range from uint32_t to uint16_t. Add helper functions for reading and matching jtagid. Modified socinfo_modem_supported() API to utilize helper functions. BUG=b:248187555 TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/68384 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13soc/intel/xeon_sp/nb_acpi.c: Use read{16,32,64}p()Elyes Haouas
Change-Id: I89bfbab7850dd9bd29ca2097ee2efce058720ca7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/intel/broadwell/early_init.c: Use {read,write}32p()Elyes Haouas
Change-Id: I80b1535b86c7fc05354404d628a0a527a6701498 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/intel/baytrail/pmutil.c: Use {read,write}32p()Elyes Haouas
Change-Id: I6168be71913d00eb59d38dd4c5cf8f9c7f7ab678 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/intel/apollolake/pmutil.c: Use {read,wrire}32p()Elyes Haouas
Change-Id: Iab3215487d0a19e0791a78f953a8545dfae3d2dc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/intel/alderlake/bootblock: Use 'false/true' macrosElyes Haouas
Change-Id: Ic40f1e935b244f39fa3c1322e5128465c57f5e26 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70579 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/intel/alderlake/bootblock: Use read32p()Elyes Haouas
Change-Id: I3062e5b8a0524059b9695dfd32254c5c53598925 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70578 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/mediatek/common: Use write32p()Elyes Haouas
Change-Id: I83707071fe1801322dffad7fc89afaef5617f3c7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-13soc/cavium/cn81xx: Use write{32,64}p()Elyes Haouas
Change-Id: I9c94f45264f541ce0849a53245534a10aaa5d854 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12soc/intel/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: I97332e3008ed2e26a75c067baffdabfc7cfcf65f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12soc/intel/acpi: Replace Subtract(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Subtract (a, b)` with `a - b`. Change-Id: I77028c17dcd7925a392d56488d34090837d660f2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12{soc,superio}/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Subtract (a, b, c)` with `c = a - b`. Change-Id: If6455ab2c91619f884abae227f1ac2e2c2af6ba9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12soc/intel/acpi: Replace Add(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b)` with `a + b`. Change-Id: I0b7f22acf153fe02b471c196f8161fc0fa5a1450 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70624 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12soc/intel/acpi: Replace Add(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b, c)` with `c = a + b`, respectively `a += b` where possible. Change-Id: I96390f565d6c1ca0f4e06db9ad07af784051650c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70622 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12soc/intel/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual (a, b)` with `a != b`. Change-Id: Ia1bd22a62ec2868324a88400e27ed52c9f169751 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70619 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/braswell/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual (a, b)` with `a == b`. Change-Id: I7b74d026d0800df647fb0c981fa7865be492d3ac Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70590 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/baytrail/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual (a, b)` with `a == b`. Change-Id: I9d50ddcb4427774681aedba945079f5d04401f07 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70589 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/icelake/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual (a, b)` with `a == b`. Change-Id: I36137cbf63a36e68480029058f4426ed80ff6e3e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70588 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/acpi: Replace Decrement(a) with ASL 2.0 syntaxFelix Singer
Replace `Decrement (a)` with `a--`. Change-Id: I5c9290aaa9fc969368d5934e4f48a75d915ca5ff Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12soc/apollolake: Add DPTF HIDsSean Rhodes
Add the HIDs that Windows uses for the DPTF driver. Change-Id: Ic0cb4a45b5ebaf777a09bed1e5836e8afd873657 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66013 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12vc/amd/fsp/glinda/FspmUpd: don't use pointers for usb_phy configFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5db2587ff74432a0ce1805d8d7ae76d650693eea Reviewed-on: https://review.coreboot.org/c/coreboot/+/70506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-12soc/intel/adl/acpi: add entries for HEC1 and SRAM to DSDTAnil Kumar
HEC1 and SRAM are defined in src/soc/intel/alderlake/chipset.cb: device pci 16.0 alias heci1 on end device pci 14.2 alias shared_sram off end This patch adds entries for these devices in DSDT to prevent "AE_NOT_FOUND" errors from kernel TEST=Built and tested on brya to confirm errors are not seen. BUG=b:260258765 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ifd9c509e82ccf02a7801d51513597fe2e5d9e631 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70454 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12mb/google/geralt: Put MIPI panel data in panel_geralt.cBo-Chen Chen
There are eDP and MIPI panels supported in geralt. We put the panels' specified functions - `power_on()` and `configure_panel_backlight()` in panel_geralt.c. Also provide the common interface `get_active_panel()` in panel.c to generalize the display initialization. Since each board may support a different set of MIPI panels, we put the MIPI data in a separate file panel_geralt.c. BUG=b:244208960 TEST=emerge-geralt coreboot Change-Id: Ie928759e020a916f29f0364201a3cf202dc512c3 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-12soc/amd/morgana: Remove emmc selectFred Reitberger
Morgana does not have emmc, so do not select it. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib75618c137e825befc7384275f1a4ef9b5137b09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70477 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/meteorlake: Enable SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRIDSridhar Siricilla
The patch enables CPPCv3 support for Intel Meteor Lake which is based on hybrid core architecture. TEST=Build code for Rex. Change-Id: Iddf15f01a401eedf695f2dd07fbee0b643d143e2 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70511 Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/meteorlake: Select DISPLAY_FSP_VERSION_INFO_2Saurabh Mishra
Changes include: - Add config for Meteor Lake SoC to select FirmwareVersionInfo.h using 'DISPLAY_FSP_VERSION_INFO_2' BUG=b:260183604 TEST=Verified Google/Rex0 build with all the patch in relation chain and verified the version output prints no junk data. Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Change-Id: I789db9d280c45639eca6ceafea65b96a93a395cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/69883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-12drivers/wifi: Move ADL-P CNVi IDs from generic to IA common code CNVi driverKapil Porwal
BUG=b:259716145 TEST=Dump SSDT and see that _PRW and _DSD for CNVi device contains the value from the devicetree on google/redrix. Before: Scope (\_SB.PCI0.WFA3) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x6D, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) ... } After: Scope (\_SB.PCI0.CNVW) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x6D, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) ... } Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ia4ffedcb53afe350694eb03a144d12f714190cc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70447 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/alderlake/Kconfig: Sort defaults alphabeticallyAngel Pons
"Argh! Lack of consistency! UNACCEPTABLE!" - Emotions Swap the position of two lines so that defaults are listed in alphabetical order according to the PCH type: M, N, P, S. Change-Id: I82a23eb2b5036d3b7ec6766ae9891078f1caab69 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70522 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12vc/amd/fsp/morgana/FspmUpd: don't use pointers for usb_phy configFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Also make sure that the address of the lcl_usb_phy struct is located below the 4GB boundary, so that the truncation to 32 bits won't result in pointing to a different memory location than intended. In this error case, which I don't expect to happen, print an error and write 0 to mcfg->usb_phy_ptr so that the FSP will use its default values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1394aa6ef5f401e0c7bdd4861f1e28ae46e56e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/70505 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel: Move TCSS FW latency macros to IA common tcss.hSubrata Banik
This patch moves TCSS firmware latency related macros from SoC specific tcss.h to IA common tcss.h Additionally, ensure other structure definitions belonging to the IA common code tcss.h are not causing compilation issues for ASL files (due to including FW latency macros) hence, guarded against `!defined(__ACPI__)`. TEST=Able to build and boot Google/Rex and Google/Kano. Change-Id: Id51545ef714979c6ba09a2b468231b1f4bab0be7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70487 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/tigerlake: Move TCSS FW latency macros to tcss.hSubrata Banik
This patch moves TCSS firmware latency related macros from `tcss_pcierp.asl` to SoC specific `tcss.h`. TEST=Able to build and boot Google/Volteer. Change-Id: I96416f3b68d853c9a5a44c499719f154aa15f0ca Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70486 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/alderlake: Move TCSS FW latency macros to tcss.hSubrata Banik
This patch moves TCSS firmware latency related macros from `tcss_pcierp.asl` to SoC specific `tcss.h`. TEST=Able to build and boot Google/Kano. Change-Id: I96db2dbf050c8f09e4d9c4018a2caa286f7ef1d1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70485 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Fix typoSubrata Banik
This patch fixes typo mistake `Pyhsical` -> `Physical`. Change-Id: I211a3a710f5b63c4c16d4105f2eac50c992cfcf2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70484 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Update DPTF participants ACPI IDsSubrata Banik
This patch updates DPTF participants' ACPI IDs based on the Intel Meteor Lake Reference Code. TEST=Able to build and boot Google/Rex. Change-Id: Iccc7f3cad26a028a3b11d5e5e761bbefa7776583 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70482 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>