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2021-11-08soc/mediatek/mt8186: Add SPI driver supportRuwen Liu
Add SPI controller drivers. TEST=build pass BUG=b:202871018 Signed-off-by: Ruwen Liu <ot_ruwen.liu@mediatek.com> Change-Id: I59a885c4fa31b6e2921698eaa3b97dbdc3144946 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05soc/amd/*/include/smi: move NUMBER_SMITYPES definition to the topFelix Held
Since all other defines for the number of certain things are at the top of the file, move NUMBER_SMITYPES there as well to keep things consistent. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idfb599531d6cc382ab258bd1eae89e7b35fa9e79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-05soc/amd/*/include/smi: fix off-by-one in SCIMAPS definesFelix Held
SCIMAPS is the total number of SCI to GEVENT mappings. configure_scimap returns early when the scimap is greater or equal than SCIMAPS, so for SMITYPE_ACDC_TIMER it returned early without doing what was expected from it to do despite that being a valid value, so fix this off-by-one. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibaf8c5618ddbf0b8d4cd612a7f1347d8562bbfcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-05soc/mediatek/mt8186: Enable and initialize EINTRex-BC Chen
EINT event mask register is used to mask EINT wakeup source. All wakeup sources are masked by default. Since most MediaTek SoCs do not have this design, we can't modify the kernel EINT upstream driver to solve the issue 'Can't wake using power button (cros_ec) or touchpad'. So we add a driver here to unmask all wakeup sources. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I84946c2c74dd233419cb94f013a42c734363baf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05soc/mediatek/mt8186: Add timer supportRex-BC Chen
Add timer drivers to use timer function. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I6524e4dec4cbe7f7eb75a7940c329416559a03c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05soc/mediatek/mt8186: Add PLL and clock init supportChun-Jie Chen
Add PLL and clock init code, frequency meter and APIs for raising little CPU/CCI frequency. TEST=build pass BUG=b:202871018 Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Change-Id: Id46d0708e7ba0c1a4043a5dce33ef69421cb59c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05soc/mediatek/mt8186: add NOR-Flash GPIO setting in soc folderRex-BC Chen
The NOR-Flash can be configured on SPI0 or TDM-RX GPIOs so we have to provide an init function in SoC for the mainboard to select right configuration. TEST=boot to romstage BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I285ec64ace8b72a48ef1d481d366bd67cb9b0337 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05soc/intel/denverton_ns: Refactor `detect_num_cpus_via_cpuid()`Angel Pons
Rewrite level type check and use unsigned types. In addition, also use unsigned types in the `get_cpu_count()` function. Change-Id: I63f236f0f94f9412ec03ae25781befe619cf7c1f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05soc/intel/xeon_sp: Refactor `get_threads_per_package()`Angel Pons
Reduce the visibility of the `get_threads_per_package()` function and retype its return value to `unsigned int`. Change-Id: Ie71730d9a89eb7c4bb82d09d140fbcec7a6fe5f3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05soc/intel/braswell: Make `num_cpus` unsignedAngel Pons
Change-Id: Iff6da3dc9c744a3dae3f4dd4ac37a91f348450a3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05soc/intel/baytrail: Make `num_cpus` unsignedAngel Pons
Change-Id: I9ab0106c27a834d5d2ac1cb8023f4400a8ad91cd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04soc/intel: Replace bad uses of `find_resource`Angel Pons
The `find_resource` function will never return null (will die instead). In cases where the existing code already accounts for null pointers, it is better to use `probe_resource` instead, which returns a null pointer instead of dying. Change-Id: I2a57ea1c2f5b156afd0724829e5b1880246f351f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-04soc/amd/common/block/spi: Add prompt to SOC_AMD_COMMON_BLOCK_SPI_DEBUGRaul E Rangel
Makes it so I can enable SPI debugging without modifying the source. BUG=b:179699789 TEST=Add CONFIG_SOC_AMD_COMMON_BLOCK_SPI_DEBUG=y to my .config Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie3815e0398b5268874039196a625fc29dd3dc3d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04Kconfig,soc/amd/cezanne: Make COOP_MULTITASKING select TIMER_QUEUERaul E Rangel
This reduces the number of selects required in the SOC_SPECIFIC_OPTIONS. BUG=b:179699789 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7f1364fc269ea5ec17982bf750a164a3290adb0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMARaul E Rangel
AMD platforms require the destination buffer to be 64 byte aligned when using the SPI DMA controller. BUG=b:179699789 TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug $1 = {buf = 0x0, size = 0, alignment = 64, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0} Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec Reviewed-on: https://review.coreboot.org/c/coreboot/+/58707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-04amd/i2c: Remove the weak functionZheng Bao
BUG=b:140165023 Change-Id: Ieedd6c9f3abeed9839892e5d07127862cd47d57f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04soc/amd/cezanne/include/gpio: fix GPIO 106 native function namesFelix Held
The name looked a bit odd and the Cezanne PPR #56569 Rev 3.03 confirmed that the native function names don't have the EMMC_ prefix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I917c74afd98f2e2133e160d352f11f08c19a3ec6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-04soc/amd/cezanne/include/cppc: use AMD_CEZANNE_CPPC_H as include guardFelix Held
This makes this header file consistent with the rest. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ice2872b4a24032d3a65777795943602cd2595de7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-04soc/mediatek/mt8186: Add NOR-Flash supportRex-BC Chen
Add NOR-Flash drivers to pass verification of flash at verstage. TEST=boot to romstage BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If51d765e1fd4895f97898710ec6fa1374e1048fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58837 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek/mt8186: Add GPIO driversGuodong Liu
Add GPIO drivers to let other module control GPIOs. TEST=build pass BUG=b:202871018 Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> Change-Id: Ice342ab94397db8bc0fbbeb8fb5ee7e19de871ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/58836 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek/mt8186: Initialize watchdogRex-BC Chen
MT8186 requires writing speical value to mode register to clear status register. The flow of clear status is different from other platforms, so we override mtk_wdt_clr_status() for MT8186. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I290b69573a8e58db76814e16b5c17c23413f1108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58835 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek: Add an overridable function for WDT clear statusRex-BC Chen
mtk_wdt_clr_status is different for MT8186 and MT8195, so we move this function to soc folder. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia8697ffdca1e2d1443f2259713c4ab6fdf1b1a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58834 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/amd/cezanne/include/aoac_defs: drop leading newlineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8458fbee7edd19117a207f39ac8f9575b1374fbc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03soc/amd/cezanne/include: replace PICASSO with CEZANNE in include guardsFelix Held
Somehow missed renaming those when creating the coreboot support for Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I13c28f67d32ba987987cfc2b45e248d535ccdca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03soc/amd/*/cpu: handle mp_init_with_smm failureFelix Held
When the mp_init_with_smm call returns a failure, coreboot can't just continue with the initialization and boot process due to the system being in a bad state. Ignoring the failure here would just cause the boot process failing elsewhere where it may not be obvious that the failed multi-processor initialization step was the root cause of that. I'm not 100% sure if calling do_cold_reset or calling die_with_post_code is the better option here. Calling do_cold_reset likely here would likely result in a boot-failure loop, so I call die_with_post_code here. BUG=b:193809448 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifeadffb3bae749c4bbd7ad2f3f395201e67d9e28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03cpu/amd/mtrr: Remove topmem global variablesArthur Heymans
The comments are not correct anymore. With AGESA there is no need to synchronize TOM_MEMx msr's between AP's. It's also not the best place to do so anyway. Change-Id: Iecbe1553035680b7c3780338070b852606d74d15 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-03cpu/x86/Kconfig: Remove unused CPU_ADDR_BITSArthur Heymans
Change-Id: I88f62c18b814ac0ddd356944359e727d6e3bba5a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2021-11-03soc/amd/stoneyridge/cpu: remove unneeded line break in get_cpu_countFelix Held
The line length is no longer limited to 80 characters, so there's no need for that line break any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7a8fb472f00e039f25a71ee526a3dd0bc6c754f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03soc/intel/xeon_sp: disable PM ACPI timer if chosenMichael Niewöhner
Disable the PM ACPI timer during PMC init, when `USE_PM_ACPI_TIMER` is disabled. This is done to bring SKL, CNL, DNV in line with the other platforms, in order to transition handling of the PM timer from FSP to coreboot in the follow-up changes. Disabling is done in `finalize` since FSP makes use of the PMtimer. Without PM Timer emulation disabling it too early would block. Change-Id: If85c64ba578991a1b112ceac7dd10276b58b0900 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2021-11-03soc/intel/alderlake: Allow devicetree override to leave some VR settings as ↵Bora Guvendik
default Allow devicetree override to leave ac_loadline, dc_loadline and icc_max as default. Test=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I715345d5ea83aed9ee929b2a4e13921c9d8895b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-03soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoCRex-BC Chen
Add new folder and basic drivers for Mediatek SoC 'MT8186'. Difference of modules including in this patch between MT8186 and existing SoCs: Timer: Similar to MT8195, MT8186 uses v2 timer. EMI/PLL/SPI: Different from existing SoCs. TEST=boot from SPI-NOR and show uart log on MT8186 EVB BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58640 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek/mt8195: move timer enum variables to timer_v2.hRex-BC Chen
Some enum variables of timer v2 are the same between MT8195 and MT8186, so we move them to common timer_v2.h. TEST=emerge-cherry coreboot BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I89891a19e622aa24783025e73c38c4ffa43aa166 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58829 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek/mt8195: add apusys init flowFlora Fu
Set up APU mbox's functional configuration registers. BUG=b:203145462 BRANCH=cherry TEST=boot cherry correctly Signed-off-by: Flora Fu <flora.fu@mediatek.com> Change-Id: I5053d5e1f1c2286c9dce280ff83e8b8611b573b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58794 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02soc/intel/denverton_ns: Fetch addr bits at runtimeArthur Heymans
Change-Id: Ic46a7d56cbaf45724ebc2a1911f5096af2fe461a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-02include/device/pci_ids,soc/amd/common/block/lpc: drop duplicate PCI IDsFelix Held
PCI_DEVICE_ID_AMD_FAM17H_LPC and PCI_DEVICE_ID_AMD_FAM17H_SMBUS redefine the same values that are already defined by PCI_DEVICE_ID_AMD_CZ_LPC and PCI_DEVICE_ID_AMD_CZ_SMBUS, so drop PCI_DEVICE_ID_AMD_FAM17H_LPC and PCI_DEVICE_ID_AMD_FAM17H_SMBUS. Also add some comments to the places in the code where the defines are used to clarify which ID is used on which hardware generation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id0b3d7b5a886ccc76d82ada6be4145e85fd51ede Reviewed-on: https://review.coreboot.org/c/coreboot/+/58696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-02soc/amd/common/block/cpu: Add support for cbfs_cache regionRaul E Rangel
This change adds the cbfs_cache region into the x86 memlayout. The SoC or mainboard can decide how big the region should be by specifying CBFS_CACHE_SIZE. BUG=b:179699789 TEST=Build guybrush and verify cbfs_cache region wasn't added. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I268b6bc10906932ee94f795684a28cfac247a68c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-02psp_verstage: convert relative address in EFS2Kangheui Won
Addresses in AMD fw table with EFS gen2 are relative addresses, but PSP doesn't accept relative addresses in update_psp_bios_dir(). Check for EFS gen2 and convert them as needed. BUG=b:194263115 TEST=build and boot on guybrush and shuboz Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I95813beba7278480e6640599fcf7445923259361 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-02lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width()Subrata Banik
Add DDR5 and LPDDR5 memory type checks while calculating bus width extension (in bits). Additionally, update all caller functions of smbios_bus_width_to_spd_width() to pass `MemoryType` as argument. Update `test_smbios_bus_width_to_spd_width()` to accommodate different memory types. Create new macro to fix incorrect bus width reporting on platform with DDR5 and LPDDR5 memory. With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit primary bus width per Ch showed the Total width as: Handle 0x000F, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 80 bits Data Width: 64 bits Size: 16 GB ... BUG=b:194659789 Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`. Change-Id: I79ec64c9d522a34cb44b3f575725571823048380 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-01soc/intel: Don't send CSE EOP if CSME is disabledSean Rhodes
CSE EOP will fail if the CSE is disabled (CB:52800) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic00fdb0d97fefac977c0878d1d5893d07d4481ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/57149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-01soc/intel/braswell: Set GNVS DPTE via devicetreeAngel Pons
Introduce the `dptf_enable` devicetree setting to set the DPTE GNVS field, as newer Intel platforms do. Change-Id: I88b746c64ca57604f946eefb00a70487a2fb27c0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-01soc/intel/braswell/chip.h: Use `bool` typeAngel Pons
Use `bool` type where applicable. Change-Id: I4d5422c16381676738b8614e8e50737b59739921 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-01amd/lpc: Remove the weak functionZheng Bao
BUG=b:140165023 Change-Id: Idb4613dc08c8dee6c92b4dabb39c2f5c189471aa Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-01soc/intel/common/block/cse: Add get_me_fw_version functionJohnny Lin
Modify print_me_fw_version to get ME firmware version by calling it. Tested=On a not yet to be public platform, verified the function can get ME FW version successfully. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I50d472a413bcaaaa085955657bde6a0e6ec2c1db Reviewed-on: https://review.coreboot.org/c/coreboot/+/58520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-30lib: Use `smbios_bus_width_to_spd_width` for setting dimm.bus_widthSubrata Banik
Make use of `smbios_bus_width_to_spd_width()` for filling DIMM info. Additionally, ensures dimm_info_util.c file is getting compiled for romstage. TEST=dmidecode -t 17 output Total Width and Data Width as expected. Change-Id: I7fdc19fadc576dec43e12f182fe088707e6654d9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29soc/intel/alderlake: Add ACPI addition for USB4/TBT latency optimizationJohn Zhao
The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency optimization. This change adds additional ACPI DSM function with both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME to the USB4/TBT topology which has the same implementation on Tiger Lake in commit I5a19118b75ed0a78b7436f2f90295c03928300d7. BUG=b:199757442 TEST= It was validated that the first connected device waits only 50ms instead of 100ms and all functions work on Alder Lake platform boards. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I0c8977c96de27ab0e554469eba658660975b8493 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29soc/intel/apollolake: Fix BUG-message when checking for XDCI deviceWerner Zeh
The current check for XDCI enabled uses a static device path to an internal PCI device at a very late point in the boot flow. At this time the devicetree has been processed and disabled devices have been already removed. If this device (00:15.1, XDCI) is disabled in devicetree this will trigger the message 'BUG: check_xdci_enable requests hidden 00:15.1' in the log. This looks weird and is wrong since it is not a bug to disable this device when it is not needed. To avoid this look up the devicetree by a tree walk instead of using a static value for the devicetree. Change-Id: If193be724299c4017e7e10142fac8db9fac44383 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-29soc/intel/icelake: select SOC_INTEL_COMMON_BLOCK_ACPI_GPIOArthur Heymans
The Intel icelake rvp boards actually rely on this but this failure was hidden in a runtime error instead of a compile time error, due to weakly linked functions. Change-Id: Idbbe774efa1515ce1d34ce2ce8f87953300a3312 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58662 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-27soc/intel/common/acpi: Correct IPC sub command for reading LPM requirementEthan Tsao
Modify IPC sub command to 2 from 0 for reading LPM requirement from PMC. Reference: https://github.com/otcshare/CCG-ADL-Generic-Full ClientOneSiliconPkg\Include\Register\PmcRegs.h #define V_PMC_PWRM_IPC_SUBCMD_GEN_COMM_READ 2 It is consumed in below. ClientOneSiliconPkg\IpBlock\Pmc\Library\PeiDxeSmmPmcLib\PmcLib.c Change-Id: I58509f14f1e67472adda78e65c3a2e3ee9210765 Signed-off-by: Ethan Tsao <ethan.tsao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-27soc/amd/common/block/graphics: add missing GPU PCI IDsFelix Held
Since the iGPU PCI device IDs for AMD Renoir (family 17h, model 60h) and Lucienne (family 17h, model 68h) are already defined in pci_ids.h, also add them to the pci_device_ids list in the common AMD graphics support block. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1c554d21eece182ecea7b09b45b7aa8a733425d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26cpu/x86/Kconfig.debug_cpu: drop HAVE_DISPLAY_MTRRS optionFelix Held
Since all x86 CPUs in tree have MTRR support, there is no need to guard the DISPLAY_MTRRS option with HAVE_DISPLAY_MTRRS. Also all x86 CPUs/SoCs have a display_mtrrs call at least somewhere in their code, so selecting the DISPLAY_MTRRS option will always have an effect. All SoCs that don't select RESET_VECTOR_IN_RAM have the postcar stage where it gets called. The two AMD SoCs that select RESET_VECTOR_IN_RAM use the FSP2 driver which contains plenty of display_mtrrs calls. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2894689ce58e7404d9d5a894f3c288bc4016ea19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26soc/intel/quark/Kconfig: don't unselect CPU_X86_LAPICFelix Held
The Intel Quark SoC does have a LAPIC on its x86 CPU core, so we should select CPU_X86_LAPIC. This will additionally include the Makefile from cpu/x86/lapic. Since none of AP_IN_SIPI_WAIT, LEGACY_SMP_INIT and UDELAY_LAPIC gets selected, only the boot_cpu.c and lapic.c targets will be added to the build. Since SMP isn't set, adding the boot_cpu.c target won't change the resulting binary of a timeless build, since the only function inside will be removed by the compiler's pre-processor in the !SMP case. So the only thing that will change the resulting binary is the addition of the lapic.c target. From this target only the function cpu_get_lapic_addr will be used which overrides the weak implementation in acpi/acpi.c. The call in arch/x86/mpspec.c can be ignored, since GENERATE_MP_TABLE isn't selected. So this change will result in the LAPIC address in the MADT being changed from 0 to to LAPIC_DEFAULT_BASE. Since the documentation of the Quark SoC mentions that it has a LAPIC on its one x86 core, this should work. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2f163bd608f0548abb0e8de90843d2a796b8ef6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-26soc/intel/alderlake: set lock offset for gpio pad communitiesNick Vaccaro
Initialize the pad_cfg_lock_offset field for the various gpio pad_community structures in the adl_communities. BUG=b:201430600 TEST='emerge-brya coreboot' and verify it compiles successfully. Change-Id: I2cd3e43a84b0140bb2aeae5de1e299db714d419b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-26soc/intel: Update api name for getting spi destination idWonkyu Kim
Update api name and comments to be more generic as spi destination id is not DMI specific. Update api name as soc_get_spi_psf_destination_id and comments. And move PSF definition from pcr_ids.h as it's not pcr id. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ie338d05649d23bddae5355dc6ce8440dfb183073 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2021-10-26soc/example/min86/Kconfig: don't unselect CPU_X86_LAPICFelix Held
Since all multi-core x86 CPUs need to have LAPICs, this option should be selected for soc/example/min86. TEST=The example/min86 mainboard still builds. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5aa6e850f0b4dca27309385ba889b04335fe4f0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26cpu/x86: Introduce and use `CPU_X86_LAPIC`Felix Held
With using a Kconfig option to add the x86 LAPIC support code to the build, there's no need for adding the corresponding directory to subdirs in the CPU/SoC Makefile. Comparing which CPU/SoC Makefiles added (cpu/)x86/mtrr and (cpu/)x86/lapic before this and the corresponding MTRR code selection patch and having verified that all platforms added the MTRR code on that patch shows that soc/example/min86 and soc/intel/quark are the only platforms that don't end up selecting the LAPIC code. So for now the default value of CPU_X86_LAPIC is chosen as y which gets overridden to n in the Kconfig of the two SoCs mentioned above. Change-Id: I6f683ea7ba92c91117017ebc6ad063ec54902b0a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26soc/*/Makefile: don't add cpu/x86/cacheFelix Held
No SoC uses the ramstage-only x86_enable_cache helper function to call enable_cache with some added port 0x80 and console output. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I7c5039e1341fd4089078ad7ffb2fe6584a94045c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26soc/intel/common: Add HECI Reset flow in the CSE driverSridhar Siricilla
This change is required as part of HECI Interface initialization in order to put the host and CSE into a known good state for communication. Please refer ME BIOS specification for more details. The change adds HECI interface reset flow in the CSE driver. It enables coreboot to send HECI commands before DRAM Init. BUG=b:175516533 TEST=Run 50 cold reset cycles on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ie078beaa33c6a35ae8f5f460d4354766aa710fba Reviewed-on: https://review.coreboot.org/c/coreboot/+/55363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-26soc/intel/adl: Skip sending MBP HOB to save boot timeMAULIK V VAGHELA
MBP Hob is being generated by FSP after getting data from ME. coreboot does not consume this HOB and FSP provides an option for bootloader to skip generation of MBP HOB. This will help in saving ~14 ms of boot time. Here is the data from Brya P1 Board: Before: 955 returning from FspSiliconInit 879,432 (99,156) After: 955 returning from FspSiliconInit 1,177,513 (84,506) BUG=b:188577893 BRANCH=None TEST=No functional impact on Brya system and boot time is reduced with this patch. Change-Id: Ibb64e4d0f4ae7212defb6704b05a78e754f75cd7 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58289 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-25sc7280: Add AOP FW download supportRavi Kumar Bokka
AOP firmware support from sc7280. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: Ib7027cdf78a9cdcccc8cfff7eef3cc540fb4093e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-25soc/qualcomm: Commonize AOP firmware supportRavi Kumar Bokka
Move AOP firmware support from qualcomm/sc7180 into qualcomm/common BUG=b:182963902 TEST=Validated on qualcomm sc7180 development board Change-Id: I90b0f48e15df390970e027bff2065b7a89b14cec Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-25soc/qualcomm/sc7280: define the aop symbolsRavi Kumar Bokka
BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I62044f6fcb301c0ca35c42598f998913f9b94b95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-25soc/amd/common/block/lpc/Makefile: simplify handling spi_dma.cFelix Held
Use the verstage_x86 class for the spi_dma.c target instead of using the verstage class and guarding it with !VBOOT_STARTS_BEFORE_BOOTBLOCK. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b8cafd1ef17df8c485f6594bc0928cea88e436b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-25cpu,soc/amd/*/Makefile: don't add cpu/x86/pae a second timeFelix Held
Since cpu/x86/Makefile.inc already adds the pae sub-directory, there is no need to include it in the Makefile of a CPU or SoC, so remove it from those Makefiles. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I78368f7eb880fb64f511a2fa8c8acde222d0dca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-25cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCsFelix Held
All x86-based CPUs and SoCs in the coreboot tree end up including the Makefile in cpu/x86/mtrr, so include this directly in the Makefile in cpu/x86 to add it for all x86 CPUs/SoCs. In the unlikely case that a new x86 CPU/SoC will be added, a CPU_X86_MTRR Kconfig option that is selected be default could be added and the new CPU/SoC without MTRR support can override this option that then will be used in the Makefile to guard adding the Makefile from the cpu/x86/mtrr sub-directory. In cpu/intel all models except model 2065X and 206AX are selcted by a socket and rely on the socket's Makefile.inc to add x86/mtrr to the subdirs, so those models don't add x86/mtrr themselves. The Intel Broadwell SoC selects CPU_INTEL_HASWELL and which added x86/mtrr to the subdirs. The Intel Xeon SP SoC directory contains two sub-folders for different versions or generations which both add x86/mtrr to the subdirs in their Makefiles. Change-Id: I743eaac99a85a5c712241ba48a320243c5a51f76 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-25soc/intel/common: Skip CSE post hook when CSE is disabledSubrata Banik
This patch fixes regression introduced by commit bee4bb5f0 (soc/intel/common/cse: Late sending EOP msg if !HECI_DISABLE_USING_SMM) FAFT test case fail when doing `firmware_DevMode` test. If CSE is already hidden then accessing CSE registers would be wrong and will receive junk, hence, return as CSE is already disabled. BUG=b:203061531 TEST=Brya system can boot to OS with recovery mode. Change-Id: I2046eb19716c397a066c2c41e1b027a256bd6cf9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-22soc/amd/cezanne,picasso/chipset.cb: drop LAPIC deviceFelix Held
After adding code to handle the case of missing the link/bus on the CPU cluster device in mp_cpu_bus_init, there's no need to have the LAPIC device in the devicetree any more. TEST=Mandolin still boots successfully. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icfc4fb61b373129f3bf4f4de09c38076a8f66733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22soc/intel/denverton_ns: use mp_cpu_bus_initFelix Held
After adding the functionality to add a bus/link on the CPU cluster device in mp_cpu_bus_init if it is missing due to no LAPIC device being present in the devicetree below the CPU cluster device, we can use mp_cpu_bus_init as init function in cpu_bus_ops and implement mp_init_cpus. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I76aebeca1b3227cfd310b6c45f506c042b35ae04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22soc/intel/elkhartlake: Add PSE PCI devices into header fileLean Sheng Tan
Since PSE devices could be initialized as either host owned (PCI devices) or PSE owned (will be hidden from coreboot and only visible to PSE interface), add all PSE devices in PCI list header file for future usage. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Iaa40cdcb021d05e50504dd85f94e9c021e284d00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58466 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-22arch/x86/ioapic: Select IOAPIC with SMPKyösti Mälkki
For coreboot proper, I/O APIC programming is not really required, except for the APIC ID field. We generally do not guard the related set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC). In practice it's something one cannot leave unselected, but maintain the Kconfig for the time being. Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22sb,soc/intel: Replace set_ioapic_id() with setup_ioapic()Kyösti Mälkki
This adds delivery of PIC/i8259 interrupts via ExtNMI on the affected platfoms. Change-Id: If99e321fd9b153101d71e1b995b43dba48d8763f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-22sb,soc/intel: Set IOAPIC max entries before APIC IDKyösti Mälkki
This allows to replace set_ioapic_id() call with setup_ioapic() that also clears redirection table entries. Change-Id: I854f19c997a96bcdccb11a0906431e3291788cb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-22sb,soc/intel: Set IOAPIC redirection entry countKyösti Mälkki
The number of redirection table entries (aka interrupt vectors) inside an I/O APIC may depend of the SKU, with the related register being of type read/write-once. Provide support utilities to either lock or set this registers value. Change-Id: I8da869ba390dd821b43032e4ccbc9291c39e6bab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-22soc/intel/braswell: use mp_cpu_bus_initFelix Held
Implement mp_init_cpus and use mp_cpu_bus_init as init function in cpu_bus_ops. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2adcb1e1d79ced804925c81095cc5c0c2e6f9948 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22soc/intel/baytrail: use mp_cpu_bus_initFelix Held
Implement mp_init_cpus and use mp_cpu_bus_init as init function in cpu_bus_ops. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I057ae8d95bdc510e9e7afb144b692531107fa45d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22cpu/x86/mp_init: move printing of failure message into mp_init_with_smmFelix Held
Each CPU/SoC checks the return value of the mp_init_with_smm and prints the same error message if it wasn't successful, so move this check and printk to mp_init_with_smm. For this the original mp_init_with_smm function gets renamed to do_mp_init_with_smm and a new mp_init_with_smm function is created which then calls do_mp_init_with_smm, prints the error if it didn't return CB_SUCCESS and passes the return value of do_mp_init_with_smm to its caller. Since no CPU/SoC code handles a mp_init_with_smm failure apart from printing a message, also add a comment at the mp_init_with_smm call sites that the code might want to handle a failure. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I181602723c204f3e43eb43302921adf7a88c81ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/58498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22cpu/x86/mp_init: use cb_err as status return type in remaining functionsFelix Held
Using cb_err as return type of mp_run_on_aps, mp_run_on_all_aps, mp_run_on_all_cpus and mp_park_aps clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of all 4 functions listed above against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b3f03415a041d3ec9cd0e102980e53868b004b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-21soc/amd/common/block/cpu/smm/finalize: simplify finalize_coresFelix Held
The local variable int r isn't needed, so remove it. This is a preparation to change the return type of mp_run_on_all_cpus from int to enum cb_err which will be done in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie4c454cbfcc581be41ea3463ea6f852a72886128 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21soc/intel/skylake/cpu: rework failure handling in post_mp_initFelix Held
Use a boolean type to store the information if any mp_run_on_all_cpus call failed. This is a preparation to change the return type of mp_run_on_all_cpus from int to enum cb_err which will be done in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic04ad3e4a781a00ee6edcd7dbd24bc7601be1384 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as mp_init_with_smm return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of mp_init_with_smm against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibcd4a9a63cc87fe176ba885ced0f00832587d492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC tableMichael Niewöhner
Some elements in the ACPI CPPC table allow static DWORDs. Instead of using a fake register resource, use a tagged union with the two types "register" and "DWORD" and respective macros for CPPC table entries. Test: dumped SSDT before and after do not differ. Change-Id: Ib853261b5c0ea87ae2424fed188f2d1872be9a06 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-20soc/amd/common/block/cpu: Remove magic number in memlayoutRaul E Rangel
The SPI DMA controller can only perform transactions on a cache line boundary. This change removes the magic number and uses the #define to make it clear. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie7b851dc2433e44a23224c3ff733fdea5fbcca0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20soc/intel/alderlake: Fix wrong FIVR configs assignmentBora Guvendik
For PchFivrExtVnnRailSxEnabledStates, vnn_enable_bitmap config is used by mistake, instead of the expected vnn_sx_enable_bitmap Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Idf100be3ac4d6d97335c627e790c1870558d1210 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20psp_verstage: remove psp_ef_table structKangheui Won
psp_efs.h now has embedded_firmware struct which is copied from amdfwtool. Remove psp_ef_table from psp_verstage and use it instead to remove duplicates. TEST=boot on zork and guybrush Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ia362445cb7fc565b2d963f264461d833dc0338d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-20soc/intel/{skl,apl}: don't run or even include SGX code if disabledMichael Niewöhner
Do not run or include any code in case the user did not explicitly enable SGX through `SOC_INTEL_COMMON_BLOCK_SGX_ENABLE`. Also move the ifdef inside the ASL file. Change-Id: Iec4d3d3eb2811ec14d29aff9601ba325724bc28c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-10-19soc/intel/skl: Constify `soc_get_cstate_map()`Patrick Georgi
This is a follow-up to commit e9f10ff38b which changed the base signature and all other occurrences. To make gcc11 happy (which is pickier about these things), let skylake follow. Change-Id: I42a629d865baa53640213a03e54e85623a386e35 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58458 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-19soc/intel/common/block/cse: Use newly added `create-cse-region`Furquan Shaikh
This change uses the newly added `create-cse-region` command for cse_serger tool instead of performing `dd` operations for each partition. BUG=b:189177580 Change-Id: Ia915e3ac423f9461876e9ae186fb8ddce55f3194 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19soc/intel/common/cse: Support RW update when stitching CSE binaryFurquan Shaikh
This change updates the STITCH_ME_BIN path to enable support for including CSE RW update in CBFS. CSE_RW_FILE is set to either CONFIG_SOC_INTEL_CSE_RW_FILE or CSE_BP2_BIN depending upon the selection of STITCH_ME_BIN config. BUG=b:189177580 Change-Id: I0478f6b2a3342ed29c7ca21aa8e26655c58265f4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19soc/intel/alderlake: Enable support for CSE stitchingFurquan Shaikh
This change enables support for stitching of BP1 and BP2 partitions for CSE. This currently mimics what Intel FIT tool does w.r.t. adding different components to the different partitions. BP1: * Dummy components: DLMP, IFPP, SBDT, UFSP, UFSG, OEMP. * Decomposed components from CSE FPT file: RBEP, MFTP. * Input components: PMCP, IOMP, NPHY, TBTP, PCHC. BP2: * Dummy components: DLMP, IFPP, SBDT, UFSP, UFSG, OEMP, ISHP. * Decomposed components from CSE FPT file: RBEP, FTPR, NFTP. * Input components: PMCP, IOMP, NPHY, TBTP, PCHC, IUNP. BUG=b:189177580,b:189177538 Change-Id: I2b14405aab2a4919431d9c16bc7ff2eb1abf1f6b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19soc/intel/common/cse: Add support for stitching CSE componentsFurquan Shaikh
This change adds support for allowing mainboards to stitch CSE components during build time instead of adding a pre-built CSE binary. Several Kconfig options are added to allow mainboard to provide the file names for different CSE region components. This makes use of the newly added cse_serger and cse_fpt tools to create following partitions: 1. BP1 - RO 2. BP2 - RW 3. Layout In addition to this, it accepts CSE data partition as an input using Kconfig CSE_DATA_FILE. All these partitions are then assembled together as per the following mainboard FMAP regions: 1. BP1(RO) : CSE_RO 2. BP2(RW) : CSE_RW 3. Layout : CSE_LAYOUT 4. Data : CSE_DATA Finally, it generates the target $(OBJ_ME_BIN) which is used to put together the binary in final coreboot.rom image. Several helper functions are added to soc/intel/Makefile.inc to allow SoCs to define which components use: 1. Decomposed files: Files decomposed from Intel release CSE binary in FPT format. 2. Input files: Mainboard provided input files using corresponding Kconfigs. 3. Dummy: Components that are required to have dummy entries in BPDT header. These helpers are added to soc/intel/Makefile.inc to ensure that the functions are defined by the time the invocations are encountered in SoC Makefile.inc. BUG=b:189177580 Change-Id: I8359cd49ad256703285e55bc4319c6e9c9fccb67 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19soc/intel: Constify `soc_get_cstate_map()`Angel Pons
Return a read-only pointer from the `soc_get_cstate_map()` function. Also, constify the actual data where applicable. Change-Id: I7d46f1e373971c789eaf1eb582e9aa2d3f661785 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-19acpi/acpigen: Constify CST functions' pointersAngel Pons
The `acpigen_write_CST_package` and `acpigen_write_CST_package_entry` functions don't modify the provided C-state information. So, make the pointer parameters read-only to enforce this. Also constify arguments where possible. Change-Id: I9e18d82ee6c16e4435b8fad6d467e58c33194cf4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-19soc/intel/*/acpi.c: Don't copy structs with `memcpy()`Angel Pons
A regular assignment works just as well and also allows type-checking. Change-Id: Id772771f000ba3bad5d4af05f5651c0f0ee43d6d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-19soc/amd/common/block/include/psp_efs: don't typedef structFelix Held
Don't use a typedef for the embedded_firmware struct so that it's clearer that this is a struct. TEST=Timeless build for google/guybrush results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97a02c350af57c8f58014aaf7dda8b4796905ff3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-10-19soc/amd/common/block/include/psp_efs: rename embedded_firmware elementsFelix Held
The element at offset 0x14 in the embedded_firmware struct is the pointer to the combo PSP directory header, so rename it from comboable to combo_psp_directory to clarify that this is not a flag, but a pointer to a data structure. Also rename psp_entry to psp_directory since it points to the PSP directory table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia70e97f10f4fa0ac63cc65a33ecdc956538482b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-10-18sc7280: Add GSI FW download supportRavi Kumar Bokka
Add GSI Firmware download support for QUP wrappers. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I68c106c942acadc752351f03843d93612cf9c19f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-18ACPI: Have common acpi_fill_mcfg()Kyösti Mälkki
As long as there is only one PCI segment we do not need more complicated MCFG generation. Change-Id: Ic2a8e84383883039bb7f994227e2e425366f9e13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-18intel/tigerlake: Add missing IRQ for CNViSean Rhodes
Add CNVi (14.3) to IRQ Table to stop dmesg error: iwlwifi 0000:00:14.3: can't derive routing for PCI INT F iwlwifi 0000:00:14.3: PCI INT F: not connected Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5b793997f9ea954217871eb4656dacf6abe77e74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-18soc/skylake: Make VT-d controllable from CMOS optionSean Rhodes
Make VT-d enable or disable based on CMOS value "vtd" 1 = Enable 0 = Disable Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1aea14968e08ee6af822bd259ca1d462f8926994 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel/skylake: switch to common ACPI codeMichael Niewöhner
Use the common ACPI code to reduce code duplication. After this change, `PSS_MAX_ENTRIES` is honored correctly in P-state table generation (as of commit c2540a9) and the number reduces from 10 to 7 entries. Also, remnants of P_BLK support missed in CB:58096 will vanish. Tested on google/fizz: no errors in dmesg, ACPI tables remain the same (except PSS, as mentioned above). Change-Id: I1ec804ae4006a2d9b69c0d93a658eb3b84d60b40 Tested-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-10-17soc/intel/{common,apl,glk}: guard PM Timer option on SoCs w/o PM TimerMichael Niewöhner
Apollo Lake and Gemini Lake do not have a hardware PM ACPI timer but only uCode PM Timer emulation. Add a Kconfig `NO_PM_ACPI_TIMER` denoting SoCs without PM Timer and make it mutually exclusive with the Kconfig `USE_PM_ACPI_TIMER`. This is partly redundant to `PM_ACPI_TIMER_OPTIONAL`, which will be dropped in the follow-up change, though. Change-Id: Ic323bbfb7089c53a6f22724910a0ff3df8904ebd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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