summaryrefslogtreecommitdiff
path: root/src/soc
AgeCommit message (Collapse)Author
2016-02-12tegra132/pistachio: Increase romstage size in memlayout.ldJulius Werner
These SoCs have come within a kilobyte of their romstage limit, so let's expand that a little to make room for future core code contributions. (In the Tegra case just by copying the layout from Tegra210, because why not? Keeps things simple.) BRANCH=None BUG=None TEST=Ran abuild with and without --chromeos for Foster, Rush, Ryu, Smaug and Urara. Change-Id: If8c1ea81cf9827412c78d67a09d54e7a2dc044ac Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13668 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-12tegra132/210: Remove memlayout_vboot2.ldJulius Werner
Having two separate memlayouts is an unnecessary complication. Contributors need to make sure that their code fits into the vboot one (with smaller stage sizes) either way, and the Tegras have plenty of SRAM anyway. Let's just make the vboot layout the default (as it was done on other SoCs) to keep things easier to maintain. The empty SRAM holes on non-vboot systems where the verstage and work buffer would've been won't hurt them. BRANCH=None BUG=None TEST=Ran abuild with and without --chromeos on Foster, Rush, Ryu and Smaug. Change-Id: If37228facb4de1459cc720dca10bf03e04eb9930 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13667 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-12timestamp: Remove HAS_PRECBMEM_TIMESTAMP_REGION KconfigJulius Werner
This patch generalizes the approach previously used for ARM32 TTB_SUBTABLES to "auto-detect" whether a certain region was defined in memlayout.ld. This allows us to get rid of the explicit Kconfig for the TIMESTAMP region, reducing configuration redundancy and avoiding confusion when setting up future boards. (Removing armv4/bootblock_simple.c because it references this Kconfig and it is a dead file that I just forgot to remove in CL:12076.) BRANCH=None BUG=None TEST=Booted Oak and confirmed that all pre-RAM timestamps are still there. Built Nyan and Falco. Change-Id: I557a4b263018511d17baa4177963130a97ea310a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13652 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11arches: lib: add main_decl.h for main() declarationAaron Durbin
It is silly to have a single header to declare the main() symbol, however some of the arches provided it while lib/bootblock.c relied on the arch headers to declare it. Just move the declaration into its own header file and utilize it. Change-Id: I743b4c286956ae047c17fe46241b699feca73628 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13681 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-02-11soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLEAndrey Petrov
Early UART driver is for bootblock and romstage. It is supposed to be used when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits in bootblock requiered for serial to be set up. Change-Id: I15520d566f107797e68d618885d4379e73d0fa45 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13677 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11soc/apollolake: Add minimal GPIO driverAndrey Petrov
This adds the minimal functionality needed to configure SoC pads. Change-Id: I2e2268eee2b8c822b42a48a95604b0fab86c9833 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13676 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-02-11soc/apollolake: Add initial cache-as-ram setup for bootblockAlexandru Gagniuc
This is the minimum setup needed to both get cache-as-ram setup and a C environment working. On apollolake, we only get 32 KiB of data loaded into an SRAM that is readonly to the main CPU. Due to this restriction we have to set CAR and a C environment very early on. Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13301 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-11util/marvell: Add Marvell doimage utility and dependency in relevant MakefileRuilin Hao
- Add the doimage sources in util/marvell - Add dependency in root makefile - Add dependency in makefile for armada38x soc BUG=chrome-os-partner:47462 TEST=emerge-cyclone coreboot BRANCH=tot Change-Id: I81b30e0865cbd619a41659c3f2819ad3bafc5f24 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4b2a990150580e0b879a346ed8b71b3765b66bab Original-Change-Id: I7e89b5e96206fde97ce69c296850122fd6c858f9 Original-Signed-off-by: Kefei Yao <kfyao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/318046 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org> Reviewed-on: https://review.coreboot.org/13137 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-10Kconfig: Move defaults for CBFS_SIZEMartin Roth
We want the question for CBFS size to be next to the rom size in the mainboard directory, but that doesn't seem to work for how people want to set the defaults. Instead of having the list of exceptions to the size, just set the defaults at the end of kconfig. - Move the defaults for chipsets not setting HAVE_INTEL_FIRMWARE into the chipset Kconfigs (gm45, nehalem, sandybridge, x4x) - Override the default for HAVE_INTEL_FIRMWARE on skylake. - Move the HAVE_INTEL_FIRMWARE default setting into the firmware Kconfig file - Move the location of the default CBFS_SIZE=ROM_SIZE to the end of the top level kconfig file, while leaving the question where it is. Test=rebuild Kconfig files before and after the change, verify that they are how they were intended to be. Note: the Skylake boards actually changed value, because they were picking up the 0x100000 from HAVE_INTEL_FIRMWARE instead of the 0x200000 desired. This was due to the SOC_INTEL_SKYLAKE being after the HAVE_INTEL_FIRMWARE default. Affected boards were: Google chell, glados, & lars and Intel kunimitsu. Change-Id: I2963a7a7eab037955558d401f5573533674a664f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-10soc/intel/quark: Report CPU infoLee Leahy
Decode the CPU variants and display the CPU info. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Successful if Quark X1000 is displayed Change-Id: I7234a6d81a48cdd02708b80663147e2b09ba979e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13605 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-10soc/intel/quark: Call FSP SiliconInitLee Leahy
Optionally relocate FSP into DRAM and then call FSP SiliconInit. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select DISPLAY_FSP_ENTRY_POINTS" * Add "select DISPLAY_HOBS" * Optionally add "select RELOCATE_FSP_INTO_DRAM" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * FSP entry points are displayed and * The message "FspSiliconInit returned 0x00000000" is displayed and * The HOBs are displayed correctly and * The message "ERROR - Missing one or more required FSP HOBs!" is not displayed Change-Id: I91e660ea373a8bb00fc97fe8b760347cbfa96b1e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13631 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-10soc/intel/quark: MTRR supportLee Leahy
Add the SoC specific routines to access the MTRR registers. These registers exist in the host bridge and are not accessible via the rdmsr/wrmsr instructions. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select DISPLAY_MTRRS" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The message "FSP TempRamInit successful" is displayed Change-Id: I7c124145429ae1d1365a6222a68853edbef4ff69 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13530 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-10soc/fsp_baytrail: Add support for FSP MR 005Ben Gardner
Baytrail FSP MR 005 adds two new fields: AutoSelfRefreshEnable APTaskTimeoutCnt Add the device tree definitions. Change-Id: I12e2a8b0b5cbeb6b7289cf91f65b25e73007a8de Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12973 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com>
2016-02-10soc/intel/quark: FSP MemoryInit SupportLee Leahy
Add a dummy fill_power_state routine so that execution is able to reach FSP MemoryInit. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select DISPLAY_HOBS" * Add "select DISPLAY_UPD_DATA" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * MemoryInit returns 0 (success) and * The the message "ERROR - Coreboot's requirements not met by FSP binary!" is not displayed Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13447 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09rockchip/rk3288: UART uses 32bit wide registersPatrick Georgi
Change-Id: I084eb4694a2aa8f66afc1f3148480608ac3ff02b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13635 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-09intel/skylake: Add gpio macro for unused GPIO pinsdavid
Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and GPIO TX/RX will be disabled. BUG=none BRANCH=none TEST=Build and boot lars Change-Id: I3a6fcd2f3462e8e0d1273aa80b1599b76b160825 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 889bfd66dbc918e9fb0ba1b95b63fd7a3bf180d9 Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319964 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/13628 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09soc/intel/quark: Enable Serial PortLee Leahy
Add the code to enable debug serial output using HSUART1: * Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1 * Note that the BIST value is always zero as validated in esram_init.inc * The initial TSC value is currently not saved! Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if serial output is present on HSUART1 at 115200 baud, 8-bit, no parity Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13445 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-09nhlt: add api to override oem_id and oem_table_id of acpi_header_tFang, Yang A
This patch added nhlt_soc_serialize_oem_overrides and nhlt_serilalize_oem_overrides to be able to override oem_id and oem_table_id.board file can pass specific string by calling nhlt_soc_serialize_oem_overrides kernel use these two fields to construct a topology binary name if the designate file is not found a default dfw_sst.bin will be used it is optional. BUG=chrome-os-partner:49570 BRANCH=glados TEST=Build & Booted kunimitsu board. Verified that kernel can read new strings. Change-Id: I00b64fb8bb63de601d3116e0b8941057c1efa230 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 374ce08b2d8a2f4e5dd7f51eacb505dbb77fd171 Original-Change-Id: I03623c8ac81efb5a5ea3ec9c6cd604d2e9294022 Original-Signed-off-by: Fang, Yang A <yang.a.fang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/322860 Original-Commit-Ready: Yang Fang <yang.a.fang@intel.com> Original-Tested-by: Yang Fang <yang.a.fang@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13602 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09chromeos: Remove CONFIG_VBNV_SIZE variableDuncan Laurie
The VBNV region size is determined by vboot and is not really configurable. Only the CMOS implementation defined this config variable so switch it to use VBNV_BLOCK_SIZE defined by vboot in vbnv_layout.h instead. This requires updating the broadwell/skylake cmos reset functions to use the right constant. BUG=chrome-os-partner:47915 BRANCH=glados TEST=manually tested on chell Change-Id: I45e3efc2a22efcb1470bbbefbdae4eda33fc6c96 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e2b803ff3ac30ab22d65d1e62aca623730999a1d Original-Change-Id: I4896a1a5b7889d77ad00c4c8f285d184c4218e17 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324520 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13598 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-08soc/intel/quark: Add TempRamInit supportLee Leahy
Successfully invoke TempRamInit from the FSP binary: * Don't relocate the FSP binary image * Copy the FSP binary into ESRAM * Specify Kconfig values to easily debug ESRAM and TempRamInit code * Specify the FSP binary file location * Specify the FSP binary image ID * Specify where in the flash image the FSP image must reside * Specify the FSP data file location * Specify where to place the FSP data file in the flash image * Specify where in the ESRAM the FSP image must reside Test 1 on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select ENABLE_DEBUG_LED_FINDFSP" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if the SD LED is on indicating that the FSP.bin file was properly located, The test fails if the SD LED is flashing. Test 2 on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Remove "select ENABLE_DEBUG_LED_FINDFSP" * Add "select ENABLE_DEBUG_LED_TEMPRAMINIT" * Testing is successful if the SD LED is on indicating that the FSP.bin file was properly located, The test fails if the SD LED is flashing. Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13443 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-08soc/intel/quark: Enable ESRAMLee Leahy
The Quark SoC uses ESRAM instead of cache-as-RAM. This code requires that utils/xcompile/xcompile change the machine architecture from i686 to i586 to ensure that the Quark does not attempt to execute unsupported instructions: * Adjust Makefile.inc to add the RMU to the coreboot image * Add code to enable the ESRAM Directly use the QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h file from the EDK2 tree (https://github.com/tianocore/edk2.git) to enable easy differences and correct issues in coreboot that were found in EDK2. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_RMU_FILE" * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Remove power from the board * Apply power to the board * Testing is successful if the SD LED is on indicating that the end of esram_init.inc was reached Change-Id: I91d919da144bb72a5d4c4a8050ffab256632a395 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13440 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-04intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdownArchana Patni
Keeping ACPI PM timer alive prevents XTAL OSC shutdown in S0ix which has a power impact. Based on a DT variable, this patch disables the ACPI PM timer late in the boot sequence - disabling earlier will lead to a hang since the FSP boot flow needs this timer. This also hides the ACPI PM timer from the OS by removing from FADT table. Once the ACPI PM timer is disabled, TCO gets switched off as well. BRANCH=none BUG=chrome-os-partner:48646 TEST=Build for skylake board with the PmTimerDisabled policy in devicetree set to 1. iotools mmio_read32 0xfe0000fc should return 0x2. cat /sys/devices/system/clocksource/clocksource0/available_clocksource should list only "tsc hpet". acpi_pm should be removed from this list. Change-Id: Icfdc51bc33b5190a55196d67e18afdaaa2f9b310 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 18bcb8a434b029295e1f1cc925e2b47e79254583 Original-Change-Id: Ifebe8bb5a7978339e07e4e12e174b9b978135467 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319361 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13588 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04intel/skylake: unconditionally set SPI controller BARAaron Durbin
The setting of the SPI controller BAR was conditional on the nominal frequency being set. Therefore, that doesn't mean the SPI BAR is set on all boots. Move the setting of the BAR in the southbridge_bootblock_init() which is called prioer to cpu_bootblock_init(). BUG=chrome-os-partner:44827 BRANCH=None TEST=Confirmed spibar is always set on glados. Change-Id: Ia58447d70f5e39a4336d4d08593f143332de833a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 56fff7c25c2eb0ccd90e08f71c064b83c66640f8 Original-Change-Id: I1e0cff783f4b072b80589a3a84703a262b86be3a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/319461 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13587 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04intel/skylake: implement vboot_platform_prepare_reboot()Aaron Durbin
In order to not reboot loop in the face of failed vboot verification on resume set the PM1 control register to indicate S5. After the subsequent cold reset the PM1 control register will indicate S5 as it should. BUG=chrome-os-partner:46049 BRANCH=glados TEST=On chell injected failed vboot verification. Ensured a reboot loop doesn't ensue. Change-Id: Ie5e9e3f6441a217a5e02b4d78aaf21f8249b8a43 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a63b57d7bc59bcaf5518f7cc4afccd3d5da6df1c Original-Change-Id: I5e467854bf065a138bd46e476a7e7088f51454ca Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323504 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13579 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04intel/skylake: implement vboot_platform_is_resuming()Aaron Durbin
To allow skylake platforms to run with verified memory init code the chipset needs to implement vboot_platform_is_resuming() so that the vboot code can make proper decisions. BUG=chrome-os-partner:46049 BRANCH=glados TEST=Suspended and resumed on chell. Also, tested with an EC build which returns a bad hash to ensure that is properly caught. Change-Id: I508a339c07dcc9e7c56a0df4201660827b3ae07a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a3e11789339bcd8fc8fc99b704c6a1110acf5302 Original-Change-Id: I40264019eb28e85795258112c720056a6a3fc523 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323503 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13578 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04intel/skylake: Display ME firmware status before os bootDhaval Sharma
Display ME firmware status before os boot. Specifically this patch reads out the ME hfsts1 and hfsts2 status registers that provide information about overall ME health before device gets disabled. This change reused most of the code from bdw me_status implementation. BUG=chrome-os-partner:47384 BRANCH=glados TEST=Builds and Boots on FAB4 SKU2/3. Can observe me status table Change-Id: Ia511c4f336d33a6f3b49a344bfbaea6ed227ffeb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a9d0fb411c3921654f0fdcea2a3d4ee601987af2 Original-Change-Id: Ied7e2dcd9a1298a38dfe1eda9296b9ca8eccf6b1 Original-Credits-to: Duncan Laurie <dlaurie@chromium.org> Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/323260 Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma@intel.com> Original-Tested-by: dhaval v sharma <dhaval.v.sharma@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13573 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04soc/intel/quark: Add minimal Quark SoC X1000 filesLee Leahy
Add the files for minimal Quark X1000 SoC support: * Declare pei_data structure * Declare sleep states and chipset_power_state structure * Specify top of memory * Empty FspUpdVpd.h file TEST=None Change-Id: If741f84904394780e1f29bd6ddbd81514c3e21c9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13439 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04soc/marvell/armada38x: Add i2c driver for armada38xRuilin Hao
Port i2c driver from uboot to coreboot BUG=chrome-os-partner:47462 TEST=emerge-cyclone coreboot BRANCH=tot Change-Id: I8ce2a965acaed68ad0f0518648490ec471c6810b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c2e9592662787ebed1d0aa8cafaa00fd12c2e9c Original-Change-Id: If791228edf29405fa4b2f959a21510bd7da9865b Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313342 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/13113 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04soc/marvell/armada38x: Add gpio driver for armada38xRuilin Hao
Port gpio driver from uboot to coreboot BUG=chrome-os-partner:47462 TEST=None BRANCH=tot Change-Id: Ib6cfbb6e44cb642c7af937778076a51d405ff4a2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5cf94502faad96147d4a4adb42eb13edb64a6439 Original-Change-Id: Ia2e081a85347e2fc8bb365ca527ee2ee32af86f1 Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313341 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org> Reviewed-on: https://review.coreboot.org/13112 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04soc/marvell/armada38x: Add spi driver for armada38xRuilin Hao
Port spi driver from uboot to coreboot BUG=chrome-os-partner:47462 TEST=None BRANCH=tot Change-Id: I747be7001f4cfb8eec33e8e5bdef3fe5bb0eb2ca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9fbc5c2feb6ffacb54ed94e5c7b94b38be2b2ded Original-Change-Id: Ibea9a050ac8bdab6ce4eeb07accde53aeadade5f Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313340 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org> Reviewed-on: https://review.coreboot.org/13111 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04soc/marvell/armada38x: Add generic support for armada38xRuilin Hao
Skeleton for soc armada38x BUG=chrome-os-partner:47462 TEST=None BRANCH=tot Change-Id: I76f631ee6cdfc90c44727cb20aa960796bc785a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e91cc19468325f005c6ac920bbe27a174c409727 Original-Change-Id: Iac5fc34df1ba18b4515029aa2fcff8f78a5df191 Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313179 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Kan Yan <kyan@google.com> Reviewed-on: https://review.coreboot.org/13110 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-02soc/intel/common: Use SoC specific routine to read/write MTRRsLee Leahy
The registers associated with the MTRRs for Quark are referenced through a port on the host bridge. Support the standard configurations by providing a weak routines which just do a rdmsr/wrmsr. Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select DISPLAY_MTRRS" * Add "select HAVE_FSP_PDAT_FILE" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The MTRRs are displayed and * The message "FspTempRamExit returned successfully" is displayed TEST=Build and run on Galileo Change-Id: If2fea66d4b054be4555f5f172ea5945620648325 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13529 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-02Kconfig: indent with tabs, not spaces.Martin Roth
Change-Id: I8996f8ab739a07014a4189738b5624485d752d9d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13540 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-31drivers/intel/fsp1_1: Fix spelling error in API and copyrightLee Leahy
Change granluarity to granularity. Change wacbmem_entryanty to warranty. Update copyright dates. TEST=None Change-Id: Ib7775cb33616751760919a5850777dc6f77a6be9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13528 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-30soc/intel: Add skeleton infrastructure for Apollolake SOCAlexandru Gagniuc
This is the very very minimum needed to compile the code. Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13297 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-29soc/braswell: Fix Global NVS base addressHannah Williams
TEST=Boot to OS Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I9b43eb4f6f7af62a8a0bbe7bfa08feee1eaca24e Reviewed-on: https://review.coreboot.org/13506 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29src/: Chmod 644 all .c, .h, .asl, .inc, .cb, .hex, & Kconfig filesMartin Roth
Some trivial cleanup. Change-Id: I866efc4939b5e036ef02d1acb7b8bb8335671914 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13427 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-29intel/skylake: Implement native Cache-as-RAM (CAR)Subrata Banik
Now coreboot should do BIOS CAR setup along with NEM mode setup. This patch also provides a mechanism to use 16MB code caching benefit although LLC still limited to 1M/1.5M based on SOC LLC limit. Here with unlimited cache line gets replaced. Now we could use unlimited cache size along with well defined data size [pg: updated to current upstream #defines] BUG=chrome-os-partner:48412 BRANCH=glados TEST=Builds and Boots on FAB4 SKU2/3. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: pchandri <preetham.chandrian@intel.com> Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com> Change-Id: I96a9cf3a6e41cae9619c683dca28ad31dcaa2536 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2ec51f15c874ad2f1f4fad52fa8deced7b27a24b Original-Change-Id: Id62c15799d98bc27b5e558adfa7c7b3468aa153a Original-Reviewed-on: https://chromium-review.googlesource.com/320855 Original-Commit-Ready: Subrata Banik <subrata.banik@intel.com> Original-Tested-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13138 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Add interface to program USB2_COMPBG registershkim
Add interface to program USB2_COMPBG register to set HS_DISC_BG and HS_SQ reference voltage for each project. TEST=Get build success and do EFT test Original-Reviewed-on: https://chromium-review.googlesource.com/300846 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Original-Tested-by: shkim <sh_.kim@samsung.com> Change-Id: If2201829e1a16b4f9916547f08c24e9291358325 Signed-off-by: Kenji Chen <kenji.chen@intel.com> Signed-off-by: shkim <sh_.kim@samsung.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12739 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell/acpi/DPTF: Write TCHG state on AC connect.Jenny TC
DPTF should update the charger cooling device state during boot time and every 3 seconds after boot. But 3 seconds polling doesn't seems to be working with current version of DPTF. This impacts charging since DPTF writes states 4 when charger is not connected at boot time. On connecting the charger, DPTF doesn't write 0 to enable charging. This issue is addressed by calling the PPPC function to read cooling device state and passing the value to SPPC to set cooling device state. This doesn't compromise safety since DPTF can override this value later based on the platform thermal condition. Also this provides additional safety measure in the unlikely event that DPTF crashes and is not re-spawned by OS. With this patch even after DPTF crashes, if the power adapter is plugged it would still allow the system to charge correctly. Original-Reviewed-on: https://chromium-review.googlesource.com/288460 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Jenny Tc <jenny.tc@intel.com> Change-Id: I50c7666b86e45d5ab537a9d4149e6c71eba04e50 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12729 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell/acpi: Fix CID1 offset in commentHannah Williams
Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I9fd2ebba985362fe8068c10390bb014cf9015ac5 Reviewed-on: https://review.coreboot.org/13483 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Fix issues found during static code analysisRavi Sarawadi
TEST=Build, boot to OS Original-Reviewed-on: https://chromium-review.googlesource.com/299483 Original-Reviewed-by: Aaron Durbin <adurbin@google.com> Change-Id: I738003b8dfff6a5255085d39e378e18d6ad36bcf Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/12738 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28Braswell: Separate L1 Sub State init procedure for boards.Kenji Chen
Original-Reviewed-on: https://chromium-review.googlesource.com/312743 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: Ib0a891f229477cf359bff6cd02f305606468f07f Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: https://review.coreboot.org/12750 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28Strago: Enable CA MirrorShobhit Srivastava
Configuring UPD PcdCaMirrorEn. This is a board specific parameter. CA mirror is the Command Address mirroring option that is enabled on this board CQ-DEPEND=CL:13038 Original-Reviewed-on: https://chromium-review.googlesource.com/309190 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I05174e18d650332d838e5036c713e91c4840ee75 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12749 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Disable SD card detect simulation in FSPDivya Sasidharan
CQ-DEPEND=CL:13038 Debounce for SD card detect takes a long time and thus affects boot time. Disabling SD card detect simulation in FSP through UPD Original-Reviewed-on: https://chromium-review.googlesource.com/311850 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Iab0794ec058460df94f6bbed5c9b0911e57e3a71 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://review.coreboot.org/12742 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Set max frequency to be turbo frequencyHannah Williams
In set_max_freq, instead of using ratio from IA_CORE_RATIOS, using ratio from MSR_IACORE_TURBO_RATIOS Also, punit_init needs to be called before enabling this frequency. Original-Reviewed-on: https://chromium-review.googlesource.com/295268 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Iabdab9ec45f8eef0a105a5a05dbcdb997b6764b0 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12736 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Fix DSP clockfdurairx
The codec clock frequency was incorrectly set to 25MHz. The only available frequency is 19.2MHz through external clock and PLL. Original-Reviewed-on: https://chromium-review.googlesource.com/295768 Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5 Signed-off-by: Felix Durairaj <felixx.durairaj@intel.com> Reviewed-on: https://review.coreboot.org/12732 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28drivers/intel/fsp1_1: Remove extra include referencesLee Leahy
Remove include references to the soc include directory which are not required to build the FSP driver. Remove "duplicate" include file definitions from file that include fsp/romstage.h. Move the definition of fill_power_state into soc/pm.h to ensure it is still available. TEST=Build and run on Galileo Change-Id: Ie519b3a8da8c36b47da512d3811796eab62ce208 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13436 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-27soc/braswell: Fix leakage on V1P8S railShobhit Srivastava
Tristate MMC1_RCLK pin to fix leakage on V1P8S rail. Original-Reviewed-on: https://chromium-review.googlesource.com/292043 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Change-Id: I76cc9211ba93b2596d3c0d772d99f8934656e01c Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com> Reviewed-on: https://review.coreboot.org/12730 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-27soc/braswell: Add macro NATIVE_INT_PU20KHannah Williams
Change-Id: I04db02d37a76f0643a73ae4d67b839e5cd61f7e3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13054 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-26Braswell: Implement Gpio library functions to read RAMIDSubrata Banik
Added GPIO library code to allow all BSW board specific code to use memory configuration GPIOs in GPIO Input mode and read them to determine which memory type is on the board. Also added other GPIO related APIs to support GPIO access in BSW. Original-Reviewed-on: https://chromium-review.googlesource.com/294893 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Idd65136c0449f0cdebfae12a510985e29889fa2b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12735 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: revise cbmem_topCC Ma
Support memory range querying to above/below 4GiB. Enable PRERAM_CBMEM_CONSOLE. BRANCH=none BUG=none TEST=build and verified pass on oak board Change-Id: If12ab2e9b8a129e2c82dd97b0493d9abdd6985a9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 139a3163ca867ec5676c6cb81fdec724c99a4a99 Original-Change-Id: Ie190f86f49ae88671f0738e2d6ceafdad58a93cc Original-Signed-off-by: CC Ma <cc.ma@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292559 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13098 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22mediatek/mt8173: move rtc_boot() to romstageYidi Lin
BRANCH=none BUG=none TEST=boot to kernel Change-Id: I0630d7c172e97f81abb1722afe028542e9e7f106 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 608c66df0543c76be7e811b06718464776631b55 Original-Change-Id: I03426085121bfa44c99c351d63db28f567d0ee1d Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313969 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13097 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22mediatek/mt8173: Add usb phy driverChunfeng Yun
BRANCH=none BUG=none TEST=build pass and test it ok on oak Change-Id: Ib3d3f420dd576a63d7504dd0949040a3d430c675 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b17b03ed40b562a520185fa243bc4458daed6f23 Original-Change-Id: Ib9346f7913433ca82e8123feaf34fd0d6c071047 Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292687 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13095 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: pll: Add API for enabling USB 3.0 phy reference clockChunfeng Yun
BRANCH=none BUG=none TEST=test it ok on oak-rev3 Change-Id: I05233c5b9aa237dce1e6667ed09fe6d56f8e6350 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eb3efe8d0d1199ab836af01dc012cc97257b4fd4 Original-Change-Id: Ie1ab9421052dbd6aea8fbd762143cec0ce0d88f5 Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297942 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13094 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: configure audioKoro Chen
BRANCH=none BUG=none TEST=build and verified pass on oak board Change-Id: I2680f6b87614362dffb27490bdeedf7125006c3f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc2bb9f5b461ec848df8aba07940b895401004f8 Original-Change-Id: I848468cec04a36659fbb4b898dff9368305d72ac Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292683 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13091 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: add APLL clock settingKoro Chen
Add a new function mt_pll_set_aud_div() to set APLL for audio I2S. The function is called by mainboard's configure_audio(). BRANCH=chromeos-2015.07 BUG=chrome-os-partner:41507 TEST=build and verified pass on oak board Change-Id: Ia3c2f250627028422a7427b93d78d49545eb7a75 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bb18943f5e74af7723bd4e01d4da96c0b153a0f6 Original-Change-Id: I7996a8048f2e54ab09093cca3c8bc7447b61170f Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297225 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13090 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: Add mtcmos power-on control for audio and displayCC Ma
BRANCH=none BUG=none TEST=none Change-Id: Ic046c66c8e314bd61f96c2edbc5d832260590afe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 84de3a6f1a726938e2318814d6faaf6a7dd29ac0 Original-Change-Id: If29f28a092617532dd73e71e0dbe24fd930c3bf8 Original-Signed-off-by: CC Ma <cc.ma@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292677 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12617 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-01-22mediatek/mt8173: Add RTC driverTianping Fang
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I03740ce1afeb8607891fff61110a40dd98b80bdc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9b0cc22cb9e2010e28e854d9984c11149a71ae0b Original-Change-Id: I6d6482a75cc40ed6183ee115d5d866257afa24af Original-Signed-off-by: Tianping Fang <tianping.fang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292676 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12616 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-01-22mediatek/mt8173: Add I2C driverLiguo Zhang
BUG=none TEST=emerge-oak coreboot BRANCH=none [pg: split into multiple commits] Change-Id: If2cac5aecc5675048e0e2d28897b1a82e099de7d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2a3d867fd1e547cadc6c947f38082fddc2265d32 Original-Change-Id: I4f3a9b403b949d8ae8e3c393cc9441fb66ea5f1d Original-Signed-off-by: liguo.zhang <liguo.zhang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292667 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12615 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: Add MMU supportJimmy Huang
BRANCH=none BUG=none TEST=build pass [pg: split into multiple commits] Change-Id: Ib46b243102969e2860479070e19640fb6cb9bdd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3ee2a20ec56359e917bb8f4825846c54d4f6276a Original-Change-Id: Iedc81a85569b00524620e9ba128e7d77f17b0405 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292666 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12614 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: Add gen-bl-img.py for mt8173 bootblock codeYidi Lin
The mt8173 boot rom expects the bootblock to be in a certain format. gen-bl-img wraps our bootblock appropriately. BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I7486e548d356c5bd27261851f1f1bed620715e91 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fbcd7959e0fda595de91899ace7236037ac833d3 Original-Change-Id: Ib9df440bfa95cf06e8041491ecdb34c357047acd Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292664 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12613 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: Add support for verstageItamar
Add support for verstage [pg: split original commit into multiple commits] Change-Id: Ia43bc72a1fb36c6fad5be5654abee5fc19fc4093 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292662 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13051 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: add watchdog driverItamar
[pg: split original commit into multiple commits] Change-Id: I0dc8d9855c98c077d4a47227de0c504c3a846953 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292662 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13050 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-22mediatek/mt8173: Add SPI supportLeilk Liu
BUG=none TEST=emerge-oak coreboot BRANCH=none [pg: split into multiple commits] Change-Id: I82d982b40dd0bfaa7770a6b08c70b20337a46955 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 41acc14e9fe54924d20e4e5a2d1519251f0e1c87 Original-Change-Id: I2559be4191da9af523944563729171bd92a86cd0 Original-Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292661 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12611 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22soc/braswell: Add method for Wifi regulatory domainFelix Durairaj
Get the WRDD domain code from VPD and put it in global nvs. WRDD method in wifi.asl returns this value from global nvs. This wifi.asl should be included in dsdt.asl under the root port where wifi module resides. Original-Reviewed-on: https://chromium-review.googlesource.com/314373 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com> Change-Id: I809d28f10e80681471a785e604df102fb943a983 Signed-off-by: fdurairx <felixx.durairaj@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12745 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22intel/skylake: Fix klockwork violationNaresh G Solanki
File: src/soc/intel/skylake/flash_controller.c Line: 192 Variable 'ret' might be used uninitialized in this function. Hence initializing it with initial value of zero. BRANCH=None BUG=chrome-os-partner:48542 TEST=Built & booted Kunimitsu board. Change-Id: I4e63612890057a2180f38b2e74419d98b02b70c1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b93ca876912d2336dae25b9b84e56ffb171b215b Original-Change-Id: Ied8c909f5294d56daddb2806111d477246f98957 Original-Reviewed-on: https://chromium-review.googlesource.com/322082 Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com> Original-Tested-by: Naresh Solanki <naresh.solanki@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13072 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22intel/skylake: Thermal Design Power PL1 and PL2 Config Changespchandri
Override the default PL2 values with one recommended by Intel. Disable PL1 configuration via MMIO register. BUG=chrome-os-partner:49292 BRANCH=glados TEST=MMIO 0x59A0[14-0] to find PL1 value (0x78) / 8 Watts = 15W MMIO 0x59A0[15] to find PL1 enable/disable = Disable MMIO 0x59A0[46-32] to find PL2 Value (0xC8) / 8 Watts = 25W Here PL2 is set to 25W and PL1 is disabled. Change-Id: I10742f91cc7179de1482d42392338976e8082afe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1b7771ccb34bdff92ffa9870733bd641e4644cdf Original-Change-Id: Iefa93912008c71b41f2b20465e8acfd42bb6c731 Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/321392 Original-Commit-Ready: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Original-Tested-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/13070 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21intel/skylake: remove third paragraph of license headerMartin Roth
We had another one that crept in while the linter was broken. Change-Id: Ie690e2d7fc7ad31b3b674de1618723bb100ac961 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13056 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-21broadwell: gpio.asl: Make GWAK method serializedDuncan Laurie
This method creates named objects and must be serialized to prevent a warning from IASL. Tested by compiling purism/librem13 which includes this ASL. Change-Id: Ic043ea479e681d2180421fcf8e0583b62e6fcd71 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/13045 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-19Braswell: add code to support customization of I2C data hold timeKane Chen
The I2C data hold time can be vary on different boards/devices. So, it needs to be customized by boards/devices TEST=compile ok and check IC_SDA_HOLD is changed if the hold time is defined in onboard.h Original-Reviewed-on: https://chromium-review.googlesource.com/308623 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I66c799de400670916cebbcb529d4f59d5b0f081b Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/12740 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19intel/skylake: Fix issues found by klockworkNaresh G Solanki
src/soc/intel/skylake/acpi.c Function cbmem_find may return NULL, check before using its result. src/soc/intel/skylake/flash_controller.c Remove dead code: spi_claim_bus is a no-op, always returning 0. src/soc/intel/skylake/gpio.c Check for NULL before using pointers. src/soc/intel/skylake/igd.c Don't copy 0-termination of signature string. src/soc/intel/skylake/lpc.c Don't check unsigned >= 0. src/soc/intel/skylake/systemagent.c Explicitly cast result to 64bit. BRANCH=None BUG=chrome-os-partner:48542 TEST=Built & booted Kunimitsu board. Change-Id: I6cbf4f78382383d3c8c3b15f66c5898ab5bf183a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d98a8cdd3d095a6943c0e104cd4938639a62bd14 Original-Change-Id: Id2a31402618f4c9f6f53525ebcf6b71fd67428db Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317522 Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com> Original-Tested-by: Naresh Solanki <naresh.solanki@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12991 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-19intel/skylake: Adding provision to set voltages to the I2C portsNaresh G Solanki
This patch adds an UPD/VPD parameter to set voltages to the I2C ports individually via devicetree.cb BRANCH=None BUG=chrome-os-partner:47821 TEST=Tesed by setting voltage via devicetree.cb and verified voltage level using a DSO probe. CQ-DEPEND=CL:*242225, CL:*241206 Change-Id: Iaeb1ab3f9724aa1139c876dc63250469661d8439 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fc73b98529ad1eb187f97a4177beda4224f473d1 Original-Change-Id: Ib477ad26667ef59cd298b5e20a68a8c68d85bd8d Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315167 Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com> Original-Tested-by: Naresh Solanki <naresh.solanki@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13006 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19intel/skylake: Disable SaGv in recovery modeharidhar
This patch disables the SaGv feature in recovery mode. Since the memory training happens at both low and high frequency points when SaGv is enabled, recovery mode boot time increases by 5 seconds. To reduce this 5 second increase, the SaGv feature is disabled in recovery mode. The value "0" here means SaGv disable. Following is the table for same. 0=Disabled (SaGv disabled) 1=FixedLow (Fixed to low frequency) 2=FixedHigh (Fixed to High frequency) 3=Enabled (SaGv Enabled. Dynamically changes) BRANCH=None BUG=chrome-os-partner:48534 TEST=Built for kunimitsu. Results show recovery mode boot time is not affected (not increased). Change-Id: I77412a73a183a5dbecf5564a22acc6e63865123e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dc586079052acf9af573b68dff910386cd43484d Original-Change-Id: Ice3e1a630e119d40d3df52e3a53ca984e999ab0b Original-Signed-off-by: haridhar <haridhar.kalvala@intel.com> Original-Signed-off-by: Somayaji, Vishwanath <vishwanath.somayaji@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315759 Original-Commit-Ready: Haridhar Kalvala <haridhar.kalvala@intel.com> Original-Tested-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-on: https://review.coreboot.org/12998 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19soc/braswell: Remove the unneccessary functions from pcie.cShaunak Saha
Functions in file pcie.c is not needed. TEST=Boot and test wifi and video playback Original-Reviewed-on: https://chromium-review.googlesource.com/298965 Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I70337c0fc61c221330836ef17f6cefea8c5f0f11 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/12737 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19intel/skylake: Add support for IV feedback loop capture blobSathya Prakash M R
SSM4567 smart speaker needs Current and Voltage sensing to be captured and reported to the algorithm. This needs 4 CH capture blob. BUG=chrome-os-partner:48625 BRANCH=none TEST=Built and booted. Verified CBFS locates the blob. CQ-DEPEND=CL:*242635 Change-Id: Ie13622da9a9a8ce5930d32e52ddaf2e0d4862895 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 06f1a501dcb3fa6102eccdb3e24f9011b7869ab0 Original-Change-Id: I7b65b7582b619be53544ebbe4b3ea65398d32a34 Original-Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319020 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12995 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/skylake: Change in UPD name from SkipMpInit to FspSkipMpInitBarnali Sarkar
Changing the UPD param name from "SkipMpInit" to "FspSkipMpInit" BRANCH=none BUG=none TEST=Build and booted in kunimitsu with FspSkipMpInit token enabled from Coreboot. Change-Id: I5ebe7a1338ac77a62d5aa2e48e083b4fb906bf28 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cdaa95a82bc7e90637c6b90e33d88d040e085f58 Original-Change-Id: Ibdaa3d202f8f6f6f0ca6c6d4c6428f1616572f1d Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319353 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12993 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-18intel/skylake: Remove unused devicetree configuration variablesDuncan Laurie
The GPU panel configuration variables are unused on skylake and are no longer needed in chip.h. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-chell coreboot Change-Id: Ie6bfb676b5a32b4d4d39dda91b90fc7e973d38e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f261d7ca9ec93aae1362975efde11ac9657b7ca6 Original-Change-Id: If64594455754e4dea1f53511861b74ddd880c5b5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/318923 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12986 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/skylake: provide default VR configurationAaron Durbin
FSP 1.8.0 will do nothing with the VR settings if VrConfigEnable is non-zero. That behavior is not desired because it's not clear what the behavior will be for various processor SKUs. Instead provide default values for the VR config. Note that PSI3 and PSI4 are not enabled for those defaults. BUG=chrome-os-partner:48466 BRANCH=None TEST=Built and booted glados. Change-Id: I02cb5fbdd4549cc827a0b0e4006bc21da4593b55 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a68c53e0fdf15584270dfafc679a22319f497d17 Original-Change-Id: I82b1d1da2cfa3c83ccc6a981e30ffac6fb6c8c4b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/318263 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12983 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/skylake: Add devicetree setting for DDR frequency limit UPDDuncan Laurie
There is a UPD setting exposed by FSP that allows the DDR frequency to be limited. Expose this for devicetree. BUG=chrome-os-partner:47346 BRANCH=none TEST=tested by limiting DDR frequency to 1600 on chell EVT Change-Id: I1f17b221d9fa4c2dd1e8c5f403deb0f2bc0493a7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 91f760ad19823225f7e5bd2dc690164ed253e220 Original-Change-Id: Ibcd4a65a9cfd7d32fbf2ba8843ab25da8e9cf28a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/317243 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12981 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/skylake: Add elog event for THERMTRIPDuncan Laurie
The THERMTRIP status bit is in GBLRST_CAUSE instead of GEN_PMCON like the EDSv1 indicates. Read this status bit and add an elog event if THERMTRIP has fired. BUG=chrome-os-partner:48438 BRANCH=none TEST=tested on chell EVT after thermtrip fired Change-Id: Icd52b753c7f3ab0d48095279f1255dd2dd08fd59 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b090c7897a8f99a685f523990235d83fafa063b2 Original-Change-Id: I5a287d7fdae2ba8ae8585cb9a4d4dd873393e1e6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/317242 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12980 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18header files: Fix guard name comments to match guard namesMartin Roth
This just updates existing guard name comments on the header files to match the actual #define name. As a side effect, if there was no newline at the end of these files, one was added. Change-Id: Ia2cd8057f2b1ceb0fa1b946e85e0c16a327a04d7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12900 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-17intel/skylake: disable heci1 if psf is unlockedArchana Patni
This patch adds support for disabling the heci1 device at the end of boot sequence. Prior to this, FSP would have sent the end of post message to ME and initiated the d0i3 bit. This uses the Psf unlock policy and the p2sb device to disable the heci1 device, then lock the configuration and hide the device. BRANCH=none BUG=chrome-os-partner:45618 TEST=build for kunimitsu or glados board. set the hecienabled policy to 0 and check for heci 1 device status in kernel lspci. CQ-DEPEND=CL:*238451 Change-Id: I26b145231f8ed0c140af42d378b222e857d9aff6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fe184b8baf1bea9bcd0af1841785a4d763af9358 Original-Change-Id: I3b435491aeea0f2ca36b7877e942dc940560e4dd Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311912 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12976 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-17intel/skylake: During RO mode after FSP reset CB lose original stateSubrata Banik
CB used to clear recovery status towards romstage end after FSP memory init. Later inside FSP silicon init due to HSIO CRC mismatch it will request for an additional reset.On next boot system resume in dev mode rather than recovery because lost its original state due to FSP silicon init reset. Hence an additional 1 reset require to identify original state. With this patch, we will get future platform reset info during romstage and restore back recovery request flag so, in next boot CB can maintain its original status and avoid 1 extra reboot. BUG=chrome-os-partner:43517 BRANCH=none TEST= build and booted Kunimitsu and tested RO mode Change-Id: Ibf86ff2b140cd9ad259eb39987d78177535cd975 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 40ddc21a97b318510116b7d5c4314380778a40f7 Original-Change-Id: Ia52835f87ef580317e91931aee5dd0119dea8111 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/302257 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12975 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16intel/skylake: Fix uninitialized variable warningMartin Roth
I don't think the warning is valid, because we already verify that num_channels is 2 or 4 as soon as we enter the function. Adding the default case makes the compiler happy. Fixes warning: src/soc/intel/skylake/nhlt/dmic.c: In function 'nhlt_soc_add_dmic_array': src/soc/intel/skylake/nhlt/dmic.c:100:2: error: 'formats' may be used uninitialized in this function [-Werror=maybe-uninitialized] return nhlt_endpoint_add_formats(endp, formats, num_formats); ^ Change-Id: Idc22c8478ff666af8915d780d7553909c3163690 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13021 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-16intel/skylake: Add kconfig option to skip Native SD ControllerSubrata Banik
Skylake Core boot should have configurable option to skip PCH based SD 3.0 Controller from customer/reference design. Addition to that no unused or unnecessary should list under device view. BUG=chrome-os-partner:48190 BRANCH=None TEST=Build & boot Kunimitsu and LARs. Change-Id: Ie17fd6db01e0cabcdf605017509d809b54509a0d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 99ac17b723125822368539d0562aa35119e520fb Original-Change-Id: I98a48f45ef442246227fd54ea021b53f824954c5 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315420 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12946 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16intel/skylake: Add VrConfig UPD parameters from corebootRizwan Qureshi
Adding VrConfig UPDs and assign values to those from devicetree BRANCH=none BUG=chrome-os-partner:45387 TEST=Build and booted in kunimitsu CQ-DEPEND=CL:310192 Change-Id: Ifce9dfacabc742b55266c48459c56c69b1f22236 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b34a3cc77afc8795abb64972f8169986c30c2acd Original-Change-Id: Ifa960e718ed77db729f1fc4e2c00c9b305093e04 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311317 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12944 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-16intel/skylake: Enable SkipMpInit tokenRizwan Qureshi
This patch helps to enable SkipMpInit token of FSP SiliconInit UPD BRANCH=none BUG=chrome-os-partner:44805 TEST=Build and booted in kunimitsu with SkipMpInit enabled from CB. CQ-DEPEND=CL:310869 Change-Id: I43377e4b8adadf42091a9387883363fdfbab4c1b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b7962273fd1a591cfe9a658f49ebc7d23bcad577 Original-Change-Id: I977d2d39c283d74f1aa9033c8aa60dc652735019 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310192 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12943 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/skylake: Init variable so GCC knows it's setMartin Roth
Even though the data32 variable was getting written by pch_pcr_read(), GCC still flagged it as being used while uninitialized and failed the build. Note that pch_pcr_read() may only set 1 or 2 bytes of data32 in the successful path, depending on the size of the read. Change-Id: Icd6e80d06b9bf4af506d62d55ffe4c5e98634b2b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12860 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2016-01-15intel/skylake: More UPD params are added for PCH policy in FSPRizwan Qureshi
Some more PCH Policy UPD Parameters are added in FSP. Lockdown config moved from FSP to coreboot. Removing settings in devicetree.cb which are zero. BRANCH=none BUG=none TEST=Build and booted on kunimitsu, verified that CB is doing the Lockdowns which were previously done by FSP. CQ-DEPEND=CL:*237842, CL:310191 Change-Id: I3dcf3a5340f3c5ef2fece2de5390cde48db4d327 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e8bdb35897b640d271adcaed266030367f060553 Original-Change-Id: Ia201672565c07b2e03d972b2718512cd4fcbb95c Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310869 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12941 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-15intel/skylake: Update UPD parameters as per FSP 1.8.0Barnali Sarkar
Some MemoryInit UPD parameters have been moved to SiliconInit in FSP 1.8.0. This patch has the respective changes in coreboot for this. BRANCH=none BUG=none TEST=Build and booted in kunimitsu CQ-DEPEND=CL:*237423, CL:*237424 Change-Id: Ic008d22f96fb5f14965e5b5db15e05fb39dd52d3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 573c1d8325cd504213528030ecf99559402b5118 Original-Change-Id: I71b893aa7788519ed2ef15f3247945ffcbbbcf4d Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310191 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12940 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/skylake: Add GPIO ACPI Apis.Subrata Banik
GPIO ASL APIs to get GPIO Value. Need such APIs to read GPIO config settings. Example: Kunimitsu need to read AUDIO_DB GPIO to identify codec select. BUG=chrome-os-partner:44481 BRANCH=none TEST=build and boot on Kunimitsu. Change-Id: If56bb7b3eae08e1949d372850a6426dfde5aadd0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4983ba835a8da2baf578b035ae482755983c1ecb Original-Change-Id: Ia40d86c8d4b14857fa8822677b3f7d393a35b677 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316352 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12956 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/skylake: add nhlt supportAaron Durbin
The use of a NHLT table is required to make audio work on the skylake SoCs employing the internal DSP. The table describes the audo endpoints (render vs capture) along with their supported formats. These formats are not only dependent on the audio peripheral but also hardware interfaces. As such each format has an associated blob of DSP settings to make the peripheral work. Lastly, each of these settings are provided by Intel and need to be generated for each device's hardware connection plus mode/format it supports. This patch does not include the dsp setting blobs. The current supported connections: - digital mic array 2 channel - digital mic array 4 channel - Maxim 98357 amplifier - ADI ssm4567 - NAU88L25 headset codec BUG=chrome-os-partner:44481 BRANCH=None TEST=Built glados. Speakers, headphones, and mic on camera decently worked. CQ-DEPEND=CL:*239598 Change-Id: If1a9be97573b9b160893944661790cac7df26fca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1f5514e27811c500732de97e1cc7edeced2607e7 Original-Change-Id: Ib42e895f00e7605cb30ce24d9b8dd00bf68a7477 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313998 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12938 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14soc/braswell: Add CPUID for D0 steppingDivya Sasidharan
Original-Reviewed-on: https://chromium-review.googlesource.com/309122 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Ia24dbeb6b23ccbbb380843a4684def578cde168a Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://review.coreboot.org/12727 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14soc/braswell: Fix P-state tableSubrata Banik
Incorrect bus-core-ratio been used to generate P-state table Original-Reviewed-on: https://chromium-review.googlesource.com/290681 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I4a34ec80ff3f2ed46dc074c9f8fe06756db8b357 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12731 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14intel/skylake/pcr.c: error out on invalid size in pcr read/writeMartin Roth
The read and write routines take a number of bytes to write, which should be 1,2, or 4. We now return an error if an invalid size is specified. Change-Id: I93344bc0837c3715fc7660503f405c8878eb711c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12936 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-13tree: drop last paragraph of GPL copyright header from new filesMartin Roth
This continues what was done in commit a73b93157f2 (tree: drop last paragraph of GPL copyright header) Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12914 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-12intel/skylake: Remove check for Microcode loaded by MEMartin Roth
This method of reporting has been removed from the current Skylake ME binaries so is no longer needed. Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12854 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-08fsp_baytrail: Add additional PCI space above 4GBMartin Roth
This just tells the OS that it can use the 16GB of address space at the 48GB mark for PCI. This is the upper 16GB of Bay Trail's 36 bit physical address space. This could be hardcoded into the UMEM definition, but doing it this way makes it more plain what it's doing, and allows for modification to put it just above the top of upper memory, similar to what is done with the standard PCI region above the top of low memory. Change-Id: Id6208c3712e5d94d62a83c4ac69e8ffd0e19f4ad Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12791 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: York Yang <york.yang@intel.com>
2016-01-07intel/braswell: Disable IFD & ME by default so abuild can buildMartin Roth
The Braswell IFD & ME blobs aren't published in the 3rdparty repo, so disable them by default for now. Change-Id: If68ff1f37fbf7afb2f9eb1e5d9942afcf40ab1e3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12828 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 05:22:41 +0000