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EFS header is mapped during PSP verstage and bootblock to read some SPI
configuration. After use it is left unmapped. Unmap the EFS region after
use.
BUG=b:240664755
TEST=Build and boot to OS in Skyrim with unsigned PSP verstage.
Change-Id: I865f45a3d25bc639eb8435b54aa80895ec4afd27
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75455
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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cbfs_unmap does not unmap the mapped region from the boot device. This
leads to some resource leaks eg. TLB slots in PSP. Explicitly call
rdev_munmap on the address mapped by cbfs_map.
BUG=b:240664755
TEST=Build and boot to OS in Skyrim with unsigned PSP verstage.
Change-Id: I51b9d066a40103f2ebdf2ef2fc3da13beb467921
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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cbfs_unmap does not unmap the mapped region from the boot device. This
leads to some resource leaks eg. TLB slots in PSP. Explicitly call
rdev_munmap on the address mapped by cbfs_map.
BUG=b:240664755
TEST=Build and boot to OS in Skyrim with unsigned PSP verstage.
Change-Id: If1d355972cc743b8d8c451e1b3f827abd15e98fe
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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On FMAP without RW slots, PSP verstage fails to build because of
reference to FMAP_SECTION_FW_MAIN_A_*. Instead extract the offset and
size of relevant sections using fmap_locate_area().
BUG=b:240664755
TEST=Build and boot to OS in Skyrim with unsigned PSP verstage.
Change-Id: I29997534c6843b47a36655431f79e5c70bd17f9b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Add support to update power limit values for variants.
Until now, each SoC implements this themselves.
To avoid code duplication, add this to common code.
BRANCH=None
BUG=b:270664854
TEST=Built and verified power limit values as below log message
for 15W SKU on Rex board.
Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW)
(57000, 57000) PL4 (W) (114)
Change-Id: I414715f211d816bbfad03a673ca96dd5df94caeb
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Hook the SaGvFreq, SaGvGear upds so that mainboard can change the
settings via devicetree. Meteor Lake supports 4 SaGv work points and it
can dynamically scale the work point based on memory bandwidth
utilization. Dynamic gearing technology allows the Memory Controller to
run at 1:1, 1:2 or 1:4 ratio of DRAM speed. The gear ratio is the ratio
of DRAM speed to Memory Controller Clock.
BUG=b:282164577
TEST=Verified the settings on google/rex using debug FSP logs.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I37169880af4019675374594e90735b5d7d0873b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75290
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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"extern" is automatically implied with function declaration.
Change-Id: Ic40218acab5a009621b6882faacfcac800aaf0b9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71890
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Implement PS0 and PS3 methods to support xHCI clock gating in S0ix
suspend and resume.
BUG=b:283989367
TEST=S0iX test passed
Change-Id: Ia5b72b81fd1c0d0b7b90f8d9cbf6ef4aa9da9743
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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BUG=b:276988831
Platform=Rex
Test= inteltool -k
============= Dumping INTEL Key Locker status =============
Key Locker supported : YES
AESKL instructions enabled : YES
===========================================================
Also,
No S0ix issue seen, no impact on power just with this coreboot patch, no stability issue seen.
Boot time delta (using cbmem -t):
Without this CL:
963:returning from FspMultiPhaseSiInit 1,299,043 (98,480)
With this CL:
963:returning from FspMultiPhaseSiInit 1,324,659 (121,995)
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I9919f44623972d7bbae4a9b886e1da4ac7879c98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71120
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch adds an enum macro to define the different SaGv work points.
The enum macro is named `sagv_wp_bitmap` and it has three values:
The goal is to choose the optimal SaGv work point for the target
platform after considering the two inputs as power consumption and performance. The first group is for workloads that require high performance, even if it means consuming more power. The second group
is for workloads that can tolerate lower performance, in order to save
power.
SAGV_POINTS_0_1: The highest power consumption, but also the highest
performance.
SAGV_POINTS_0_1_2: A lower power consumption than work point
SAGV_POINTS_0_1, but also a lower performance.
SAGV_POINTS_0_1_2_3: The lowest power consumption, but also the lowest
performance.
Set SaGv work points after reviewing the power and performance impact
with SaGv set to 1 (Enabled) and various considering various work points
between 0-3 being enabled.
BUG=b:267879107
TEST=Able to build google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4af0038f2799a458d1b006270068341f65d36609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75362
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add CPU PortID for GPIO communities in order to calculate
IOM Aux Bias data correctly.
BUG=b:283044004
TEST=able to detect external display
Signed-off-by: Marx Wang <marx.wang@intel.com>
Change-Id: I79f27fb0b6bde0a4ce2466eaf707166a952fad81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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The data payload size of PCIe root ports can be set to either 128
(default) or 256 bytes. A bigger payload size can improve PCIe data
throughput on the given port. FSP-S provides a parameter to configure
this value.
This patch provides a chip config so that this FSP parameter can be set
as needed in the devicetree on mainboard level.
Change-Id: I5798a72adaa8089dda0b4bc12266b5a235ed4aa3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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1. Rename set_cmos_mrc_cold_boot_flag() to soc_set_mrc_cold_boot_flag
in case a certain platform may not support this via CMOS data, and
the function could in turn calls mainboard defined method in the
future. Move the code into soc_util.c.
2. Remove redundant static get_system_memory_map() from cpx/romstage.c
and call the soc_util.c one.
Change-Id: Ib7d9bed9092814658f4a0b1d6dcf3c7d79178048
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Add PCI IDs to support Raptor Point PCH.
Ref: Intel 700 Series PCH Datasheet, Volume 1 (#743835, rev 2)
Change-Id: Iee410ed3179260b08d45f50e8126fb815c686324
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73437
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Earlier the entire SPI ROM is mapped at the start of verstage and then
unmapped at the end of verstage. With CB:74606, this behavior has
changed. So unmap the hash table CBFS file after usage.
BUG=b:240664755
TEST=Build and boot to OS in Skyrim. Perform cold, warm reboots and
suspend/resume cycles for 50 iterations each. Ensured that there is no
impact to boot time.
Change-Id: I5c605f8ba8bbd571b589b3cdf91e9cc71d711c1c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75092
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently the SPI ROM is mapped completely when the boot device is
initialized. That mapping remains active throughout the execution time
of PSP verstage. Every 1 MiB of mapped SPI ROM region consumes 1 TLB
Slot in PSP for use during memory mapped or DMA access. With 16 MiB of
mapped SPI ROM + FCH devices + 4 reserved TLB slots, 31 out of 32 total
TLB slots is consumed. This leaves almost no scope for future expansion.
With upcoming programs possibly using 32 MiB SPI ROM, PSP will run out
of TLB slots to support 32 MiB.
Hence instead of mapping the entire SPI ROM upfront, get the SPI ROM SMN
address during the boot device initialization. Update the boot device
region operations to map and unmap the SPI flash with the desired offset
and size using the SVC call. Then anytime a memory mapped SPI ROM access
is performed: map the required area, read the data and immediately unmap
the area. There is no update required when using CCP DMA, since the
concerned SVC call performs mapping and unmapping of the required SPI
flash area implicitly.
With these changes, maximum of 8 slots(size of RO section) might get
used at any point in time during the PSP verstage execution.
BUG=b:240664755
TEST=Build and boot to OS in Skyrim. Perform cold, warm reboots and
suspend/resume cycles for 50 iterations each. Ensured that there is no
impact to boot time.
Change-Id: Icd44ea7b2a366e9269debcab4186d1fc71651db2
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74606
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently unsigned PSP verstage binary is copied from ELF file only when
required in amdfw*.rom. If a signed PSP verstage binary is supplied
while building amdfw*.rom, then it is dropped. Copy the unsigned PSP
verstage binary always so that it can be used for signing directly from
the CI build infrastructure instead of a locally built binary.
BUG=None
TEST=Build Skyrim BIOS image and ensure that the unsigned PSP verstage
is part of the build artifacts.
Change-Id: If797dcfd20aa2991f3517904ef862406b9b9875c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75334
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Show an error if an option table is used, and the ramtop entry is not
defined on a platform that uses it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie48f0766b29be8e1fb0c1f71c4b2ce6ed20e6207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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This patch adds an API to check FSP reset pending requests. This
information is useful to understand if FSP would like boot firmware to
issue any reset to complete the silicon initialization.
As per recent debug it has been found that, FSP is accumulating all
platform resets and executing a single reset from FSP Notify Phase.
As coreboot skipped calling into the FSP Notify APIs hence, it might
have missed the scope to issue the platform reset.
BUG=b:282266168
TEST=Able to build and boot google/rex and able to detect FSP reset
pending request.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibf7c996f09affa099c9124773fe2d581f370d1a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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As announced in the 4.20 release notes, support for the Intel Quark SoC
is moved to the 4.20 branch and dropped from master.
Change-Id: I8a1ca7a2092aaeaea9c72eac5a8dd8f7d72e8f09
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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The `ramtop_table` is 10 bytes long, so adjust the check to
account for this.
Also, adjust the wording to make it clear what is required to fix it,
should the error be shown.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If2898c4bb22abb1779035aadc08f32898e9a096b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Enable PSYS capability. PSYS is required to safeguard the system
stability if no charger IC.
BUG=b:281479111
TEST=emerge-dedede coreboot chromeos-bootimage & ensure the value is
passed to FSP by enabling FSP log & Boot into the OS
Change-Id: Ibe54acaf80700252558b82f194b9536b6117b84e
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75196
Reviewed-by: Reka Norman <rekanorman@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add igd device name in soc_acpi_name(), and src/drivers/gfx/generic
can generate device in GFX0 scope in SSDT.
BUG=b:277629750
TEST=emerge-rex coreboot then check SSDT on DUT
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Id7a136b5234cf5c0f60ecf253ee78c123f1f573b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch drops the assert check around
`FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN` config to ensure
`fsp_get_pch_reset_status()` can be used by all other FSP APIs to know
the status of the pending reset.
As per recent debug it has been found that, FSP is accumulating all
platform resets and executing a single reset from FSP Notify Phase.
As coreboot skipped calling into the FSP Notify APIs hence, it might
have missed the scope to issue the platform reset.
Going forward coreboot needs to implement the corresponding logic to be
able to identify any pending platform reset request and execute to
complete the silicon initialization flow.
BUG=b:282266168
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2c9e37fadc27eab820a3121e47e09529de34d10e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75309
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Code changes are necessary because `-Wformat` warns about empty
format strings by default.
Change-Id: Ic8021b70f4cd4875b06f196f88b84940c9a79fe0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75147
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I1384a02fa2931002ddd629acef0a4368435cfeb5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The `ramtop` can be obtained from the `option.h`, so remove the
hardcoded value. Keep the check for the value being byte aligned.
Change-Id: I5327b5d4e78b715a85072e5d9a62cf8fd2ae92c0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74511
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch overrides FSP-S UPD `LogoPtr/LogoSize` with a valid
logo.bmp file if `BMP_LOGO` config is enabled.
TEST=Able to see splash screen while booting google/marasov
with BMP_LOGO config enable.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I421da2b4dadb892f17a859ce0ec586a2880469eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75294
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch overrides FSP-S UPD `LogoPtr/LogoSize` with a valid
logo.bmp file if `BMP_LOGO` config is enabled.
TEST=Able to see splash screen while booting Intel Meteor Lake RVP
with BMP_LOGO config enable.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iaba187456dd4dfb2f69d3532e83a3850f31783ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75198
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Both the AMD AGESA reference code and the default coreboot
ACPI_CPU_STRING use hexadecimal numbers in the ACPI CPU object names, so
change the ACPI_CPU_STRING format string in the both the Stoneyridge
Kconfig and the common non-CAR AMD SoC config Kconfig which covers all
other AMD SoCs in soc/amd. All platforms where the P state and C state
SSDT from binaryPI (Stoneyridge) or FSP (Picasso) was used in coreboot
before it got replaced by native code, had at most 8 cores/threads, so
the mismatch never became apparent.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9d6822c5df01786ee541ce90734b75ed1a761fca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75250
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Specifying types without addresses for PM1B events is
not useful.
Change-Id: I839208eaecf689a32484b9154647fc66633e5eef
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Set the default soft fuse bits to the recommended values
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I2354aefe90a08eaef95a68926806d11a9118c3de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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In ACPI 1.0 the processor objects were inside the \_PR scope, but since
ACPI 2.0 the \_SB scope can be used for that. Outside of coreboot some
firmwares still used the \_PR scope for a while for legacy ACPI 1.0 OS
compatibility, but apart from that the \_PR scope is deprecated.
coreboot already uses the \_SB scope for the processor devices
everywhere, so move the \_SB scope out of the ACPI_CPU_STRING to the
format string inside the 3 snprintf statements that use the
ACPI_CPU_STRING.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I76f18594a3a623b437a163c270547d3e9618c31a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Don't set bit 2 of the return value of the _STA method in order for
Windows not to show a warning about an unknown device in the device
manager for this device.
TEST=The unknown device with device instance path ACPI\AMD0040\3
disappeared from the device manager in Windows 10 build 19045 on a
Mandolin board with a Picasso APU.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If005f06843956004c281fd70cf364171148cb9ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68962
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit 396fb3db74db ("soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide AAHB
device") didn't only change the visibility of the device, but also
changed the _STA method to a name. While this worked, the specification
says that _STA is supposed to be a method, so change it back to being a
method.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0932b2875aaf563a4dbd860bdd11a04272e3780
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75169
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Clang complains about this.
Change-Id: I2d761d2fa946f171033220ab7b2e399cf359782a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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TEST: BUILD_TIMELESS=1 remains the same.
Change-Id: I740b59574303145fc673a97556367daefe8d1540
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74540
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Clang warns about unsigned comparison below 0. Use the enum value itself
to fix this warning.
Change-Id: I12fccff2fb7d43fd4582afd518a7eab632908a5f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74553
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I62b7390c2de244cce169550e9b1fa41af738525d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75037
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I1c995d942fa25a9268fbf716034335937df57714
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75036
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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This fixes clang warnings.
Change-Id: I407da6ec05ef646f61bd81e314fee1b5ea659192
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74557
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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The patch defines enum type for MKHI group IDs and ME SKU types instead
of macros.
TEST=Build code for Rex
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I102e802938a6a664a43a362d90a26755cff8f316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
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Having `_cmos_offset` in a CMOS offset is superfluous; remove it
so the CMOS entry is just `ramtop`.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ibc1e7d78d2e3ae04330d19e64c3437ff07060ea8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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In GEN_PMCON1 (Offset 1020h), Bit 0 is the "After G3 Enable" (ag3e)
(source Intel document #569262). Only use 8 bits, in the same way as
most other Intel SOCs do, for pmc_soc_set_afterg3_en.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Idb290d1480b03cb3425edc6ff29b9c78a6545df1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74955
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The return value of cse_get_bp_info() is an enum integer, where zero
means success and non-zero means failure. The function
store_cse_rw_fw_version() calls the function cse_get_bp_info() and
validates the return value as a boolean causing prematurely returns of
the parent API even if cse_get_bp_info() is successful.
This patch corrects this logical error by returning only if
cse_get_bp_info() fails.
TEST=Build and boot google/nivviks and verify that the ISH version info
command is only being sent during cold boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ice278e5ac69ff2f2c9f1936b76d71ae9deb6f855
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74998
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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If the ME is disabled with the `me_state` CMOS setting, boot
times are approximately 5 seconds longer:
942:before sending EOP to ME 1,240,773 (5,599)
943:after sending EOP to ME 6,263,951 (5,023,177)
Total Time: 6,167,443
This is because the current code only checks if the ME is
disabled for CSE LITE SKUs. With this patch, boot times are
approximately 5 seconds quicker:
Total Time: 1,143,932
Tested on `starbook/adl` and `starbook/tgl`.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I182f30d4fbf43955747c6a7a0b284a43f9c5e4ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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This fixes an issue where pcie was not power gating and blocked
S0ix entry. Overwrite pcie max non-snoop and snoop latency tolerance
values to 15.73ms as stated in doc #729123 - MTL External Design
Specification.
BUG=none
TEST=Boot google/rex, print/check values.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com>
Change-Id: I9dfb9edbac95d28d50653777466ea172be64f612
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68308
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ibb680bb8f94fb8a2812f420ac38f15684b5c0b4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Change-Id: I20a66dce1612ab4394c26f9b0943dac14bcdcfc4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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The Intel SoC Meteor Lake requires a higher pcie max non-snoop and
snoop latency tolerance. Add config to let SoC overwrite the common
code settings if needed.
BUG=none
TEST=Boot google/rex and print/check if able to overwrite values.
Change-Id: Ic2b9a158d219e6c6e7f6e7f0ae0f093c1183b402
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Intel's EHL FSP offers the possibility to select the connected hard
drive type to SATA ports. One has the option to choose between HDD ('0'
- default) and SSD ('1').
This patch provides a chip config so that this FSP parameter can be set
as needed in the devicetree on mainboard level.
Change-Id: Idb03aff5b6c5df592b47e2f4abe4fe58ac7151ba
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74946
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Change-Id: I4d34e5c094440dad4a6ab9adc67d3da6b71ac2bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74514
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Change-Id: I27a610255e5680be1b507d45c6695cf9419ee052
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Assigning duty_offset while duty_width==0 has no purpose.
Under intel/common/block, previous assignment for fadt->gpe0_blk
resolves GPE0_STS(0) from xeon_sp/ebg/.../soc_pm.h and also assigns
value matching pmbase + 0x60.
Change-Id: Iaf688d9471ac527ac20307cf16216abdab731a06
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74827
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit d6e0a90aa0bd574b28b6c9b4b46289bf46a208db.
Reason for revert: Not ready to land, blocked by ancestor CL
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic14e17db4aed2f998878920c66cdc16362920dcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75050
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FSP-M is normally memmapped and then decompressed. The SPI DMA
controller can actually read faster than mmap. So by reading the
contents into a buffer and then decompressing we reduce boot time.
It is interesting that FSP-M takes an additional 8ms to execute. I
suspect since we call it 50ms earlier it's having to wait for one of
its dependencies.
BUG=b:179699789
TEST=Boot guybrush and see 30ms reduction in boot time
| 970 - loading FSP-M | 0.316 | 0.997 Δ( 0.68, 0.05%) |
| 17 - starting LZ4 decompress (ignore for x86) | 0.026 | 13.874 Δ( 13.85, 0.96%) |
| 18 - finished LZ4 decompress (ignore for x86) | 64.361 | 0.337 Δ(-64.02, -4.43%) |
| 2 - before RAM initialization | 0.534 | 0.529 Δ( -0.01, -0.00%) |
| 950 - calling FspMemoryInit | 1.455 | 1.132 Δ( -0.32, -0.02%) |
| 951 - returning from FspMemoryInit | 207.695 | 216.537 Δ( 8.84, 0.61%) |
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I850b1576501753a355e7b23745e04802a0560387
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Beware that there's no XHCI2 controller and the USB4 controller device
pointers were added right after the xhci_0 and xhci_1 controller device
pointers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I14725d4b546ffcca42e21bbe7756babaaff8fea3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74658
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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For early Sign of Life to work, we may need certain pin configurations
very early in boot (e.g. HDMI). This may happen before romstage GPIOs
are configured, and bootblock is not suitable for field upgrading
existing devices. Add a separate GPIO table that can be configured
when early graphics is invoked.
BUG=b:277861633
BRANCH=firmware-brya-14505.B
TEST=Builds and SoL functions on HDMI enabled variants
Change-Id: I7b3ce96a4166451e72aa70b3086eff3fb8b082b7
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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Return 0xf from PCI0 _STA method so that bit 2 is set which indicates
that the device should be shown in the user interface. This ports commit
c259d7192806 ("soc/amd/stoney/acpi: Unhide PCI0 root device from OS")
forward from Stoneyridge to the newer AMD SoCs.
TEST=On Mandolin the PCI Express Root Complex now shows up in the device
manager on Windows 10 and when switching the view to 'devices by
connection', all PCI(e) devices are shown below it.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4155556dc5df8f163fe06aa6719fadbb2684cc19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74949
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures that the PRERAM_CBMEM_CONSOLE_SIZE and
CONSOLE_CBMEM_BUFFER_SIZE hold a larger cbmem buffer size to contain
the entire FSP debug serial log.
The existing implementation was not appropriate, where the larger cbmem
size was even applicable for serial AP firmware (w/o FSP debug) image
as well.
This change is necessary to ensure that the FSP debug serial log is
always available, even in cases where the cbmem buffer size is
limited.
BUG=b:280481298
TEST=Able to build and boot google/rex with non-FSP serial AP image
and with FSP serial AP image. Able to see the AP log completely inside
the cbmem.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib35780fd558c8b6d9aa2e17241131ea4a58c2b9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This patch makes CSE sync in romstage default enabled unless ramstage
config (SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) chooses to override it.
TEST=Able to build google/marasov with this change where CSE sync is
performed early inside romstage.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3f5017fbcf917201eaf8233089050bd31c3d1917
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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Adjust a few things so that the sleepstates.asl file is the same for
sb/amd and soc/amd. These adjustments don't have a functional impact.
Change-Id: I0cc9462b326cdc371ffdbf5759d8adc42456ce74
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74960
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit cbc5d3f34b87db779829eabc90c32780a3865a56 ("soc/intel: Don't
report _S1 state when unsupported") added the `ACPI_S1_NOT_SUPPORTED`
option and commit 0eb5974def63a2fc0dce6dfdad62b0b4c6f4b865 ("acpigen:
Add a runtime method to override exposed _Sx sleep states") added a
mechanism to override the enabled sleep states at runtime. However,
these were only hooked up to Intel sleepstates. so the options would
not have any effect on AMD platforms.
Apply the changes from these two commits to AMD sleepstates so that
both options can be used on AMD platforms as well.
Change-Id: I7d5ef2361e36659ac5c6f54b2c236d48713a07c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74959
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iaf88f34cedd09e2461bb05050392e178ec84d5d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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The commit a0b199c6b483 ("soc/intel/xeon_sp/spr: Add soc
set_cmos_mrc_cold_boot_flag") introduced a copy-paste issue in two error
messages. The error messages should mention the Intel platform SPR
instead of CPX. Fix that.
Change-Id: I4de61ec2cf9fbd98263a7a7a588938d548148656
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74956
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Now that we don't need to find a specific resource in the set resources
function any more, there's no need to use hard-coded indices for the
fixed resources. Instead use an index variable that gets incremented
after each fixed resource got added. The index now starts at 0 instead
of at 1, but now the only requirement is that those indices are unique.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ida5f1f001c622da2e31474b62832782f5f303a32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74849
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Drop the custom lpc_set_resources implementation that does some register
access that has no effect and then calls pci_dev_set_resources and use
pci_dev_set_resources for set_resources in amd_lpc_ops instead.
The SPI controller's base address got configured early in boot in the
lpc_set_spibase call and the enable bits got set early in boot in the
lpc_enable_spi_rom call.
TEST=The contents of the SPI_BASE_ADDRESS_REGISTER at the beginning and
at the end of the call stay the same, so it's simply a no-op.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7a5e3e00b2e38eeb3e9dae6d6c83d11ef925ce22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I77471d464dddffc63bb2f005fef3a33c84ff5f5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I813a27e392a842188dc474018f82e10309783260
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I63fb70da3e9ded6c05354f94ee69bc6dd04e58f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The memory map granularity for those devices is 4kByte.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8806128bdce8988f5cd7c8fa8a342fdb01eb7f42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Since the 16MByte of memory-mapped SPI flash region right below the 4GB
boundary is both a fixed region and isn't decoded on a device below the
LPC device, but assumed to be decoded by the LPC device itself, it
shouldn't be reported as a subtractive resource, but as an MMIO resource
instead.
TEST=On mandolin the 16MByte MMIO-mapped SPI flash now show up as a
reserved region in the e820 memory map which wasn't the case before:
13. 00000000ff000000-00000000ffffffff: RESERVED
The Linux kernel doesn't show any new or possibly related errors.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: Ib52df2b2d79a1e6213c3499984a5a1e0e25c058a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iadc32f4dbf8bd48d8666a213d7b5f3ba42175a90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Since disabling C1E could improve acoustic noise for RPL, add judgement
in SOC code to disable C1E on RPL CPUs and enabling it on ADL CPUs .
BUG=b:278654939
TEST:emerge-brya coreboot
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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At present the problem has only been reported with Alder Lake and
Raptor Lake FSP where MultiPhaseSiInit API is unable to return any ERROR
status. Hence, this patch ensures to select applicable W/A config to
read FSP return status from the FSP Reset HOB.
BUG=b:278665768
TEST=Able to select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN for ADL/RPL SoC
code and call into this API to know the return status from
MultiPhaseSiInit FSP API.
Without this patch:
IshInit() Start
IshDisable() Start
IshPerformGlobalReset()
....
....
FSP returning control to Bootloader with reset required return
status 40000003
FspMultiPhaseSiInit Index-1 returned 0 <-- after control returns
into coreboot, the `status` from the FSP API is reset to `0`
instead 0x40000003. Hence, coreboot avoid hitting the reset.
With this patch:
IshInit() Start
IshDisable() Start
IshPerformGlobalReset()
....
....
FSP returning control to Bootloader with reset required return
status 40000003
FSP: handling reset type 40000003 <-- coreboot is able to understand
the reset request in proper.
GLOBAL RESET!
global_reset() called!
HECI: Global Reset(Type:1) Command
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I18a918cca7e19e03ed6020c55c86c64a94212963
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74785
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch creates a function to read the FSP API Reset Status. This
function relies on the FSP Scheduled Reset HOB which holds the reset
type (warm/cold/shutdown) information along with any platform specific
reset need (like global reset).
Ideally FSP API should be able to return the status (both success and
error code) upon exiting the FSP API but unfortunately there are some
scenarios in ADL/RPL FSP where MultiPhaseSiInit API is unable to return
any ERROR status. Hence, this function provides an additional hook to
read the FSP reset status by reading the dedicated HOB without relying
on the FSP API exit status code.
Additionally, create FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN config option
to handle broken FSP API return status issue.
Any SoC platform that selects the `FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN`
config will call into this newly added API to get the FSP return status
from MultiPhaseSiInit.
BUG=b:278665768
TEST=Able to select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN for ADL/RPL SoC
code and call into this API to know the return status from
MultiPhaseSiInit FSP API.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ief5d79736cc11a0a31ca2889128285795f8b5aae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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These were hidden because no Windows drivers existed, but now that
they do, the ACPI devices need to be visible in order for the
drivers to properly attach.
TEST=build google/banshee, boot Windows, verify Windows drivers
correctly attach to PCM/IOM devices.
Change-Id: Idbbaee29bffb49059d8450abd09e0c3f7b490fae
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74850
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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These were hidden because no Windows drivers existed, but now that
they do, the ACPI devices need to be visible in order for the
drivers to properly attach.
TEST=build google/drobit, boot Windows, verify Windows drivers
correctly attach to PCM/IOM devices.
Change-Id: I1520a71e318674baa234fc6a2126d1d17933d983
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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In order for Windows to detect/load drivers for any child devices,
the PCI0 root device status must be enabled and visible.
TEST=build google/liara, boot Windows, verify PCI child devices
visible in Device Manager.
Change-Id: I3fb1ba11247f0811120a4cf8a4fd99342ae201de
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The change 'commit Iac37aaa5ede5e1cd ("Add Kconfigs to indicate
when CSE FW sync is performed")' adds support to choose CSE FW update
to be performed in ROMSTAGE or RAMSTAGE. The patch also introduced a
dependency on ME_RW firmware compression.
This patch removes the dependency between CSE FW sync in RAMSTAGE and
ME_RW firmware compression as these two are not related and should be
decoupled to support CSE FW sync in RAMSTAGE without the requirement
to compress ME_FW.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I5ca4e4a993e4c4cc98b8829cbefff00b28e31549
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74796
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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I forgot to remove these in commit 0fe36db154eb ("ACPI: Make FADT
entries for SMI architectural").
Change-Id: Ib1bc1dad6053ddb0454d4510917fd2bcf0901f35
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74811
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY
that points to same offset. Since the century field inside
RTC falls within the NVRAM space, and could interfere with
OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY.
There were no reference for the use of offset 0x48 for century.
Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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On boards with RECOVERY_MRC_CACHE FMAP section, populate type 0x63 BIOS
directory entry in RO with that section. If the RECOVERY_MRC_CACHE
section is not present, then fall back to RW_MRC_CACHE.
BUG=b:270569389
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ic5ac87685eaa5fec717e3efa4df7af511b4ce8aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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This ports back commit d75ee46d3ce6 ("soc/amd/picasso/acpi: Change PCI0
BAR window") to Stoneyridge so that the correct end of the non-fixed
MMIO region gets reported in PCI0's _CRS method.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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This ports commit 8c28e51a16e1 ("soc/amd/picasso: fix host bridge bus
numbers") back to Stoneyridge so that the correct number of PCI buses
gets reported from PCI0's _CRS method. The MCFG ACPI table already had
the correct last bus number.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I40121ab0e0438281192b6a0bec8dbecdc1749379
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Change-Id: I7392ede4226a940896c805fc0b0bc0dd615a964c
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74810
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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VGA defined the extended ASCII set based on CP437, but the function
vga_write_text() accepts a signed char array.
This will cause unnecessary confusion that if we want to print u with
umlaut (code=129 in CP437), we need to explicitly cast it to -127 in
signed char.
Since we still want to leverage the built-in string utilities
which only accepts const char*, we still need to cast it to signed char
while processing, and cast it back to unsigned once we write into the
frame buffer.
BRANCH=brya
BUG=b:264666392
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: If555bbc05f40ce3f02339c0468afff6dda8b7ded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Add UPD parameter for eDP power sequence adjustment.
The edp_panel_t9_ms parameter is set for bloff to varybloff.
BUG=b:271704149
BRANCH=Skyrim
TEST=Build; Verify the UPD was pass to system integrated table.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Id651c9cc4d6f4e27f6c78ca10ca12936d66ef43b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74789
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rename the UPD pwr_on_vary_bl_to_blon to edp_panel_t8_ms to
match the eDP sequence timing in milliseconds.
BUG=b:271704149
BRANCH=Skyrim
Test=Build/Boot to ChromeOS
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74787
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Change-Id: I80aa71b813ab8e50801a66556d45ff66804ad349
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74600
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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It is unused. The use of field irq is problematic as it should
appear relative to IOAPIC GSI bases in the devicetree.
Change-Id: I460fd5fde3a7fba5518ccfc153a266d097a95a39
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This patch implements helper function get_cse_ver_from_cbfs() to
retrieve the CSE Lite version from CBFE RW's metadata and calls
the helper function from cse_check_update_status()
TEST=Verified CSE Lite version in coreboot boot log
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Change-Id: Ie1bf186adfc3f87826a7ce9b0167a6bbe6767299
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74755
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
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Commit c7b8809f155a ("soc/amd/common/block/gfx: Use TPM-stored hash
for vbios cache validation") replaced checking the vbios signature
(first two bytes) with checking against a TPM-stored hash, but there
exists an edge case where the empty cache can be hashed and therefore
never updated with the correct vbios data. To mitigate this, re-add
the signature check to ensure that an empty cache will never be hashed
to TPM.
BUG=b:255812886
BRANCH=skyrim
TEST=build/boot skyrim w/selective GOP enabled, flash full firmware
image, ensure GOP driver is run until cache updated with valid data
and hashed to TPM.
Change-Id: Id06a8cfaa44d346fb2eece53dcf74ee46f4a5352
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Since skylake Intel hardware does not support this sleep state. Trying
to enter S1 by having the OS enter sleep results in a system hang on at
least Alder lake (prodrive/atlas).
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC is a good proxy whether devices
support 'skylake style' PMC PCI device for ACPI registers.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic9e19410696240755e8714db53a0525284f3a2da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Fix copy-paste comment on closing endif
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9671a9228c304988eb3903391f74a21d80d0a8bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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For the first IOAPIC, use the common MADT generator with
default IRQ overrides.
Change-Id: Ie6e3eae1728a9a94205ec59557d4af1655191166
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change IRQ #0 to GSI #2 override to positive edge trigger from
the bus ISA default (positive edge).
Change-Id: I2de941071fca6f7208646a065a271fbf47ac2696
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74354
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change IRQ #0 to GSI #2 override to positive edge trigger from
the bus ISA default (positive edge).
Change-Id: I3a61a0ceb0e6e4a09570beef6d0170354eb498ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change IRQ #0 to GSI #2 override to positive edge trigger from
the bus ISA default (positive edge).
Change-Id: Iab3d38da9610ede1d338440b4a8ec0f1537c17e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add Kconfig COMMON_ACPI_MADT_IOAPIC to replace platforms'
implementations of adding IOAPIC and IRQ override entries
for ACPI MADT tables.
Platforms that have a more complex MADT may continue to
add custom entries using CUSTOM_ACPI_MADT.
Change-Id: I0b77769f89cc319ad228eb37bc341e2150b8a892
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74348
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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