summaryrefslogtreecommitdiff
path: root/src/soc
AgeCommit message (Collapse)Author
2019-08-08lib/stage_cache: Refactor Kconfig optionsKyösti Mälkki
Add explicit CBMEM_STAGE_CACHE option. Rename CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE. Platforms with SMM_TSEG=y always need to implement stage_cache_external_region(). It is allowed to return with a region of size 0 to effectively disable the cache. There are no provisions in Kconfig to degrade from TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE. As a security measure CBMEM_STAGE_CACHE default is changed to disabled. AGESA platforms without TSEG will experience slower S3 resume speed unless they explicitly select the option. Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-08fsp_baytrail/fsp_broadwell_de: Sort entries in Makefile.inchcl-coreboot
Change-Id: I12e6ec4aec7dcadcbb886c3fc4c3b9126a0a835c Signed-off-by: Sourabh Kashyap <sourabhka@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-08-07soc/amd/picasso: Set HAVE_BOOTBLOCK=nKyösti Mälkki
Change-Id: Iaf370e04adb04eb81555a57e81812ebe3339971d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-07intel/braswell: Drop config IED_REGION_SIZEKyösti Mälkki
Platform does not set up IED. Change-Id: Ied72888c6406b59332bc3d68eccb50bf1eab3419 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-07soc/amd: Rename smm_region_info() to smm_region()Kyösti Mälkki
Change-Id: I361fb0e02fd0bd92bb1e13fe84c898a1ac85aa40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34703 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-07intel/apollolake: Replace smm_region_info() with smm_region()Kyösti Mälkki
Implementation remains the same. Change-Id: I8483bb8e5bba66b4854597f58ddcfe59aac17ae0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07cpu/x86/smm: Promote smm_subregion()Kyösti Mälkki
No need to limit these declarations to FSP. Both PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE can be built on top of this. Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07intel/icelake,skylake,cannonlake: Drop unused parameterKyösti Mälkki
Change-Id: I0900c3b893d72063cc8df5d8ac370cf9d54df17a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07soc/intel: Obsolete mmap_region_granularity()Kyösti Mälkki
Change-Id: I471598d3ce61b70e35adba3bd983f5d823ba3816 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07mediatek/mt8183: Add I2C driver codeQii Wang
This patch implements i2c driver for MT8183. BUG=b:80501386 BRANCH=none TEST=Boot correctly on kukui. Change-Id: I0a4d78b494819f45951f78e5a618021000cf3463 Signed-off-by: Qii Wang <qii.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30976 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-06tegra210: Increase size of verstage due to overflowChristian Walter
When imlpementing changes in VBOOT, within the build process, tegra210 overflows into the romstage. Reduce the size of romstage from 104 to 100 and increase the size from verstage from 66 to 70. Change-Id: Ie00498838a644a6f92881db85833dd0a94b87f53 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34640 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-06soc/*: Report mp_init errorsPatrick Rudolph
* Increase log level from ERR to CRITICAL in run_ap_work(). * Print or return errors if mp_run_on_all_cpus() failed. Tested on Supermicro X11SSH-TF. Change-Id: I740505e3b6a46ebb3311d0e6b9669e7f929f9ab9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-05soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOCAamir Bohra
This implementation adds support to provide list of LPSS controllers for a canonlake and icelake platforms. It implements strong function of get_soc_lpss_controllers defined under intel common block lpss driver. Change-Id: I36c87e2324caf8ed3e4bb3e3dc6f5d4edf3e8d46 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-05soc/intel/common/lpss: Add function to check for a LPSS controllerAamir Bohra
Add an API to check if device is a LPSS controller. This API can be used for IRQ assignments for LPSS PCI controllers, since the LPSS controllers have a requirement of unique IRQ assignments and do not share same IRQ# with other LPSS controllers. SOC code is reponsible to provide list of the LPSS controllers supported and needs to implement soc_lpss_controllers_list API, in case it needs to use this common implementation. Change-Id: I3f5bb268fc581280bb1b87b6b175a0299a24a44a Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34137 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-05soc/intel/cnl/graphics: Hook up libgfxinitNico Huber
Change-Id: Ic038adad6cf76867cd4a8626d4c49e17018389fd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-05soc/sifive/fu540: Add opensbi supportPatrick Rudolph
Tested on SiFive/unleashed: Boots into Linux until earlycon terminates. Change-Id: I35abacc16f244b95f9fd1947d1a5ea10c4dee097 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34142 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-04soc/intel/common/block/uart: Update the UART PCI device referenceAamir Bohra
This implementation revises the UART PCI device reference in common UART driver. The SOC functions have been aligned to provide the UART PCI device reference using pcidev_path_on_root. The uart_get_device() return type is changed, and files in which it gets used are updated. Change-Id: Ie0fe5991f3b0b9c596c3de9472e98e4091d7dd87 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-03intel/baytrail,broadwell: Move stage cache support functionKyösti Mälkki
Let garbage-collection take care of stage_cache_external_region() when it is not needed and move implementation to a suitable file already building for needed stages. Change-Id: Ia6adcc0c8bf6d4abc095ac669aaae876b33ed0f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34669 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-02soc/samsung/exynos5420: Refactor fimd vidtcon accessJacob Garber
Accessing the higher vidtcon variables using pointer arithmetic from the lower address FIMD_CTRL struct is undefined behaviour, since pointers manipulations are not allowed outside the objects they point to. The standard-blessed way is to perform the arithmetic using integer addresses first, and then convert that to a pointer. The end result is the same, but avoids the risk of unsafe optimizations from an over-zealous compiler. Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402096, 1402124, 1402131, 1402169 Change-Id: I13ed23836e8e9076ae0bfd88c05c4f2badac9c49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-02mediatek: Refactor I2C code among similar SOCsQii Wang
Refactor I2C code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot Change-Id: I407d5e2a9eb29562b40bb300e39f206a94afe76c Signed-off-by: qii wang <qii.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-02soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disabledAamir Bohra
Add a check to enable ACPI timer emulation only when the APCI PM timer is disabled. Change-Id: I21c0b89218d0df9336e0b0e15f1b575b8508fb96 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-08-02soc/intel/cannonlake: Disable ACPI PM timer to reduce S0ix power usageSubrata Banik
This patch overrides EnableTcoTimer FSP UPD default value based on PmTimerDisabled coreboot devcietree config. BRANCH=none BUG=b:138152075 Change-Id: I347c15c7b65fb4c19b9680f127980d4ddab8df51 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-08-02soc/intel/common/pch: Move thermal kconfig selection into common/pchSubrata Banik
This patch moves SOC_INTEL_COMMON_BLOCK_THERMAL selection from respective soc/intel/{skl/cnl/icl} to common/pch/Kconfig. Change-Id: I7c9c8a87cfc5cb4c2fa8b215e56cc35c1f0cce28 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34650 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-02soc/intel/icelake: Make use of common thermal code for ICLSubrata Banik
This patch ports CB:34522 and CB:33147 changes from CNL to ICL. TEST=Build and boot dragonegg Change-Id: I0b983005f16fe182e634eac63fef4f6b22197a85 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34649 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-02soc/intel/skylake: Make use of common thermal code for SKLSubrata Banik
This patch ensures skylake soc is using common thermal code from intel common block. TEST=Build and boot soraka Change-Id: I0812daa3536051918ccac973fde8d7f4f949609d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34648 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-01soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registersDavid Wu
Clear the GPI Interrupt Status & Enable registers to prevent any interrupt storms due to GPI. BUG=b:138282962 TEST=Ensure that the Interrupt status & enable registers are reset during the boot-up when the system is brought out of G3, S5 & S3. Ensure that the system boots fine to ChromeOS. Change-Id: I2185355d0095601e0778b6bf47ae137cc53e4051 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-31soc/intel/skl: Add C232 chipset and reorder IDsFelix Singer
This patch ... - adds the PCH ID for C232 chipset, - renames "Premium" chipset to "HM170" (because of same IDs), - reorders the Skylake-H PCH IDs ascending by hex values. Used documents: - Intel 332690-005EN Change-Id: I859975fe7bcd3c10dead8fe150a2fbead9c64a51 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-31soc/intel/cannonlake: Enable FSP to use coreboot stack for cometlakeAamir Bohra
FSP v1263 for CML supports FSP to use coreboot stack. This change selects common stack config, that enables coreboot to support share stack with FSP. BUG=b:133398276 Change-Id: I4098a4374363ca6f3c86c396d097f9eabc9a28fe Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34130 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31soc/amd/stoneyridge: Change code to accommodate Merlin Falcon SOCRichard Spiegel
Stoney Ridge is family 15h models 70h-7Fh, Merlin Falcon is family 15h models 60h-6Fh. Add changes based on config parameter SOC_AMD_MERLINFALCON to make the code backward compatible with Merlin Falcon. BUG=none. TEST=Tested later with padmelon board. Change-Id: I00fe832324500bcb07fca292a0a55f7258a2d82f Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33624 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31soc/intel/common/block/lpss: Correct the PCI device referenceAamir Bohra
The initial implementation was assigning the devfn as PCI device reference directly which was incorrect. Change-Id: Iad57e9bc6b2acf1823ee38116aea8a93feece6f9 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-31soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ixSumeet Pawnikar
Enable PCH thermal sensor for dynamic thermal shutdown for S0ix state. BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE. Change-Id: I50796bcf9e0d5a65cd7ba63fedd932967c4c1ff9 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34522 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31soc/intel/common/block: Enable PCH Thermal Sensor for threshold configurationSumeet Pawnikar
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE. Change-Id: Ibd1e669fcbfe8dc6e6e5556aa5b1373ed19c3685 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33129 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-30soc/intel/cnl: Only print ME status one timeTim Wawrzynczak
There were two hooks in the boot state machine which dumped the ME status to the debug UART, which is unnecessary. Removed the hook for the BS_OS_RESUME_CHECK state, leaving just BS_PAYLOAD_LOAD, which is called before FspNotifyEndOfFirmware, as required. BUG=b:138463532 BRANCH=none TEST=Boot up, check cbmem to ensure the ME status messages are only printed one time. Change-Id: I86bc6e33de4096f33023730ffabb25715c985de0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-30soc/intel/cannonlake: Allow coreboot to handle required chipset lockdownSubrata Banik
This patch disables FSP-S chipset lockdown UPDs and lets coreboot perform chipset lockdown in ramstage. BUG=b:138200201 TEST=FSP debug build suggests those UPDs are disable now. Change-Id: I7e53c4e4987a7b0e7f475c92b0f797d94fdd60f4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-30soc/intel/cannonlake: Add new PCI IDsFelix Singer
* PCH IDs: H310, H370, Z390, B360, C242, HM370 * IGD IDs: Another variant of UHD-Graphics 630 * MCH/CPU IDs: Used at i3-8100 Used documents: * 337347-005 TESTED=Gigabyte Z390M Gaming Change-Id: I5be88ef23359c6429b18f17bcffbffb7f10ba028 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34600 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-30soc/intel/{broad,cannon,sky}: Fix possible out-of-bounds readsJacob Garber
There will be a possible out of bounds array access if power_limit_1_time == ARRAY_SIZE(power_limit_time_sec_to_msr), so prevent that in the index check. This issue was fixed for other cpus in commit 5cfef13f8d (cpu/intel: Fix out-of-bounds read due to off-by-one in condition). Based on the discussion for that commit, also remove the magic constant 28 in favour of the index of the last array element. Change-Id: Ic3f8735b23a368f8a9395757bd52c2c40088afa1 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229673 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-07-29Revert "soc/intel/common: Set controller state to active in uart init"Christian Walter
This reverts commit 46445155ea21b0aa9106e12a00b9b1d89887a461. Reason for revert: Breaks coreboot. Either no UART working or the complete boot process stops. Platform: Intel Apollolake, tested on Up Squared Change-Id: If581f42e423caa76deb4ecf67296a7c2f1f7705d Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-29soc/qualcomm/qcs405: Handle invalid QUP and BLSPJacob Garber
Print an error message and return if an invalid QUP or BLSP is encountered. This prevents a possible null pointer dereference of spi_clk. Change-Id: I374e15ce899c651df9c2d3e0f1ec646e33d4bdb2 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1401086 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-29soc/intel/baytrail: Prevent unintended sign extensionsJacob Garber
Consider the following assignment: u64 = s32 For positive values this is fine, but if the s32 is negative, it will be sign-extended in the conversion to a very large unsigned integer. This manifests itself in two ways in the following code: First, gpu_pipe{a,b}_port_select are defined as int, and can have the values 1 or 2. In the case when they have the value 2, the shift 2 << 30 will be a negative number, making it susceptible to the sign-extension problem above. Change these variables to something more reasonable like a uint8_t, which is unsigned. Second, in any bit shift, any variable with width less than an int will be implicitly promoted to an int before performing the bit shift. For example, the variable gpu_pipea_power_on_delay is a uint16_t, and if its highest bit is set, the shift gpu_pipea_power_on_delay << 16 will become negative, again introducing the above problem. To prevent this, cast all smaller variables to a u32 before the shift, which will prevent the implicit promotions and sign extensions. Change-Id: Ic5db6001504cefb501dee199590a0e961a15771b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229699, 1229700, 1229701, 1229702 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34487 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29soc/nvidia/tegra124: Assert divisor is non-zeroJacob Garber
The logic for the calculation of plld.m is rather complicated, so do a sanity check that it is non-zero before doing the division. Change-Id: I60f49b8eed47a3de86713304bde7a4d3f3d935dd Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1260981 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-29soc/intel/cannonlake: Correct the data type of serial_io_devAamir Bohra
Change-Id: Id974a4bb84b7d5caddece04f93bf4e830d15b576 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34466 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-28lib: Rewrite qemu-armv7 ramdetectPatrick Rudolph
* Move armv7 RAM dection to a common place * Enable it for all emulated platforms * Use 32bit probe values and restore memory even on failure * Use the new logic on the following boards: ** qemu-armv7 ** qemu-riscv Tested on qemu-system-riscv: Fixes kernel panic due to wrong memory limits reported. Change-Id: I37386c6a95bfc3b7b25aeae32c6e14cff9913513 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-26soc/intel/baytrail/Makefile.inc: Sort entriesAngel Pons
Change-Id: Ic35a901c8272928a0389b38a74f4eac74977a080 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-26soc/mediatek/mt8183: Init SSPMErin Lo
Load SSPM firmware and boot up SSPM. BUG=b:80501386 BRANCH=none Test=We can see "SSPM is alive" in ATF stage if SSPM enabled and ipi success Change-Id: I9285034fc8ce38b40134f5eb7b986a663175e620 Signed-off-by: Erin Lo <erin.lo@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31835 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-26soc/nvidia/tegra124: Correct bitwise operatorsJacob Garber
We are treating reg_val like a bit mask, so use bitwise or instead of boolean or, and use |= to enable certain bits instead of overwriting the whole variable. Change-Id: Ia8c0ea5a58e25b3b58ed82caba20f8e49a30fb68 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1287070 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-25soc/intel/fsp_broadwell_de: Fix use of config_of()Kyösti Mälkki
Change-Id: I96d423720fbe67c067373436ad250edf37939e99 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-25soc/intel: Guard remaining SA_DEV_ROOT definitionKyösti Mälkki
Prevent implicit cast to pointers. The compiler doesn't warn about the conversion from integer to pointer without a cast, because SA_DEV_ROOT is literally '0' and there seems to be an exception for that conversion. Change-Id: I64fc156e3b9f578414ad03a00edb7cf3e33205c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-25soc/intel/broadwell: Fix case of SA_DEV_ROOTKyösti Mälkki
Commit 71756c2 soc/intel: Expand SA_DEV_ROOT for ramstage removed SA_DEV_ROOT expanding to device pointer. We missed the case here, use __SIMPLE_DEVICE__ instead for the file. Change-Id: I4331298837afa3b8c8321da610f99f8f5fa54737 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-25soc/{qualcomm,rockchip}: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also including <types.h>, is supposed to provide stdint and stddef. Change-Id: Iab605f6be4a48c10fa5aae7a1222520149ad1392 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-25soc/mediatek: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also including <types.h>, is supposed to provide stdint and stddef. Change-Id: Id6d881055826044d04843ba165641131b9111342 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-25soc/nvidia: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also including <types.h>, is supposed to provide stdint and stddef. Change-Id: I812d468c68b31917da5d406e2fb3b84bc6331b69 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-25soc/qualcomm/ipq806x: Remove unnecessary allocationJacob Garber
The bus variable doesn't live outside the scope of this function, and is only used as a convenient way for passing the pointers to all the sub-functions, so it doesn't need to be allocated. Put it on the stack instead. Change-Id: I4370d77445952731d20f7d9a91803612f4d21aef Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1294801 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-25soc/intel/cannonlake: Split the "internal PME" wake-up into more detailPaul Fagerburg
The "internal PME" wake-up source could be from integrated LAN, HD audio/audio DSP, SATA, XHCI, CNVi, or an ME maskable host wake. chromium:1680839 adds USB port details to the wake-up when the XHCI causes the wake-up. Expand the logging for wake-up details to identify and log the other wake-up sources with more details. Note that wake on Integrated LAN (GbE), SATA, and ME Maskable Host Wake are not in use on Hatch, so these will not be tested. BUG=b:128936450 BRANCH=none TEST=``FW_NAME=hatch emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`` Ensure /build/hatch/firmware/image-hatch.serial.bin has been built. Program image-hatch.serial.bin into the DUT using flashrom. Switch the DUT to the console (Ctrl-Alt-F2, or use the AP console via servo). XHCI USB 2.0 * Plug a USB keyboard into a USB-A port * ``powerd_dbus_suspend`` * Verify low power mode by issuing the ``powerinfo`` command on the EC console (via servo). Expect to see ``power state 4 = S0ix``. * Press a key on the USB keyboard * ``mosys eventlog list`` shows: 12 | 2019-06-26 14:52:23 | S0ix Enter 13 | 2019-06-26 14:53:07 | S0ix Exit 14 | 2019-06-26 14:53:07 | Wake Source | PME - XHCI (USB 2.0 port) | 3 15 | 2019-06-26 14:53:07 | Wake Source | GPE # | 109 CNVi (connected to Wi-Fi): * Enable wake on disconnect via ``iw phy0 wowlan enable disconnect`` * Set up a hotspot on an Android phone * Connect the Chromebook to th hotspot * ``powerd_dbus_suspend`` * Verify low power mode by issuing the ``powerinfo`` command on the EC console (via servo). Expect to see ``power state 4 = S0ix``. * Turn off the hotspot on the phone * ``mosys eventlog list`` shows: 8 | 2019-07-11 10:58:17 | S0ix Enter 9 | 2019-07-11 10:59:17 | S0ix Exit 10 | 2019-07-11 10:59:17 | Wake Source | PME - WIFI | 0 11 | 2019-07-11 10:59:17 | Wake Source | GPE # | 109 XHCI USB 3.0 * TBD HD Audio * TBD Change-Id: I2c71f6a56b4e1658a7427f67fa78af773b97ec7f Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34289 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25soc/nvidia/tegra210: Prevent unintended sign extensionJacob Garber
The perennial problem with u16 << 16 strikes again - the u16 is implicitly promoted to an int before the shift, which will then become negative if the highest bit of the u16 was set. Normally this isn't much of a problem, but in this case tegra_dsi_writel() expects a 64 bit integer for that argument, and so it will be sign-extended to a very large unsigned integer if it is negative. Cast bytes to a u32 beforehand to prevent the implicit promotion and thus this problem. Change-Id: Iaf0fb1040ccafafde0093e9bb192c802b86cb2ac Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1294800 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34529 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25soc/nvidia/tegra210: Add null pointer checkJacob Garber
Check that tx is not null before accessing it, similar to the previous if statements. Change-Id: I820cb670026bb12a54c63227aa04e778fd49c66a Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1294805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-25soc/rockchip/rk3399: Use 64 bits in multiplicationJacob Garber
This multiplication is of the form u64 = u32 * u32. Despite being stored in a 64 bit variable, the intermediate value is still calculated using 32 bit math, which could possibly overflow. Cast one of the variables to a u64 to ensure it uses 64 bit math instead to avoid this. Change-Id: Ib08624812e933fdca5a51150ab36d3be49383326 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1375443 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-25soc/intel/icelake: Add ENABLE_DISPLAY_OVER_EXT_PCIE_GFX kconfigSubrata Banik
This patch creates new kconfig option to bring display over external PCI based GFX card. This kconfig to select required kconfig which are not default selected by VGA_ROM_RUN to launch legacy oprom from pci based GFX card. Change-Id: I8ebde69e38defbe3321eb5e5bbd632c209ae2cd8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-07-24soc/intel/common: Set controller state to active in GSPI initMeera Ravindranath
Set the controller state to D0 during the GSPI sequence,this ensures the controller is up and active. BUG=b:135941367 TEST=Verify no timeouts seen during GSPI controller enumeration sequence for CML and ICL platforms. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I2f95059453ca5565a38650b147590ece4d8bf5ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/34449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-07-24soc/intel/common: Set controller state to active in uart initUsha P
Set the controller state to D0 during the uart init sequence, this ensures the controller is up and active. One more argument struct device *dev has been added to uart_lpss_init function for the same. BUG=b:135941367 TEST=Verify no timeouts seen during UART controller enumeration sequence in CML and ICL platforms. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I0187267670e1dea3e1d5e83d0b29967724d6063e Reviewed-on: https://review.coreboot.org/c/coreboot/+/34447 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-23mediatek/mt8183: Add md power-off flowYanjie Jiang
SRCCLKENA holds 26M clock, which will fail suspend/resume, and the SRCCLKENA is not used by mt8183, so we can simply release it for suspend/resume to work. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui, suspend test pass. Change-Id: Ib6e11faeb6936a1dd6bbe8b1a8b612446bf51082 Signed-off-by: Yanjie.jiang <yanjie.jiang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32666 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-22soc/mediatek/mt8183: Support SSPMErin Lo
SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. BUG=b:80501386 BRANCH=none Test=Build pass Change-Id: I4ae6034454326f5115cd3948819adc448b67fb1c Signed-off-by: Erin Lo <erin.lo@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31516 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-22soc/intel/broadwell: Change variable back to u32Jacob Garber
commit bde6d309df (x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer) accidentally changed the type of reg32 to a u8 *, so change it back to a u32. Change-Id: If6beff17ed3ddf85889aba5f41d1ba112cd74075 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402160 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-21mediatek/mt8183: Calibrate RTC eosc clockRan Bi
Calibrate RTC eosc clock which will be used when RTC goes into low power state. BUG=b:133872611 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ie8fd6f4cffdcf7cf410ce48343378a017923789c Signed-off-by: Ran Bi <ran.bi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-07-21soc/intel: Expand SA_DEV_ROOT for ramstageKyösti Mälkki
We do not want to disguise somewhat complex function calls as simple macros. Change-Id: I298f7f9a1c6a64cfba454e919eeaedc7bb2d4801 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21soc/intel: Change file to __SIMPLE_DEVICE__Kyösti Mälkki
All the PCI accesses in the file are now accessed without SA_DEV_ROOT expanding to function call. Change-Id: I30d331e9c18a486ea971e8397a6e20a0f82d5f84 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21soc/intel: Fix chip_info for PCH_DEV_PMCKyösti Mälkki
Since PCH_DEVFN_PMC device is a PCI device that may be hidden from enumeration, use SA_DEVFN_ROOT instead to locate the SOC configuration. Change-Id: I4b5195827fb32ec1dbd0bd6c9e243f4f9a4775ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO*Maxim Polyakov
According to the documentation [1], by default the RX Level/Edge Trig Configuration set to disable (2h = Drive '0') for each pad. Since this setting doesn't matter for the GPO pad, there is no need to change the default value for such pads. The patch updates PAD_CFG_GPO* macros to set trig to disable. It also resolves some problems of creating the PCH/SoC pads configuration based on information from the inteltool dump [2,3] [1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2, February 2019, Document Number: 332691-003EN https://www.intel.com/content/dam/www/public/us/en/documents/ datasheets/100-series-chipset-datasheet-vol-2.pdf [2] https://review.coreboot.org/c/coreboot/+/34337 [3] https://github.com/maxpoliak/pch-pads-parser/issues/1 Change-Id: I39ba83ffaad57656f31147fc72d7a708e5f61163 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21soc/intel/common: add PAD_CFG_NF_BUF_TRIG macroMaxim Polyakov
In the case there is no the circuit diagram for motherboard, the PCH/SoC GPIOs config is based on information from the inteltool dump. However, available macros from gpio_defs.h can't define the pad configuration from this dump: 0x0440: 0x0000002084000500 GPP_A8 CLKRUN# 0x0448: 0x0000102184000600 GPP_A9 CLKOUT_LPC0 0x0450: 0x0000102284000600 GPP_A10 CLKOUT_LPC1 To convert these raw DW0/DW1 register values to macros, the following parameters must be set: func - pad function, pull - termination, rst - pad reset config, trig - rx level/edge configuration, bufdis - rx/tx (in/output) buffer disable. The patch resolves the above problem by adding a new macro for the native function configuration: PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig) These changes were tested on Asrock H110M-DVS motherboard [2]. It also resolves the problem of automatically creating pads configuration [3,4] [1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2, February 2019, Document Number: 332691-003EN https://www.intel.com/content/dam/www/public/us/en/documents/ datasheets/100-series-chipset-datasheet-vol-2.pdf [2] https://review.coreboot.org/c/coreboot/+/33565 [3] https://github.com/maxpoliak/pch-pads-parser/issues/1 [4] https://github.com/maxpoliak/pch-pads-parser/commit/215d303 Change-Id: If9fe50ff9a680633db6228564345200c0e1ee3ea Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34337 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-21soc/intel/skylake: Enable Energy/Performance Bias controlMatthew Garrett
Bit 18 of MSR_POWER_CTL is documented as reserved, but we're setting it on Haswell in order to enable EPB. It seems to work on SKL/KBL as well, so do it there too. Signed-off-by: Matthew Garrett <mjg59@google.com> Change-Id: I83da1a57a04dac206cc67f2c256d0c102965abc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-21soc/amd/picasso: Remove dead SPD size Kconfig symbolMarshall Dawson
DIMM_SPD_SIZE is no longer used and should have been removed in 78025f6 "soc/amd/picasso: Remove all AGESA references". Change-Id: Iae15998835e4d8afdb44cca77d2c9009b7e3947a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-21soc/amd/picasso: Enable stage cache only with ACPI resumeMarshall Dawson
Make the option match the change in I7c3b3ec. "stoneyridge/Kconfig: Enable stage cache based on HAVE_ACPI_RESUME" Change-Id: I7fa13428ec0119b61f429116a52986067e833bdf Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-21soc/amd: Move SPI base alignment define into commonMarshall Dawson
The decision to leave the alignment in stoneyridge was driven because of a spec difference with picasso. AMD has checked the design materials and has confirmed there was no change. TEST=Build Grunt successfully BUG=b:130343127 Change-Id: If3a1d5a41dc175c9733fd09ad28627962646daf9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-19soc/intel/common/block/xhci: Add API to disable USB devicesKarthikeyan Ramasubramanian
Add API to disable USB devices that are not present but are configured in the device tree either after probing the concerned port status or as explicitly configured by the variants. BUG=None BRANCH=octopus TEST=Boot to ChromeOS. Change-Id: Ied12faabee1b8c096f2b27de89ab42ee8be5d94d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33377 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19soc/intel/common: Add SOC specific function to get XHCI USB infoKarthikeyan Ramasubramanian
It feels appropriate to define SoC specific XHCI USB info in SoC specific XHCI source file and an API to get that information instead of defining it in elog source file. This will help in other situations where the information is required. BUG=None BRANCH=None TEST=Boot to ChromeOS. Change-Id: Ie63a29a7096bfcaab87baaae947b786ab2345ed1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34290 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19src: Make implicit fall throughs explicitJacob Garber
Implicit fall throughs are a perpetual source of bugs and Coverity Scan issues, so let's squash them once and for all. GCC can flag implicit fall throughs using the -Wimplicit-fallthrough warning, and this should ensure no more enter the code base. However, many fall throughs are intentional, and we can use the following comment style to have GCC suppress the warning. switch (x) { case 1: y += 1; /* fall through */ case 2: y += 2; /* fall through - but this time with an explanation */ default: y += 3; } This patch adds comments for all remaining intentional fall throughs, and tweaks some existing fall through comments to fit the syntax that GCC expects. Change-Id: I1d75637a434a955a58d166ad203e49620d7395ed Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-18soc/intel: Use config_of()Kyösti Mälkki
Change-Id: I0727a6b327410197cf32f598d1312737744386b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian
2019-07-18soc/intel: Fix invalid use of 'static'Kyösti Mälkki
Just keep the variables on the stack. Change-Id: I36b29d8fb7dac159b29609033cba450bea9adf77 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-18soc/intel: Use config_of_path(SA_DEVFN_ROOT)Kyösti Mälkki
We do not want to disguise somewhat complex function calls as simple macros. Change-Id: I53324603c9ece1334c6e09d51338084166f7a585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34299 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-17lib: Remove the BOOTBLOCK_CUSTOM compile guardAsami Doi
This CL allows that everyone can use main() in lib/bootblock.c even if you select CONFIG_BOOTBLOCK_CUSTOM. I also rename main functions used in some soc/ to avoid the collision with the main function defined at lib/bootblock.c. Change-Id: I0575c9d1ce9dea9facfcc86760dff4deee9c1e29 Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34250 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-17amd/stoneyridge/Kconfig: Enable stage cache based on HAVE_ACPI_RESUMESubrata Banik
This patch fixes inconsistent issue with stage cache enabling with HAVE_ACPI_RESUME config enable. Only enable stage cache if CONFIG_HAVE_ACPI_RESUME=y Change-Id: I7c3b3ec4642a615e17fb3dbdedca6af8ca95ea2b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-07-17soc/rockchip/rk3288: Add fall through commentJacob Garber
Judging from the state machine on page 281 of the Rockchip RK3288 Technical Reference Manual (Rev 1.0 - Jun 2015), the fall through from the INIT_MEM -> CONF states is intentional, since that is the only way to get to the ACCESS state. Add a comment to explain this. Change-Id: I1d0cfea07211c54d6a906f5a7481c2c760f8ef0d Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1291959 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-17soc/amd/stoneyridge: Add Merlin Falcon configurationRichard Spiegel
Add config parameter for Merlin Falcon (SOC_AMD_MERLINFALCON) and modify the Makefile.inc based on this config parameter. BUG=none. TEST=Tested later with padmelon board. Change-Id: Id9f960b8f012c5a1cfd398611d6a51838493da27 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-17soc/intel/cannonlake: Add device Ids for new CFL SKUs supportLean Sheng Tan
- Add CPU, MCH & IGD IDs for new Coffeelake SKUs - Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246 - Make some minor alignments & naming corrections to align with the rest TEST= build, boot to both Linux & windows OS on CFL H & S platforms and verified all the device Id's in serial console logs. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-17soc/intel: Fix regression with hidden PCI devicesKyösti Mälkki
Fix regression with commit 903b40a soc/intel: Replace uses of dev_find_slot() Platforms where FSP hides PCI devices before enumeration may halt with error message 'PCI: dev is NULL!'. The workaround here is to print an error message revealing the faulty source code function and revert to old behaviour of dev_find_slot(). Change-Id: I5eab3e7f1993b686103eaa257aacda379dc259fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34285 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-17intel/fsp_baytrail: Avoid preprocessor with HAVE_SMI_HANDLERKyösti Mälkki
The code should probably set SCI routing if built with HAVE_SMI_HANDLER=n. Change-Id: I0ada4b2a16490a15d8036a9425c4f768f7b8f218 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-16soc/intel/{cnl,icl}: Always use CAR NEM enhanced by defaultAngel Pons
The FSP_CAR option has additional configuration options whose default values result in boot failures. Since default values should always boot, default to the open-source CAR NEM Enhanced implementation instead. This also allows us to get rid of an unnecessary vendor-specific special case. Change-Id: I30b1808f91701c07dce6f1de08c213150e8a675a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34287 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-16soc/intel/common/block/i2c: Set controller state to active in i2c initAamir Bohra
Set the controller state to D0 during the i2c init sequence, this ensures the controller is up and active. BUG=b:135941367 TEST=Verify no timeouts seen during I2C controller enumeration sequence Change-Id: I247ede44b8d1d6871e3e813b63f99a7f6398dd72 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34273 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-16soc/intel/common/block/lpss: Add provision to set controller power stateAamir Bohra
Add function to set the power state of a LPSS controller. The API implemented can be used to enforce controllers in active state(D0) during initialization. BUG=b:135941367 Change-Id: I7540924885350de64caff91d920d6cc234154616 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34272 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-15intel/cannonlake: Fix indentationKyösti Mälkki
Change-Id: Ia3ec5fbdbbf2712fe314909e05aab1b135534630 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-15src: Use '#include <timestamp.h>' when neededElyes HAOUAS
Change-Id: Ic0483982e8115ae99367d08d8ed77b8a316f5405 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-14soc/intel/icelake: Update FSP UPDs if IGD is disable in devicetreeSubrata Banik
This patch sets required FSP UPDs to skip IGD initialziation if devicetree has disable IGD. Change-Id: I34a02bff112f922cabd48c23bc76370892ec62d9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33739 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-14soc/intel/icelake: Make use of PCH_DEVFN_HDA macroSubrata Banik
Change-Id: I3be530072a6981760e9fe31e43741b4b480d045e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-13soc/nvidia/tegra124: Prevent implicit fallthroughJacob Garber
SOR_LINK_SPEED_G5_4 is unsupported, but it is not invalid, so it suffices to return here instead of printing the next warning message. Change-Id: Ifca3c52635e9a39af42e6616821d1099c43c237c Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1293137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-13soc/rockchip/rk3288/include/soc: Add missing include <types.h>Elyes HAOUAS
Change-Id: Ibde48d7cff582c91f55ad5f1328aac64d018b3c5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34235 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13soc/qualcomm: Remove unneeded '#include <lib.h>'Elyes HAOUAS
Change-Id: I39db73014c0a4456750210c002787abf9bc79fce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-13soc/intel/cannonlake: Remove unused header files from southbridge.aslAamir Bohra
Change-Id: I1f970db22f87e8eba0129ca049f75d16539644a5 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-13soc,southbridge/intel: Avoid preprocessor with HAVE_SMI_HANDLERKyösti Mälkki
Change-Id: Id375999adad71d95d4968398e90bc3c07f65ea83 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34254 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13cpu/x86: Move smm_lock() prototypeKyösti Mälkki
The function implementations are in local platform scopes. Change-Id: I7a3025398b15fe6d2c5a13cdb65f3e62a49c0bc6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34151 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSPNico Huber
We got rid of the dangerous reconfiguration of arbitrary pads in coreboot, but FSP still overrode that. Make sure that it doesn't enable a UART for debug output when it isn't configured in core- boot. This, again, shows how dangerous it is to leave any FSP UPD at its binary default. Change-Id: I7280a80f71ddddbe78352eb696e6f5844d2df0b2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-12arch, include, soc: Use common stdint.hJacob Garber
There are only minimal differences between the architecture specific stdint.h implementations, so let's tidy them up and merge them together into a single file. In particular, - Use 'unsigned long' for uintptr_t. This was already the case for x86 and riscv, while arm and mips used 'unsigned int', and arm64 and ppc64 used 'unsigned long long'. This change allows using a single integer type for uintptr_t across all architectures, and brings it into consistency with the rest of the code base, which generally uses 'unsigned long' for memory addresses anyway. This change required fixing several assumptions about integer types in the arm code. - Use _Bool as the boolean type. This is a specialized boolean type that was introduced in C99, and is preferrable over hacking booleans using integers. romcc sadly does not support _Bool, so for that we stick with the old uint8_t. - Drop the least and fast integer types. They aren't used anywhere in the code base and are an unnecessary maintenance burden. Using the standard fixed width types is essentially always better anyway. - Drop the UINT64_C() macro. It also isn't used anywhere and doesn't provide anything that a (uint64_t) cast doesn't. - Implement the rest of the MIN and MAX numerical limits. - Use static assertions to check that the integer widths are correct. Change-Id: I6b52f37793151041b7bdee9ec3708bfad69617b2 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 23:53:10 +0000