summaryrefslogtreecommitdiff
path: root/src/soc
AgeCommit message (Collapse)Author
2020-04-18soc/amd/picasso: Move BERT region to cbmemMarshall Dawson
Allocate storage for the BERT reserved memory in cbmem, and add it in response to a romstage hook. Add a Kconfig option for adjusting the size reserved. This is different from the Stoney Ridge implementation where it was intentionally oversized to ease MTRR use and to keep TSEG aligned. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4759154d394a8f5b35c0ef0a15994bbef25492e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38694 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-17soc/intel/tigerlake: Remove eMMC/SD supportDuncan Laurie
Tigerlake platform does not have built in eMMC/SD support so all this code is unused and can be removed. Change-Id: I70ff983d175375171d5a649378f32f1062c0876d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40372 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-17soc/intel: Disable config option for SCS by defaultDuncan Laurie
The eMMC/SD interface is not present in all Intel platforms so this change removes the default enable for the storage controller and instead enables it in the specific SoCs that do provide it. Currently this includes all platforms except Tigerlake. Change-Id: I8b6cab41dbd5080f4a7801f01279f47e80ceaefd Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-17intel/common: add a macro to set ownership for GPIMaxim Polyakov
Adds a new macro that allow to set the DRIVER or ACPI as host software ownership for the GPI pad using the parameter own. Thus, this macro can define more variants for pad configuration than others. This is necessary to describe in more detail the configuration for the Tioga Pass OCP server [1] and other boards. In addition, these changes will be used to automatically generate macros [2] and great simplify this task. [1] https://review.coreboot.org/c/coreboot/+/39427 [2] https://review.coreboot.org/c/coreboot/+/35643 Change-Id: I9c191fb6935e94da6e296f8fee0b91a973534e1a Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-16soc/amd/common/psp: refactor psp_print_cmd_status parametersFelix Held
psp_print_cmd_status only needs data from the mbox buffer header and not the whole buffer. This avoids type casts when the buffer type isn't mbox_default_buffer. BUG=b:153677737 Change-Id: I8688b66fefe89fc4f3ce2207d4360ceb2dbaef12 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40412 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-16soc/amd/picasso: Notify PSP system is going to sleep stateMarshall Dawson
BUG=b:153677737 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ic72bd5f5710181ca4f282feba5f7531b098c907a Reviewed-on: https://review.coreboot.org/c/coreboot/+/40298 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-16soc/amd/common/psp: Add notify_sx_infoFelix Held
Add the command to tell the PSP the system is going to a sleep state. BUG=b:153677737 Change-Id: I50da358e1f8438b46dbb1bda593becf6dd4549ea Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020367 Reviewed-on: https://chromium-review.googlesource.com/2110764 Reviewed-on: https://chromium-review.googlesource.com/2121159 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-16soc/amd/psp: Add SmmInfo commandMarshall Dawson
Implement the MboxBiosCmdSmmInfo function to inform the PSP of the SoC's SMM configuration. Once the BootDone command is sent, the PSP only responds to commands where the buffer is in SMM memory. Set aside a region for the core-to-PSP command buffer and the PSP-to-core mailbox. Also add an SMM flag, which the PSP expects to read as non-zero during an SMI. Add calls to soc functions for the soc to populate the trigger info and register info (v2 only). Add functions to set up the structures needed for the SmmInfo function in Picasso support. Issue a SW SMI, and add a new handler to call the new PSP function. BUG=b:153677737 Change-Id: I10088a53e786db788740e4b388650641339dae75 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-16intel/common/block/lpc: Add new device IDs for Lewisburg PCHBryantOu
Add C621A, C627A and C629A SKU IDs. C621A is used in the Whitley Product. We need to add device ID for setting LPC resources. Refer to Intel C620 series PCH EDS (547817). Change-Id: I19a4024808d5aa72a9e7bd434613b5e7c9284db8 Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40395 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-15soc/intel/apl/report_platform.c: Fix typoAngel Pons
"Aplollolake" => "Apollolake" Change-Id: I1881d40b5f71d07d5d217b4380241cc14467fb1a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40407 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-15soc/amd/picasso: Add common PSP supportMarshall Dawson
Add a new psp.c file so the base address can be determined, and select the common/block/psp feature. BUG=b:153677737 Change-Id: I322fd11a867a817375ff38a008219f9236c4f2ea Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020368 Tested-by: Eric Peers <epeers@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40296 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-15soc/amd/common/psp: add Kconfig description to interface versionFelix Held
BUG=b:153677737 Change-Id: I5b017dfc92563ec4f0a2edb24416d6b65587d9a3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15soc/amd/common/block/psp: move psp_load_named_blob to psp_gen1.cFelix Held
This function is only needed and valid for the 1st generation PSP interface used on stoneyridge. BUG=b:153677737 Change-Id: Ia1be09c32271fe9480a0acbe324c4a45d8620882 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope typeJohn Zhao
TCSS TBT PCIE root ports scope type was mistakenly set to PCI_ENDPOINT. Fix the scope type to be PCI_SUB. BUG=b:141609884 TEST=Booted to kernel and verified no TBT PCIE root ports scope type mismatch error in kernel log. Change-Id: I844e7e9583992be496223fb51f24c5aa24fc7d21 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-14soc/intel/tigerlake: Implement CHIPSET_LOCKDOWNWonkyu Kim
BUG=b:151161585 BRANCH=none TEST=build and boot ripto/volteer and check FSP logs for lockdown parameters Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I63cec8a718285f424914e426d0399ed821588dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/39710 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14soc/intel/apollolake: Disable XHCI LFPS power managementMarx Wang
Provide the option to disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:146768983 BRANCH=None TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Marx Wang <marx.wang@intel.com> Change-Id: Ic603e3b919d8b443c6ede8bb5e46e2de07fcb856 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14soc/intel/jasperlake: Allow mainboard to override DRAM part numberMarco Chen
In order to support mainboards that do not store DRAM part number in the traditional way i.e. within the CBFS SPD for soldered memory, this change provides a runtime callback to allow mainboards to provide DRAM part number from a custom location e.g. external EEPROM on dedede. For other boards it should be a NOP since the weak implementation of mainboard_get_dram_part_num does nothing. BUG=b:152019429 Change-Id: I7ba635f5504ba288308d7d7a4935f405f289aa8d Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-14soc/intel/icelake: Add function to dump ME firmware status informationKrishna Prasad Bhat
Add a function to dump ME Host Firmware Status registers. BUG=None BRANCH=None TEST=Build and boot iclrvp. Change-Id: I9430189665c94decb2e64680d28a7390ee6e912c Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-04-14soc/intel/tigerlake: Add function to dump ME firmware status informationKrishna Prasad Bhat
Add a function to dump ME Host Firmware Status registers. In tigerlake, Manufacturing mode is “No” if below conditions are satisfied, indicating end of manufacturing. Otherwise, manufacturing mode is "Yes". 1. Intel fuses are programmed (Indicated by HFSTS6[30] bit set) 2. The SPI flash descriptor region is locked. (Indicated by HFSTS1[4] cleared) BUG=None BRANCH=None TEST=Build and boot tglrvp. Change-Id: I831a51f9f482425bd3b97ef1d2404b1d06844d07 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-04-14soc/intel/{icl,tgl}: Make use of print_me_fw_version() from CSE libKrishna Prasad Bhat
Make use of print_me_fw_version() which is defined in the CSE lib to print ME firmware version information for icl,tgl. BUG=None BRANCH=None TEST=Build and boot iclrvp, tglrvp boards. Change-Id: Ief75403c490eee499a84372e54fa38ea3016cc11 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-04-14soc/intel/tigerlake: Configure RP settingWonkyu Kim
Add LTR and AER configuration to the root ports config. BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I668f2e5fea15019a9e5ae06fb4d55fa2aea69e8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/40262 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-13acpi: Bump FADT to revision 6Patrick Rudolph
Some of the revision 4 FADT fields were already updated to ACPI spec revision 6, but not all of them. In addition the advertised FADT revision was 3. Implement all fields as defined in version 6 and bump the advertised FADT revision to 6. Also set all used access_size fields and x_gpe0_blk to sane values as Windows 10 verifies those fields starting with FADT revision 5. Fixes: https://ticket.coreboot.org/issues/109 Tested on Windows 10. Change-Id: Ic649040025cd09ed3e490a521439ca4e681afbbf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-04-13soc/amd/common/psp: Split mailbox support into v1 and v2Marshall Dawson
Family 17h redefines the PSP command and status, and therefore the steps required to send commands via the mailbox. Convert the existing version into a v1 and add a v2. New Kconfig options allow the soc to choose v1 vs. v2. The v2 PSP begins responding to the mailbox command when the full bit range is written. Define the new mailbox as a union of a u32 and a structure. Additional PSP details may be found in the NDA publication (#55758) AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors Change the existing two soc functions that return pointers to void pointers. BUG=b:153677737 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4d358fdae07da471640856f57568059e9487f6a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-13soc/amd/picasso/soc_util: add TODO to Dali detectionFelix Held
Change-Id: I8ff5a9275d4cdf0049b63cc30b8a1cc376b50f80 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-13soc/intel/tigerlake: Remove scs.aslAamir Bohra
Remove EMMC and SD card ACPI devices copied from Ice Lake. Tiger Lake does not support these controllers. BUG=b:151208782 TEST= Build volteer board Change-Id: I4b3e37f93b94757d16d775fb27bee644d9dc539e Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40228 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-11soc/intel/tigerlake: Disable MrcSafeConfigSrinidhi N Kaushik
This change disables MrcSafeConfig option during MRC training. MrcSafeConfig was enabled as part of the early testing. Now with FSP 2527, there is no need to set this config anymore. BUG=b:150357377 BRANCH=master TEST=build and boot ripto/volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I4e4069d83754aaf1e4885d6912ab2a6d506c5269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40106 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10soc/intel/jasperlake: Publish EMMC and SD card ACPI devicesAamir Bohra
BUG=b:150872580 TEST=Build waddledoo board. Verify EMMC and SD card ACPI devices are present in dsdt.asl. Change-Id: I70d47455c48990afe9e79c013c5272d70f4f71e7 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-04-10soc/intel/jasperlake: Publish single GPIO ACPI deviceAamir Bohra
Current pin-ctrl kernel v5.4 driver expects the firmware to publish single GPIO ACPI device. Until kernel pin-ctrl driver implementation is updated to consume community based GPIO ACPI device, update the current ACPI code to comply with pin-ctrl driver requirement. BUG=b:150154277 TEST=Verify intel pin-ctrl driver can successfully load in OS Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: Ifcc92adaee550182ab405541ea85019f31bb8658 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-04-10Replace DEVICE_NOOP with noop_(set|read)_resourcesNico Huber
`.read_resources` and `.set_resources` are the only two device operations that are considered mandatory. Other function pointers can be left NULL. Having dedicated no-op implementations for the two mandatory fields should stop the leaking of no-op pointers to other fields. Change-Id: I6469a7568dc24317c95e238749d878e798b0a362 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10Drop unnecessary DEVICE_NOOP entriesNico Huber
Providing an explicit no-op function pointer is only necessary for `.read_resources` and `.set_resources`. All other device-operation pointers are optional and can be NULL. Change-Id: I3d139f7be86180558cabec04b8566873062e33be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10soc/intel/tigerlake: Add support to initialize DDR4 MemoryVarun Joshi
Support to configure DDR4 memory variant. -Add support to read SPD data based on different memory topology. -Initialize FSP UPD's for DQ and DQS mapping. BUG=b:151702387 Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com> Change-Id: I47a5dcad3ee316871a6103b9d53ef7f6fc88d7d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39847 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-09soc/intel/cannonlake: Steal no memory for disabled IGDChristian Walter
Set IgdDvmt50PreAlloc to zero if InternalGfx is disabled. It's 'correct' to do it like this, otherwise the FSP would always allocate memory for the IGD even if it is disabled. In addition the FSP enables the graphics panel power even if no IGD is present which leads to a crashing FSP. Thus, if no IGD is present we switch off the panel via UPDs. Refer to this issue on IntelFSP for details: https://github.com/IntelFsp/FSP/issues/49 Tested on: * CFL platform with IGD * CFL platform without IGD Change-Id: I6f9e0f9855224614471d8ed23bf2a9786386ddca Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-04-09soc/intel: Remove unneeded whitespacesElyes HAOUAS
Change-Id: Ib156ebede1ee24a1c7bd20d01792ec80cba8f37d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-08soc/amd/picasso: replace get_soc_config with config_of_socFelix Held
get_soc_config was a reimplementation of config_of_soc, so drop get_soc_config and cfg_util.c. Change-Id: I007c83cfe5063130c18819925844b6c643cf0232 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-08soc/amd/stoneyridge: replace get_soc_config with config_of_socFelix Held
get_soc_config was a reimplementation of config_of_soc. Change-Id: I73c6a84703e22d6778b830f4bb82419361c85ff7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-04-07soc/xeon_sp: add configs to use common/gpio diverMaxim Polyakov
Allow the use of the common/gpio driver to create Lewisburg PCH pad configurations for server motherboards with Skylake-SP processors. This patch should only be applied after adding Lewisburg PCH definitions to the soc/intel/xeon_sp code [1]. [1] https://review.coreboot.org/c/coreboot/+/39425 Change-Id: I4a8e83cad0729bbbb50ba5a2b336f6cf7c1eca13 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-07soc/intel/common: gpio: print error if pad is not foundMaxim Polyakov
Allow to print a debug error message when the GPIO community does not contain the pad number from the motherboard configuration. Change-Id: I21fb389a5d29e11b1fbc24e836d91e17957047f1 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-04-07soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driverMaxim Polyakov
Adds definitions that allow to use the common GPIO driver to configure the Lewisburg PCH pads. Using the GPIO configuration from common/gpio, unlike the FSP-style definitions from Intel RefCode [1] definitions, is more understandable and makes the motherboards code much cleaner. In addition, we can use utilities, such as inteltool, to analyze the configuration of proprietary firmware to add support for new server motherboards with Skylake-SP processors. The pin layout in this patch corresponds to the pinctrl driver in the Linux kernel v4.14 for the Lewisburg PCH GPIO controller [2]. [1] https://designintools.intel.com/product_p/stlgrn45.htm [2] drivers/pinctrl/intel/pinctrl-lewisburg.c These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US. Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39425 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-07soc/intel/tigerlake/acpi: Fix typo in HDA in commentSubrata Banik
HSA -> HDA (High Definition Audio) Change-Id: Ic0e6ad7b26105fdd6eca6cd11edcf2236e5c7123 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-07soc/intel/tigerlake: Allow mainboard to override DRAM part numberMarco Chen
In order to support mainboards that do not store DRAM part number in the traditional way i.e. within the CBFS SPD for soldered memory, this change provides a runtime callback to allow mainboards to provide DRAM part number from a custom location e.g. external EEPROM on volteer / dedede. For other boards it should be a NOP since the weak implementation of mainboard_get_dram_part_num does nothing. BUG=b:152019429 Change-Id: If940a76d36a7645a7441ba418aa7aec9af9f6319 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-04-06soc/intel/tigerlake: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I482715c166ccf5d2f3cc25118d25b07dbfd6650a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-06soc/intel/quark: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I3fdfa159194cccf15c0284700f554d2241dad6cd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-06soc/intel/jasperlake: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I2efdeb224c478995d393aa3eaac762c876832391 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-06soc/intel/icelake: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I1edbc8bb0efaad033385f29f8a4747bd178296b9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-06soc/intel/denverton_ns: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ib1e226e7816efbc5cffc95563b440fb2ad5b1f95 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-06soc/intel/cannonlake: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I48422453735d50eb9292f39a3c031073d647a17c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-06soc/intel/broadwell: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I8995372760543e9cf2c845019f7a063046c55e9c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-06soc/intel/baytrail: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ib41169395ab239e520f6047ac6bd307ec50776d4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-06soc/intel/common: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ic5a920bfe1059534566ceab85a97219dd56f069e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-06soc/intel/braswell: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I45d746ed374361036d59167293a90d8e557754fa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-06soc/intel/skylake: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I7354edb15ca9cbe181739bc2a148f16bb85ab118 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-06soc/intel/xeon_sp: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I703a656c397345025dab398fb642f3de7bbb61fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40220 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06soc/intel/apollolake: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I3c6daa484a4aa133ff2ad79eb2b8efa159da3523 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-06soc/rockchip: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I773cc57197b29fd3f4522aece4c83b3dc9e646e0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-06soc/samsung: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I25b9bbe320be891985e5fb42a0c3f1c763a833db Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40136 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06soc/cavium: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I3d872f63d56711d39c8320ace2642cea2a23f545 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-06soc/nvidia: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Id987662ba96ad7e78e76aa5a66a59b313e82f724 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40133 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06soc/intel/common: Remove unused Kconfig SKIP_GRAPHICS_ENABLINGRonak Kanabar
It is use to skip GT specific programming in ICL, TGL and JSL. In following patches use of SKIP_GRAPHICS_ENABLING is removed. b6a523927d (soc/intel/jasperlake: Remove DDI A lane programming) e5565c45cb (soc/intel/{icelake, tigerlake}: Remove DDI A lane programming) TEST=checked iclrvp, jslrvp and tglrvp compilation. Change-Id: Ie337fd727d72118c43aa869da1446ea4fceadc5b Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-04-06soc/intel/jasperlake: Remove DDI A lane programmingRonak Kanabar
For newer Intel graphics (>=11), the DDI port max lanes default to 4. And kernel driver no longer relies on coreboot to provide information via DDI_BUF_CTL_A (for DDI port A) register programming. Hence removing this code. BUG=b:150788968 BRANCH=None TEST=checked jslrvp compilation and boot. Change-Id: I4c171ec6a57d6fc53bee88420bfb3c0fbc5dc057 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40038 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-05fsp2_0: Gather Kconfig declarationsNico Huber
Move more Kconfig declarations to drivers/intel/fsp2_0/ and document them properly. This way, we don't have to repeat dependencies and have the prompts in a common place. We can also easily hide the prompt for the header path in case the FSP repository is used. SP platforms were skipped as their Kconfig is too weird but they shouldn't hold other platforms back. Change-Id: Iba5af49bcd15427e9eb9b111e6c4cc9bcb7adcae Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-05soc/intel/apollolake: Don't select repo option for Gemini LakeNico Huber
Change-Id: I70fbc0c2959acba71cbb3b2c7b6c0d6d743c91e5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40124 Reviewed-by: Mimoja <coreboot@mimoja.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-05soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD.Srinidhi N Kaushik
This change updates memory configuration on Tiger Lake Platform to replace "Reserved9" with "DisableDimmCh#" UPD in init_spd_upds(). For reference https://review.coreboot.org/c/coreboot/+/39797 added "DisableDimmCh#" UPD. BUG=b:152000235 BRANCH=none TEST= build volteer and boot to kernel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie0b5783a8bef02ec8c265fa5b47ce532a77b9675 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40061 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-05soc/mediatek: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I7c3c75eaf2d7a64e7d833541bcf168b93921a142 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-05soc/qualcomm: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ie78224f9bedd6ec3f0f10a58bb5dceeb35b73241 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-05soc/sifive: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I149d06d6241f81b535f64720d61bbd0c198caeda Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-05soc/ucb: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I1b7a4fd5c6049230799d9e77903382812bc9768d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-05soc/amd: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I22fffa0eab006be2bad4d3dd776b22ad9830faef Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-05Drop explicit NULL initializations from `device_operations`Elyes HAOUAS
Unmentioned fields are initialized with 0 (or NULL) implicitly. Beside that, the struct has grown over the years. There are too many optional fields to list them all. Change-Id: Icb9e14c58153d7c14817bcde148e86e977666e4b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40126 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-04soc/intel/xeon_sp/cpx: Add multi-core initAndrey Petrov
Add minimal MP init. No SMM, no turbo, not c/p states. TEST=boot linux kernel, observe CPUs are online, schedule tasks and perform useful work. Tested on Cedar Island CRB with only 1 socket populated Change-Id: I0af374ab3956009e9208917d911d29eb21db6069 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-04-03soc/intel/skylake: vr_config: enable PSI3 and PSI4 by defaultMichael Niewöhner
There are boards that do not need a specific domain_vr_config because the defaults provided by the soc code are sufficient. Currently, this means that these boards can't benefit from lower power states (PSI 3 and 4) because the settings default to being disabled since at the time the defaults have been defined (2015) there were bugs in FSP in this regard. Set the default values of psiXenable to 1 for boards that do not have a domain_vr_config setting in their devicetree, just like Cannon Lake does. Boards that have a domain_vr_config and set their specific settings are not affected at all. Currently, there are only three boards that have no domain_vr_config: - supermicro/x11-lga1151-series These boards have a MPS MP2955 which we can assume support for PS3 (the MP2965 and MP2935 support it, too). S-series CPUs with a 1151 socket do not have C9/C10 but only C8 and since only C10 makes use of PS4, those CPUs won't ever request PS4. That means we do not need to disable it explicitly for these boards. - 51nb/x210: Needs testing and/or VR datasheet check for PS3/PS4 support Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39980 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02soc/intel/braswell: add ACPI backlight supportMatt DeVillier
Add hook to generate ACPI methods in SSDT for screen backlight control. To make use of this, individual boards will need to include default_brightness_levels.asl in their dsdt, as well as add 'register "gfx" = "GMA_STATIC_DISPLAYS(0)"' to their devicetree. Change-Id: I0adccc6c8bee71d3c1b7840518308c8dc8ea2d81 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02soc/intel/baytrail: add ACPI backlight supportMatt DeVillier
Add hook to generate ACPI methods in SSDT for screen backlight control. To make use of this, individual boards will need to include default_brightness_levels.asl in their dsdt, as well as add 'register "gfx" = "GMA_STATIC_DISPLAYS(0)"' to their devicetree. Change-Id: I0b7fc45bda3aaf89306bedb579fb1e9f8ce07926 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02soc/intel/broadwell: add ACPI backlight supportMatt DeVillier
Add framework to generate ACPI methods in SSDT for screen backlight control. Adjust params for gtt_ methods to match prototypes in i915.h and avoid conflicts. To make use of this, individual boards will need to include default_brightness_levels.asl in their dsdt, as well as add 'register "gfx" = "GMA_STATIC_DISPLAYS(0)"' to their devicetree. Change-Id: If93b7690ef36b5d19ca43957e8a1bef91ec5821d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02soc/intel/tigerlake: Add macros and SPD information for DDR4Furquan Shaikh
This change adds new memory topologies (SODIMM, MIXED) that are supported by DDR4 and macros required for DDR4 support. Memory initialization support for DDR4 will be added in a follow-up change. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I4b565c3d71bbf437da64ac29597cc19e58f1b98a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-02soc/intel/tigerlake: Reorganize memory initialization supportFurquan Shaikh
This change reorganizes memory initialization code for LPDDR4x on TGL to allow sharing of code when adding support for other memory types. In follow-up changes, support for DDR4 will be added. 1. It adds configuration for memory topology which is currently only MEMORY_DOWN, however DDR4 requires more topologies to be supported. 2. spd_info structure is organized to allow mixed topologies as well. 3. DQ/DQS maps are organized to reflect hardware configuration. TEST=Verified that volteer still boots and memory initialization is successful. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-02soc/amd/common/psp: Move definitions into a private fileMarshall Dawson
Declutter psp.h by removing internal details the caller doesn't need to know. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: I2fb0ed1d2697c313fb8475e3f00482899e729130 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020366 Tested-by: Eric Peers <epeers@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40015 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02soc/amd/common/psp: Move early init to socFelix Held
The initialization code in common//psp is very specific to Family 15h. Move this to the stoneyridge directory. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: Ice3d06d6437f59a529c26fc2359565c940d39482 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020365 Reviewed-by: Eric Peers <epeers@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-02soc/amd/common/psp: Consolidate FW blob load functionsMarshall Dawson
The commands used in Family 15h for loading the SMU FW blobs out of flash had already been defined differently in Family 17h. To begin removing Family 15h dependencies from the common/psp, change the definitions of blob type to no longer match the Family 15h commands. Consolidate the two functions used for interpreting the command and applying the command into a single one. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: Ic5a4926175d50c01b70ff9b10908c38b3cbe8f35 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020364 Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Tested-by: Eric Peers <epeers@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-02soc/amd/common/psp: Make common function to print statusMarshall Dawson
Consolidate commands' printing of status into one static function. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: Id8abe0d1d4ac87f6d4f625593f47bf484729906f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020363 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Eric Peers <epeers@google.com> Tested-by: Eric Peers <epeers@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39998 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-01soc/intel/tigerlake: Remove Jasper Lake SoC referencesAamir Bohra
This implementation removes all JSL references from the TGL SoC code. Additionally, mainboard code changes are done to support build. BUG=b:150217037 TEST=build tglrvp and volteer Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-01soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoCAamir Bohra
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop referring from soc/intel/tigerlake. Addtionally mainboard changes are done to support build. BUG=b:150217037 TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board. Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-03-31soc/intel/common/block: Add missing includeRizwan Qureshi
Include types.h in src/soc/intel/common/block/include/intelblocks/cse.h to use type bool. Without this, there can be a build error like below, src/soc/intel/common/block/include/intelblocks/cse.h:208:1: error: unknown type name 'bool'; did you mean '_Bool'? bool cse_is_hfs1_com_soft_temp_disable(void); ^~~~ _Bool src/soc/intel/common/block/include/intelblocks/cse.h:214:1: error: unknown type name 'bool'; did you mean '_Bool'? bool cse_is_hfs3_fw_sku_custom(void); Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I92ee533bca7dc255f7a341b2a68bbc09900996a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-31security/vboot: relocate and rename vboot_platform_is_resuming()Bill XIE
After measured boot is decoupled from verified boot in CB:35077, vboot_platform_is_resuming() is never vboot-specific, thus it is renamed to platform_is_resuming() and declared in bootmode.h. Change-Id: I29b5b88af0576c34c10cfbd99659a5cdc0c75842 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-31soc/intel/common/block/cse: Add check for CSE enabledWim Vervoorn
Exit print_me_fw_version if CSE is disabled. BUG=N/A TEST=tested on facebook monolith Change-Id: Ie3f1c2a5a7f96371a0da872efc3308850c382ba7 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-31security/vboot: Decouple measured boot from verified bootBill XIE
Currently, those who want to use measured boot implemented within vboot should enable verified boot first, along with sections such as GBB and RW slots defined with manually written fmd files, even if they do not actually want to verify anything. As discussed in CB:34977, measured boot should be decoupled from verified boot and make them two fully independent options. Crypto routines necessary for measurement could be reused, and TPM and CRTM init should be done somewhere other than vboot_logic_executed() if verified boot is not enabled. In this revision, only TCPA log is initialized during bootblock. Before TPM gets set up, digests are not measured into tpm immediately, but cached in TCPA log, and measured into determined PCRs right after TPM is up. This change allows those who do not want to use the verified boot scheme implemented by vboot as well as its requirement of a more complex partition scheme designed for chromeos to make use of the measured boot functionality implemented within vboot library to measure the boot process. TODO: Measure MRC Cache somewhere, as MRC Cache has never resided in CBFS any more, so it cannot be covered by tspi_measure_cbfs_hook(). Change-Id: I1fb376b4a8b98baffaee4d574937797bba1f8aee Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-03-30intel/fsp2_0: Make FSP_USE_REPO a SoC opt-inJohanna Schander
For quite a bit now we are extending the FSP_USE_REPO option to be available for all Intel SoCs. This results in a list being not only hard to maintain but also prone to errors. To change that behaviour this commit introduces the HAVE_INTEL_FSP_REPO config option for SoCs that are supported from within 3rdparty/fsp. If a SoC selects HAVE_INTEL_FSP_REPO the config option FSP_USE_REPO is selected by default, but can be still deselected by the user in menuconfig. Change-Id: I68ae373ce591f06073064aa75aac32ceca8fa1cc Signed-off-by: Johanna Schander <coreboot@mimoja.de> Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37582 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30soc/intel/{icelake, tigerlake}: Remove DDI A lane programmingRonak Kanabar
For newer Intel graphics(>=11), The DDI port max lanes are set to 4 by default. And kernel driver no longer relies on coreboot to provide information via DDI_BUF_CTL_A(for DDI port A) register programming. Hence removing this code. BUG=b:150788968 BRANCH=None TEST=checked jslrvp and tglrvp compilation and boot. Change-Id: I32692501b60f48a07b8fbb9bb3a755b18f4b3ea9 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39313 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30soc/amd/picasso: Add helper functions for finding SOC typeMartin Roth
We're running into more and more situations where we need to tell one SOC type from another, and instead of rewriting them every time, just add some helper functions to the picasso SOC directory. Change-Id: I24b73145cdfa80c09fbe036d1fb6079696c6d013 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/2051514 Reviewed-on: https://chromium-review.googlesource.com/2060904 Reviewed-on: https://chromium-review.googlesource.com/2060905 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-30soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3Brandon Breitenstein
FSP UPD TcssAuxOri is used for setting the IOM_TYPEC_SW_CONFIGURATION_3. Configure TcssAuxOri to retimer enabled on the port 2 Type-C port. This setting informs the SoC that a retimer is taking care of SBU orientation therefore it does not need to do any flipping. The IOM_TYPEC_SW_CONFIGURATION_3 is a bitfield that controls the aux orientation settings for the Type-C ports. The TGL EDS describes this setting and what each bit represents. Reference section 3.6.5 in TGL EDS #575681 BUG=b:145943811 BRANCH=none TEST=Boot to OS and check Type-C port1 Display on volteer, Connecting Type-C display should work regardless of Type-C cable orientation. Change-Id: Iae356113cbdc72983f800060b1ebebe3c66b9daf Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39459 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-29soc/amd/picasso: Add and use CPUID defines for Picasso and Raven2Martin Roth
Change-Id: I35a1c404ff2f381d3d6bf4f2e4bbbf5429db38c3 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1961485 Reviewed-on: https://chromium-review.googlesource.com/2060905 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-29soc/amd/picasso: Add Kconfig option for chip footprintFelix Held
Pollock uses the FT5 footprint, so add the Kconfig option to allow us to differentiate the chips. Change-Id: Ia4663d38f1824786f14b6aa000adf27d64e70b5f Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/2051509 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Eric Peers <epeers@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-28soc/intel/skylake: Hook up GMA ACPI brightness controlsMatt DeVillier
Add struct i915_gpu_controller_info for boards to supply info needed to generate ACPI backlight control SSDT. Hook into soc/common framework by implementing intel_igd_get_controller_info(). Change-Id: I70e280e54d78e69a335f9a382261193c593ce430 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-28soc/intel/common: Hook up GMA ACPI brightness controlsMatt DeVillier
Add framework to hook up the generic src/drivers/intel/gma ACPI backlight control for platforms using SOC_INTEL_COMMON_BLOCK_GRAPHICS. Add a weak function to get the struct i915_gpu_controller_info needed to generate the SSDT, defaulting to NULL, which SoC's will override. Each SoC will need to override intel_igd_get_controller_info, and individual boards will need to populate the struct in order for the backlight control methods to be added to the SSDT. Change-Id: I993770fdcd0a28cee756df2bd6a795498f175952 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32549 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-28soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper LakeAamir Bohra
This is a follow-up patch to initial copy patch for Jasper Lake SoC. Remove all Tiger Lake specfic code from Jasper Lake SoC code. BUG=b:150217037 Change-Id: I44dc6bf55ca18a3f0c350f5c3e9fae2996958648 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39824 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-28soc/intel/jasperlake: Add Jasper Lake SoC supportAamir Bohra
This is a copy patch from Tiger Lake SoC code. The only changes done on top of copy is changing below configs: 1. SOC_INTEL_TIGERLAKE -> SOC_INTEL_TIGERLAKE_COPY 2. SOC_INTEL_JASPERLAKE -> SOC_INTEL_JASPERLAKE_COPY 3. SOC_INTEL_TIGERLAKE_BASE -> SOC_INTEL_TIGERLAKE_BASE_COPY We started with initial assumption that JSL and TGL can co-exist. But now we see the SoC code in Tiger Lake is relying on too many compile-time directives to make two SoCs co-exist. Some of the differences are listed below: -> Kconfig: Multiple Kconfig options using if SOC_INTEL_{TIGERLAKE/JASPERLAKE} -> GPIO: GPIO communities have their own differences. This requires conditional checks in gpio.asl, gpio.c, gpio*.h, pmc.h and gpio.asl -> PCI IRQs: Set up differently for JSL and TGL -> PCIe: Number of Root ports differ. -> eMMC/SD: Only supported on JSL. -> USB: Number of USB port are different for JSL and TGL. -> Memory configuration parameters are different for JSL and TGL. -> FSP parameters for JSL and TGL are different. The split of JSL and TGL SoC code is planned as below: 1. Copy Tiger Lake SoC code as is, and change SoC Kconfig to avoid conflicts with current mainboard builds. 2. Clean up TGL code out of copy patch done in step 1. Make it JSL only code. The SoC config still kept as SOC_INTEL_JASPERLAKE_COPY. 3. Change JSL SOC Kconfig from SOC_INTEL_JASPERLAKE_COPY to SOC_INTEL_JASPERLAKE, dedede and jasperlake_rvp boards can bind to SoC code from soc/intel/jasperlake. This step establishes Jasper Lake as a separate SoC. 4. Clean up current JSL code from TGL code. This step establishes Tiger Lake as a separate SoC. BUG=b:150217037 Change-Id: I9c33f478a2f8ed5e2d8e7815821d13044d35d388 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-03-26soc/intel/xeon_sp: Add basic Cooperlake-SP supportAndrey Petrov
This adds barebones support. What works: * Linux kernel boots fine * SIRQ and PCH interupts work fine (only in IOAPIC mode) * PCH devices are usable What doesn't: * MP init is not there yet, only 1 CPU is up * SMM is not supported * GPIO is not available * All IIO and extended bus numbers enumeration is not yet available * Warm reset flow is untested * MRC cache save/load TEST=boots into Linux Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I7c987badc3c53f16ad178369c7e0906d6596e465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39713 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-26soc/intel/xeon_sp: Configure P2SB BAR in bootblockAndrey Petrov
In order to use early serial output we need to enable P2SB BAR0, because that allows PCR access to PCH registers. TEST=tested on OCP Tioga Pass Change-Id: I476f90b2df67b8045582f0b72dd680dea5a9a275 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-26soc/intel/xeon_sp: Refactor code to allow for additional CPUs typesAndrey Petrov
Refactor the code and split it into Xeon common and CPU-specific code. Move most Skylake-SP code into skx/ and keep common code in the current folder. This is a preparation for future work that will enable next generation server CPU. TEST=Tested on OCP Tioga Pass. There does not seem to be degradation of stability as far as I could tell. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25create stdio.h and stdarg.h for {,v}snprintfJoel Kitching
Sometimes coreboot needs to compile external code (e.g. vboot_reference) using its own set of system header files. When these headers don't line up with C Standard Library, it causes problems. Create stdio.h and stdarg.h header files. Relocate snprintf into stdio.h and vsnprintf into stdarg.h from string.h. Chain include these header files from string.h, since coreboot doesn't care so much about the legacy POSIX location of these functions. Also move va_* definitions from vtxprintf.h into stdarg.h where they belong (in POSIX). Just use our own definitions regardless of GCC or LLVM. Add string.h header to a few C files which should have had it in the first place. BUG=b:124141368 TEST=make clean && make test-abuild BRANCH=none Change-Id: I7223cb96e745e11c82d4012c6671a51ced3297c2 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>