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2020-01-28drivers/spi/spi_flash: remove spi flash namesAaron Durbin
The names of each spi flash cause quite a bit of bloat in the text size of each stage/program. Remove the name entirely from spi flash in order to reduce overhead. In order to pack space as closely as possible the previous 32-bit id and mask were split into 2 16-bit ids and masks. On Chrome OS build of Aleena there's a savings of >2.21KiB in each of verstage, romstage, and ramstage. Change-Id: Ie98f7e1c7d116c5d7b4bf78605f62fee89dee0a5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-01-28commonlib: Add commonlib/bsdJulius Werner
This patch creates a new commonlib/bsd subdirectory with a similar purpose to the existing commonlib, with the difference that all files under this subdirectory shall be licensed under the BSD-3-Clause license (or compatible permissive license). The goal is to allow more code to be shared with libpayload in the future. Initially, I'm going to move a few files there that have already been BSD-licensed in the existing commonlib. I am also exracting most contents of the often-needed <commonlib/helpers.h> as long as they have either been written by me (and are hereby relicensed) or have an existing equivalent in BSD-licensed libpayload code. I am also relicensing <commonlib/compression.h> (written by me) and <commonlib/compiler.h> (same stuff exists in libpayload). Finally, I am extracting the cb_err error code definitions from <types.h> into a new BSD-licensed header so that future commonlib/bsd code can build upon a common set of error values. I am making the assumption here that the enum constants and the half-sentence fragments of documentation next to them by themselves do not meet the threshold of copyrightability. Change-Id: I316cea70930f131e8e93d4218542ddb5ae4b63a2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-26soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheetSubrata Banik
This patch updates SA DRAM registers bit definitions as per SKL datasheet vol 2, doc 332688. TEST=Build and boot EVE and Soraka to OS. Change-Id: Ia32723444c044572fbcecce151d89e739e570b3b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-26soc/intel/skylake: Add _SEG/_UID name variablesSubrata Banik
TEST=Build and boot EVE and Soraka to OS. Change-Id: Ic765dc2a7a522872ee991e47e3608f60a0e6411a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38513 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-26soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 deviceSubrata Banik
As per PC client TPM specification, the TPM description contains the base address of the TIS interface 0xfed40000 and the size of the MMIO area is 20KB (0x5000). Hence ACPI used to reserve those fixed system memory from getting used by OS. Platform with TPM_CR50 doesn't require fixed SoC mapped memory hence additional reservation might not required. TEST=Build and boot EVE and Soraka to OS. Change-Id: Id02a2659ce42f705180370000df89d4f6b64afce Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38512 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-25soc/intel/tigerlake: Add IPU in ACPIWonkyu Kim
Add IPU ACPI object for Camera ACPI. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I8c1ca9c053f0c8ef8d7c027c317c7af74d5f0f8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/38469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-01-25soc/intel/tigerlake: Configure ClkReq according to mainboard designWonkyu Kim
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from NVMe Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I14997e0a7d03bf1a97d115cbf0a7ad2603ef9953 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38285 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-25soc/intel/tigerlake: Add GPIO helper functionShaunak Saha
This patch adds ASL methods like GRXS, GTXS, STXS and CTXS which are used to get, set and clear gpio values. We use ASL 2.0 syntax here for gpio.asl. BUG=b:144680462 BRANCH=none TEST=Build and boot tigerlake rvp board Change-Id: I17e75ff2a7cb67e94669059a1ed9d73a720ebcb1 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38442 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-25soc/intel/tigerlake: Fix GPIO communitiesShaunak Saha
GPIOs are divided into different communities. Each community consists of one or more GPIO groups. We need to configure the groups in coreboot so that they are mapped properly. GPIO comuinities in coreboot should match with the kernel gpio communities also. Kernel reads the ASL file from coreboot. This patch adds the proper community mapping in ASL code to match with kernel code. In gpio_soc_defs.c file we are indexing the groups correctly. In gpio.h file we define all the gpio devices as kernel populates sysfs with separate gpio device for each community. This patch is created based on Intel Tiger Lake Processor PCH Datasheet with Document number:575857 and Chapter number:27. BUG=b:144680462 BRANCH=none TEST=Build and boot tigerlake rvp board. In /sys/kernel/debug/pinctrl verify INTC34C5:0<1-3> listing all the pins for each community. e.g., #cat /sys/kernel/debug/pinctrl/INT34C5:00/pins should list all the community 0 pins. Change-Id: I40c386db060d84c1b7fba9c587f960d6a92f84ba Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-01-24soc/intel/skylake: Remove unused ICH memory referenceSubrata Banik
TEST=Build and boot EVE and Soraka to OS. Change-Id: Ic7840ce264393b4a955f17b16f5e0f556e34a776 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38511 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-24soc/intel/skylake: Move pci_irqs.asl from SA to PCHSubrata Banik
SoC handles PCI IRQs programming inside PCH related ASL. TEST=Build and boot EVE and Soraka to OS. Change-Id: If95101193fa1b528dc64f57c0fc12f13f16d82b4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-24soc/intel/tigerlake: Enable SATAWonkyu Kim
Configure SATA FSP UPD according to mainboard design. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38504 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-23soc/intel/common: Update SA bit fields as per EDSSubrata Banik
This patch updates system agent related registers bit definitions as per EDS. For example: As per CNL/ICL EDS MCHBAR register base is between bit 16-38 but coreboot programming was not aligned with EDS previously. CNL EDS doc number: 566216 Also provide provision to program 64bit values as per SA EDS definitions TEST=Dump MCHBAR in coreboot and ASL shows same 32 bit value. Change-Id: I37340408fe89c94ce81953c751c8d7e22bc81a42 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-22soc/intel/tigerlake: enable gpio dual route supportNick Vaccaro
Enable SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT for tigerlake. BUG=b:142961277, b:145494156 BRANCH=none TEST=none Change-Id: I1f785f410982f7d7598942f9b12196851e77c240 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37629 Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22soc/intel/tigerlake: Update fsp_params for TGLSrinidhi N Kaushik
Add initial fsp upd settings for TGL, both romstage and ramstage upd's to support basic build and boot of TGL RVP. - Add Silicon upd settings which includes * Serial IO/UART settings * Graphics settings * USB2/USB3 settings - Add Romstage upd settings which includes * Pcie Root port settings * IGD initialization * Hyper Threading settings * SMBus controller settings * Debug probe settings BUG=none BRANCH=none TEST=Build and boot Tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I16df66451fd3a681df1222d283d97dd6bdaff0e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37960 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22soc/intel/tigerlake: Update GPIO configRavi Sarawadi
GPIOs are divided into different communities. Each community consists of one or more GPIO groups. We need to configure the groups from coreboot so that they are mapped properly. GPIO communities should be properly configured in GPIO_CFG and MISCCFG registers. GPP_* defines in gpio_soc_defs.h are configured in GPIO_CFG register while the PMC_GPP_* in pmc.h are used to configure the MISCCFG registers. BUG=b:144680462 BRANCH=none TEST=Build and boot tigerlake rvp board. Verified that after setting the gpe from devicetree the GPP_EN register for that community gets updated setting that specific bit. From the iotools i checked that GPE_EN register for that community is updated with that specific bit set to 1. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/37427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-01-22soc/intel/common: Add Elkhartlake Device IDsTan, Lean Sheng
Add Elkhartlake CPU, SA and PCH IDs. EHL PCH is code named as MCC. Also add a MCH ID (JSL_EHL) which is shared by both JSL and EHL SKUs. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I03f15832143bcc3095a3936c65fbc30a95e7f0f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38489 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22soc/intel/tigerlake: Update interrupt infoWonkyu Kim
Update interrupt header and interrupt mapping per Intel Silcon reference code. Need to match pci_irqs.asl with FSP setting which followed by PCH BIOS spec. Reference PCH BIOS spec#613495 https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSiliconPkg /IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/PeiItssPolicyLibVer2.c BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Iffc4efad4d0aa55fc0de88d7fe32c0356dbc3c60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38258 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22{soc,southbridge}/*/*/acpi: Add possibility to disable S4Wim Vervoorn
Some boards don't support S3 or S4. The S4 state can't be removed from the available sleep states. Add a config item that allows removal of the S4 state from the list of available sleep states. The S4 state can be removed by selecting the item on board level. For the AMD chipsets the SSFG mask is updated to remove the S4 state. BUG=N/A TEST=build Change-Id: Id802c4cc40308ddf39e99e7f226d55e0e020f0c9 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38431 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20soc/amd/picasso: Add SMMSTORE supportMarshall Dawson
Add SMMSTORE support for saving EFI NVRAM variables in conjuction with Tianocore payload. Test: none, as this duplicates tested functionality in amd/stoneyridge. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Id05b33edf949611c3f9eac94e7b63a4266c6c4d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-20soc/amd/stoneyridge: Add SMMSTORE supportMatt DeVillier
Add SMMSTORE support for saving EFI NVRAM variables in conjunction with Tianocore payload. Test: build/boot several google/kahlee variants, test manipulation and persistence of Tianocore bootorder variables. Change-Id: Ida604a44d1fa5288e96dbe05de1f847e597cc95d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-18soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDsGaggery Tsai
This patch adds CML-S 2 and 4-Core MCH IDs and fix wrong ID for 10-Core ID. Change-Id: I30f6c8a5234b7754d984b598bf7bae103ec9712e Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-18soc/intel/cannonlake: Add chip config for SATA strengthJamie Chen
Add config to chip.h for tuning SATA gen3 strength. BUG=b:147351936 BRANCH=none TEST=build successful in puff Change-Id: I4dcd23834fa3c01c1d88697a7bb8cf361709b62e Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38432 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/tigerlake: Update ACPI filesRavi Sarawadi
Add and update ACPI files for Tiger Lake SoC Use ASL2.0 code syntax for new acpi(camera_clock_ctl.asl) Reference PCH EDS#576591 vol1 rev1.2 PCH EDS#575857 vol2 rev1.0 BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ib82156830273c2937f5f02713ed7dd27da41c857 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37781 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/tigerlake: Update pci dev definitionWonkyu Kim
This change updates pci dev definition according to TGL EDS. Add GSPI3 case in chip.c according to updated pci dev definitions. Reference TGL Process EDS#575681 rev1.0 TGL PCH EDS#576591 rev1.2 BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I4717ac3cc877b13978b18ada504740512f10c709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38341 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/common: Fix typosSridhar Siricilla
Fix typos and replace spaces with tab in macro definitions. TEST=Build and Boot hatch board Change-Id: I43b2df7defc97aaeb7c8c9dfbe08ce78ba81f39b Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38384 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/common/cse: Add description for macrosSridhar Siricilla
Below changes are done in the patch: 1. Remove unnecessary lining, and replace spaces with tabs 2. Add description for macros 3. Correct comment mentioned for wrapper #ifndef TEST=Build and Boot hatch board Change-Id: I630446234321e7998ab42f8506a58b16e9ce4eb0 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-18soc/intel/tigerlake: Update chip filesRavi Sarawadi
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update - Update pmc_utils.c and JSL devicetree for build failure Reference PCH EDS#576591 vol1 rev1.2 BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37783 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/common/cse: Add consistent HECI command id/group id namingSridhar Siricilla
Below changes are done: 1. Consistent HECI command/group ID naming. 2. Rename macros to match with Intel ME BIOS Spec. 3. Move command ids, group ids and related macros into cse.h 4. Add description for structure members. TEST=Build and Boot hatch board. Change-Id: Ia902095483d5badf778d0c1faa6bf8cc431f0e50 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-18soc/intel/{skylake,common}/acpi/dptf/thermal.asl: Prevent iasl remarksWim Vervoorn
Prevent iasl remarks about unused parameters. BUG=N/A TEST=build Change-Id: I54fa4712e618038fdd5a96c2012c2ec64ca34706 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-18intel/apollolake: Remove CBFS locator overrideJulius Werner
This patch removes the CBFS locator override for the Apollolake SoC and instead integrates the extra sanity check it was used for straight in the boot device initializer. Change-Id: Iccdb885be233bb027a6a1f2cc79054582cbdf3fc Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-16soc/intel/{cnl,icl,skl, tgl}: Move SOC_INTEL_COMMON_BLOCK_THERMAL into SoC ↵Subrata Banik
specific Kconfig This patch moves common pch code SOC_INTEL_COMMON_BLOCK_THERMAL Kconfig selection into SoC specific Kconfig selection as PCH thermal device is not available with latest PCH (i.e. TGP and JSP). Also added TODO for TGL thermal configuration as applicable. TEST=Able to build and boot TGL RVP with this CL Change-Id: Ibce17cc9f38fb666011ccd8f97bee63033ff5302 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38444 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-15soc/intel/common/block/fast_spi: don't include all spi flash driversAaron Durbin
The fast spi driver implements hardware sequencing which abstracts away the underlying spi flash commands in the hardware block. It also has its own spi flash probe function to intercept the spi flash ops. As such it's not necessary to include all spi flash drivers. On a hatch Chrome OS build this saves 9.5KiB of text in each of verstage, romstage, and ramstage. Change-Id: Ifb1b962cde3a6a02353ddf83279234057a9ec2fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-15drives/spi/spi_flash: add option to not select all driversAaron Durbin
Add a new Kconfig option, SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS, to make it easier for other parts of the code base to indicate that all spi flash drivers should not be included. Change-Id: Ibf2c4f1d2b8a73cff14bb627ddf759d7970920ea Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-15soc/intel/tigerlake: Update header filesRavi Sarawadi
Modify header files to update/include tigerlake: - IOMAP BARs according to silicon reference code - Update Serial IO devices according to PCH EDS - Add board types BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I185f2c22c54a6ae386527069606abb52cce1ec80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-01-14sb/intel/common: Declare common smbus_base() and enable_smbus()Kyösti Mälkki
This avoids including platform-specific headers with different filenames from common code. Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-14soc/intel/baytrail: Add SOUTHBRIDGE_INTEL_COMMON_SMBUSKyösti Mälkki
Change-Id: Ie026b8c57046d951752158fd28277e338ed1421c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38236 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14soc/intel/cannonlake: Fix ASL compilation remarksSubrata Banik
This patch fixes below ASL compilation remarks 1. dsdt.asl 495: Method (_DSM, 4) Remark 2119 - ^ Control Method marked Serialized (Due to use of Switch operator) 2. dsdt.asl 721: Name(GPMB, Package(5) {0}) Remark 2063 - ^ Initializer list shorter than declared package length Change-Id: Iabd6c39025713dda7aa69cb479f003fbec8855b3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13soc/intel/tigerlake: Select correct fsp_param as per SoC KconfigMaulik V Vaghela
New Kconfig for Jasperlake soc was created and fsp_param for Jasperlake has differences compared to Tigerlake. Thus renaming fsp_params.c to fsp_params_tgl.c to point out correct file as per soc selected. Also adding new file for fsp_param_jsl for Jasperlake SoC and currently its the copy of fsp_param_tgl. TODO: update files with correct fsp_params Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37267 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-12soc/intel: Fix ACPI device operations initializationKarthikeyan Ramasubramanian
Initialize ACPI device operations only when CONFIG_HAVE_ACPI_TABLES is enabled. BUG=None TEST=Build Test Change-Id: I5c5266885d8b08338d17a87bb95110765882120e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-10{Documentation,soc/intel}: Fix typoElyes HAOUAS
Change-Id: I708ab503ece37f44cc38511aad2383ab2cec3368 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37468 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10soc/mediatek/mt8183: Restore vcore after DRAM calibrationHuayang Duan
DRAM calibration sets vcore to different voltages at different frequencies. After DRAM calibration, vcore should be restored to the default voltage, which is 800mV for both eMCP and discrete DDR devices. BRANCH=kukui BUG=b:146618163 TEST=bootup pass Change-Id: Ia87b4ac78a32dbd4c4ab52e84d307cb46525afa1 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-01-10soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource properSubrata Banik
This patch ensures coreboot is not publishing above 4GB mmio resource if soc common config "enable_above_4GB_mmio" not enable. Publishing unnecessary 4GB above MMIO resource with wrong base and size is causing problem while working with discrete GPU. Unable to boot with dGPU on IA platform with below error: [ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref] [ 2.352541] [drm] Not enough PCI address space for a large BAR. Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2020-01-09sb/intel/common: Add smbus_set_slave_addr()Kyösti Mälkki
Change-Id: I7dddb61fab00e0f4f67d4eebee0cfe8dcd99f4ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38230 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09device,sb/intel: Move SMBus host controller prototypesKyösti Mälkki
Also change some of the types to match the register widths of the controller. It is expected that these prototypes will be used with SMBus host controllers inside AMD chipsets as well, thus the change of location. Change-Id: I88fe834f3eee7b7bfeff02f91a1c25bb5aee9b65 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38226 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09soc/intel/common: Drop old forked version of SMBUS supportKyösti Mälkki
Switch to use the more recent version in sb/intel/common. Change-Id: Idbff410991db9592a58b9cc0ae7ee8c45d750b13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-09soc/intel/broadwell: Drop old forked version of SMBUS supportKyösti Mälkki
Switch to use the more recent version in sb/intel/common. Change-Id: Icbd54b5671ea2a94aea5db4642698ef679540625 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-09soc/intel/common: Remove extra call layerKyösti Mälkki
Change-Id: I6987eb58b593e1f2bc6adf91be61bf7b5382440d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38122 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09lib/spd_bin,soc/intel/common: Move get_spd_smbus()Kyösti Mälkki
Only smbuslib.c and spd_bin.c share the same prototypes for SMBUS functions. Therefore, get_spd_smbus() currently only works with soc/intel/.../smbuslib.c and can be implemented there locally. This allows removal of <device/early_smbus.h>. Change-Id: Ic2d9d83ede6388a01d40c6e4768f6bb6bf899c00 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-09soc/intel/common: Sync early SMBUS prototypesKyösti Mälkki
Change-Id: I6b4b5ffd552b9eb4467689c8df85905a1c199bb0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38120 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09drivers/pc80/rtc: Separate {get|set}_option() prototypesKyösti Mälkki
Long-term plan is to support loading runtime configuration from SPI flash as an alternative, so move these prototypes outside pc80/. Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09soc/intel/tigerlake: Update KconfigRavi Sarawadi
Update Kconfig: - use CAR NEM mode for tigerlake only as NEM Enhanced is under debug - update GSPI, RP max device #s according to PCH EDS#576591 vol1 rev1.2 - update UART M/N setting according to new PCH baseclock BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-01-09soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpiSubrata Banik
This patch creates a common instance of northbridge.asl inside intel common code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to refer northbridge.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify Device(MCHC) presence after booting to OS. Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38155 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08soc/intel/tigerlake: Fix PMC configRavi Sarawadi
Fix PMC base address for tigerlake. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Id13222eb5498a5704c11d6b4d1e83212bd8b2723 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-01-08soc/intel/cannonlake: Add VR config for CMLJamie Chen
Add VR config IccMax, DC and AC loadline defaults for CML. Add cpu_pl2_4_cfg to switch two kinds of VR design. BUG:b:145094963 BRANCH:none TEST:build coreboot and fsp with enabled fw_debug. Flashed to device and checked the log. All VR configs were set correctly. Change-Id: I3922bfad5c21dafc64fb05c7d9343b9835b58752 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
2020-01-08soc/intel/cannonlake: Add Comet Lake H SA 4+2 Device IDJamie Chen
This patch adds CML-H 4+2 SA DID into systemagent.c and report platform. According to doc #605546: CML-H (4+2) R1: 9B64h BUG:none BRANCH:none TEST:build no error Change-Id: I5bac6173a84a11abd2ce17f82854fbb14fb8558b Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
2020-01-07soc/intel/{apl,cnl,icl,skl,tgl}: Clean up SA ASL codeSubrata Banik
List of changes in this patch 1. Remove unused variables 2. Make use of absolute path 3. Define macros and use inside SA ASL 4. Rearrange code in nothbridge.asl to move MCRS object under _CRS Change-Id: Id74269ec5a96b087562ccdf2141233db5585ae59 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2020-01-06soc/intel/cannonlake: Add VR config for CFL, CNL and WHLPatrick Rudolph
Add VR config IccMax, DC and AC loadline defaults and voltage regulator maximum for all CFL, CNL and WHL. This supports mainboards with replaceable CPUs and provides sane defaults for boards that are missing the devicetree overwrite. Remove the default IccMax to make use of the introduced lookup-table. Also change some hex values to decimal. I couldn't find CML datasheet, so those are left out for now. Used Doc #337344 and #338023 Section 7. Change-Id: I1d2e174157d468830cc0baf2a2d8295ef61a1a63 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37466 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-06soc/intel/dnv: Remove commented out Kconfig optionSubrata Banik
Change-Id: Ibe646bad09dcfe348dcbfec439129b2d22ec4744 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-03soc/amd/common/block/spi: remove code duplicationAaron Durbin
This removes all the duplicated code and logic and leverages the existing ones in libraries themselves. The current side effect is that protection cannot be fully enabled because the read, write, and write enable command are not exposed in struct spi_flash currently. That support can be revised if protection scheme makes sense for our use-cases once it's better understood. BUG=b:146928174 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I8faf9cc719ee33dd9f03fb74b579b02bbc6a5e2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/37957 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-03device/early_smbus: Drop unused function parameterKyösti Mälkki
Change-Id: I2d62c470c5389af3b10e47ca5e721b78ff16bc79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-03soc/intel/common: Split some SMBUS support fileKyösti Mälkki
It is expected that smbuslib.c will be removed, leave the parts we want to keep in smbus_early.c. Change-Id: I21355fe95385d07c9f254fc80c90264a9539bb00 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-03intel/braswell: Drop use of <device/early_smbus.h>Kyösti Mälkki
Change-Id: Id3fa0745e90d8bb99965eceec0ac129fe0ff7446 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-03amdblocks/acpimmio: add missing MMIO functionsMichał Żygowski
Add missing Power Management 2, old and new GPIO functions to modify the contents of these MMIO blocks. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie4db6a4d12d9122ea5b87147adbf7b632ac2b311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-03amdblocks/biosram: Force use of abstractionKyösti Mälkki
Hide the fundamental BIOSRAM accessors to force use of the memory space via abstraction functions. Change-Id: I774b6640cdd9873f52e446c4ca41b7c537a87883 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37862 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-02amd/acpi: Drop empty PCSD device nodesNico Huber
These devices were just added in 727ac0d263 (AMD {SoC, AGESA, binaryPI}: Don't use both of _ADR and _HID), but they don't provide any information and are not referenced anywhere. Change-Id: I862a3c43eb610e488eb7d9246feb94a6d1333ca0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-02soc/intel/bsw/gpio.h: Drop unused valuesAngel Pons
Most of these are leftovers from the initial copy from Baytrail. Change-Id: I1c437f34902400022ac6a5e95ff6168545ca557f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-02src: Remove unneeded 'include <arch/io.h>'Elyes HAOUAS
Change-Id: Ie4293094ad703a2d8b68a8c640bd8d9cece2e6e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-02soc/qualcomm/qcs405: Remove unused QCS405_BLSP_SPIElyes HAOUAS
Change-Id: I73ff8adeb2751ed4035c60f7387576460bdd47e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-31src/{soc,southbridge}/amd: Fix typoElyes HAOUAS
Change-Id: I7e3dc64648af05d51a319019397f24ba74c25c37 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-31soc/intel/{icl,cnl,tgl}: Always add PM1_TMR block to FADTMeera Ravindranath
Provide the PM1_TMR information in the FADT even if PmTimerDisabled is set because PM timer emulation is enabled via MSR 121h so the timer will still work and can be used by things like Tianocore and Windows. Porting from 662b6cb3ed (soc/intel/skylake: Always add PM1_TMR block to FADT). Change-Id: Ie3d592623f3a84051477ffe83a0cf0daf30dd36f Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-27soc/amd/common: Correct SPI FIFO size checkMarshall Dawson
When checking that command and data fit in the FIFO, don't count the first byte. The command doesn't go through the FIFO. TEST=confirm error (4+68>71) goes away on Mandolin BUG=b:146225550 Change-Id: Ica2ca514deea401c9c5396913087e07a12ab3cf3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-12-27arch/x86: Remove <arch/cbfs.h>Kyösti Mälkki
There are no symmetrical headerfiles for other arch/ and after ROMCC_BOOTBLOCK and walkcbfs() removal this file ended up empty. Change-Id: Ice3047630ced1f1471775411b93be6383f53e8bb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-26soc/broadwell/minihd: correct vendor, subsystem IDsMatt DeVillier
Codec vendor ID was copy/pasted from Haswell, should be 0x80862808. Subsystem ID for Intel Mini-HD is always 0x80860101. Change-Id: Idf4446d3437de0dc533baa3b2b4eb49f816807a6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37860 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-26soc/intel/cannonlake: Move GPIO PM configuration to soc levelEric Lai
Enable GPIO clock gating when enter s0ix/Sx and save the PM bits. Restore the PM bits when exit s0ix/Sx. BUG=b:144002424 TEST=Check GPIO PM bits when enter/exit s0ix are expected Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I120f8369b8d3cf7ac821332bdfa124f6ed0570e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-26soc/amd/picasso: Configure APOB NV only with ACPI resumeMarshall Dawson
The APOB NV region holds the save data for resuming. Omit it if the mainboard doesn't use HAVE_ACPI_RESUME. The APOB information will also be board-specific so remove the default values. Change-Id: I65a70bb86ad1f3c11ce37d0afa5a6fdd08bc46e2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-12-26src: Remove unused include <string.h>Elyes HAOUAS
Change-Id: Ic6b66dd8fa387e67bb0ce609fb7e2553eeb66b3c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-12-26soc/intel/cannonlake: Clean up report_cpu_info() functionUsha P
This patch makes below clean-up for report_cpu_info() function. 1. Remove unused variables. 3. Reuse fill_processor_name. TEST = Successfully able to boot hatch and verify the cpu_name "CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz" Change-Id: I41c76eb93f0c5229c4a49ab041339b6ad51ad24a Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-12-26soc/intel/cannonlake: Refactor pch_early_init() codeUsha P
This patch keeps required pch_early_init() function like ABASE programming, GPE and RTC init into bootblock and moves remaining functions like TCO configuration and SMBus init into romstage/pch.c in order to maintain only required chipset programming for bootblock and verstage. Rename the pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=Able to build and boot hatch successfully. Change-Id: Idf7b04edc3fce147f7857561ce7d5b0cd05f43fe Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-12-26soc/intel/skylake: Rename pch_init() codeUsha P
This patch renames pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=Able to build and boot soraka successfully. Change-Id: Idf7b04edc3fce147f7957561ce7d5a0cd05f53fe Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-12-26soc/amd/common/car: Remove unneeded headerKyösti Mälkki
Change-Id: I9c65d3c54efcdec1ebb2648d078acdd9e7c11c49 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-25soc/intel/skylake/vr_config: Use lookup table by defaultPatrick Rudolph
If the board doesn't provide VRconfig in devicetree make sure to use the lookup table for IccMax instead of defaults for some mobile SoC. Also use decimal values instead of hex. Change-Id: If31063f9b483a3bbd6cc90df1c1b76b4efc66445 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37598 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20soc/intel/tigerlake: Update FSP stack and heap sizeMaulik V Vaghela
Tigerlake and Jasperlake fsp requires stack size to be minimum 192 KiB and heap size to be minimum 128 KiB. Updating both Kconfig to meet size requirements. Also updated required CAR region size during boot block due to increment in stack & heap requirement by fsp Change-Id: I38e93b5986811ff3e0a8df5f4f36af35f308cb6b Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37764 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20soc/mediatek/mt8183: Use DDR clock to compute Tx delay cellHuayang Duan
The delay cell result should use DDR clock PLL rate for computation, and should not be divided by 2. This helps to improve DRAM stability. BUG=b:80501386,b:142358843 BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-20AMD {SoC, AGESA, binaryPI}: Don't use both of _ADR and _HIDMichał Żygowski
PCI devices starting from 18 are processor configuration devices for each node and are not a bus itself. According to ACPI specification 6.3 section 6.1.5: "... _HID object must be used to describe any device that will be enumerated by OSPM. OSPM only enumerates a device when no bus enumerator can detect the device ID. ... Use the _ADR object to describe devices enumerated by bus enumerators other than OSPM." PCI device 18 with its functions has a standard enumerator, which is PCI enumerator so it needs a _ADR. Create a separate ACPI device for the processor configuration space. This fixes the ACPI compliance problem from CB:36318. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie7b45ce8d9e4fdd80d90752bf51bba4d30041507 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37835 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20{drivers,soc}/intel/fsp1_1: Move chipset specific logo handling to SoCWim Vervoorn
FSP logo handling used PcdLogoPtr and PcdLogoSize which are elements of the chipset specific FSP structures. Create soc_load_logo() which will pass the logo pointer and size. This function will call fsp_load_logo which will load the logo. BUG=NA TEST= Build and verified logo is displayed on Facebook FBG1701 Change-Id: I86943e64ca1ddd05e7e88fc6b882cfd33b98272e Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37791 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20src: Replace min/max() with MIN/MAX()Elyes HAOUAS
Change-Id: I63b95144f2022685c60a1bd6de5af3c1f059992e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37828 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20{nb,soc}: Replace min/max() with MIN/MAX()Elyes HAOUAS
Use MIN() and MAX() defined in commonlib/helpers.h Change-Id: I02d0a47937bc2d6ab2cd01995a2c6b6db245da15 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37454 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19soc/amd/picasso: Reduce romstage.cMarshall Dawson
Remove the old Stoney Ridge postcar stack frame setup. Reduce romstage.c to basic functionality. Until AGESA's reporting of memory configuration is available, use the TOM register as an indicator for the top of usable memory. Change-Id: I516b79c3e798f5fc68c2771b2f66034c6867b19e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19soc/amd/picasso: Remove unused Kconfig optionsMarshall Dawson
No AGESA v5 binaryPI features are still present in the picasso directory. Remove the PI and S3 selects. Remove DCACHE symbols. Remove all vboot options until the new PSP-based solution is developed. Change-Id: I6542578afafc0ee3c3117a971b1a021dbe53f42c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHEKyösti Mälkki
If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory. This also adds board reset for failing to load postcar from stage cache. Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-12-19{drivers,soc}/intel/fsp2_0: Move chipset specific logo handling to SoCWim Vervoorn
FSP logo handling used FspsConfig.LogoPtr and FspsConfig.LogoSize which are chipset specific. Create soc_load_logo() which will pass the logo pointer and size. This function will call fsp_load_logo which will load the logo. BUG=NA TEST= Build and verified logo is displayed on Facebook Monolith Change-Id: I30c7bdc0532ff8823e06f4136f210b542385d5ce Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37792 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19soc/intel/tigerlake: Add required header files in pch.cAamir Bohra
Add header files to fix build issues due to missing declaration for get_pch_series and die_with_post_code functions. Change-Id: Ie8ba4970ec1b73c1e481f54bcfbf95be87d9c442 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-12-19src: Remove unused 'include <arch/cpu.h>'Elyes HAOUAS
Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19src/soc/intel: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I71a5a6c3748d5a3910970bfb1ec3d7ecd3184cfd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33686 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19src/soc/samsung: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I6a933295de7c41d62e6a95f955c098b49ea17f08 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33689 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I83322e246fe81b97188be17a3fdda16d36df0678 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33688 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19src: Use '#include <smp/node.h>' when appropriateElyes HAOUAS
Change-Id: Icdd6b49751763ef0edd4c57e855cc1d042dc6d4d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19soc/qualcomm/sdm845: Remove unused 'include <timestamp.h>'Elyes HAOUAS
Change-Id: I9b91184ee1daf4dd40f17984ef2a30756e845906 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-12-19src/soc/qualcomm: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I0bb44636f9ce6a9f96f5909926b586d0a6cedd9e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37383 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-16 07:37:05 +0000