| Age | Commit message (Expand) | Author |
|---|
| 2016-02-04 | soc/intel/quark: Add minimal Quark SoC X1000 files | Lee Leahy |
| 2016-02-04 | soc/marvell/armada38x: Add i2c driver for armada38x | Ruilin Hao |
| 2016-02-04 | soc/marvell/armada38x: Add gpio driver for armada38x | Ruilin Hao |
| 2016-02-04 | soc/marvell/armada38x: Add spi driver for armada38x | Ruilin Hao |
| 2016-02-04 | soc/marvell/armada38x: Add generic support for armada38x | Ruilin Hao |
| 2016-02-02 | soc/intel/common: Use SoC specific routine to read/write MTRRs | Lee Leahy |
| 2016-02-02 | Kconfig: indent with tabs, not spaces. | Martin Roth |
| 2016-01-31 | drivers/intel/fsp1_1: Fix spelling error in API and copyright | Lee Leahy |
| 2016-01-30 | soc/intel: Add skeleton infrastructure for Apollolake SOC | Alexandru Gagniuc |
| 2016-01-29 | soc/braswell: Fix Global NVS base address | Hannah Williams |
| 2016-01-29 | src/: Chmod 644 all .c, .h, .asl, .inc, .cb, .hex, & Kconfig files | Martin Roth |
| 2016-01-29 | intel/skylake: Implement native Cache-as-RAM (CAR) | Subrata Banik |
| 2016-01-28 | soc/braswell: Add interface to program USB2_COMPBG register | shkim |
| 2016-01-28 | soc/braswell/acpi/DPTF: Write TCHG state on AC connect. | Jenny TC |
| 2016-01-28 | soc/braswell/acpi: Fix CID1 offset in comment | Hannah Williams |
| 2016-01-28 | soc/braswell: Fix issues found during static code analysis | Ravi Sarawadi |
| 2016-01-28 | Braswell: Separate L1 Sub State init procedure for boards. | Kenji Chen |
| 2016-01-28 | Strago: Enable CA Mirror | Shobhit Srivastava |
| 2016-01-28 | soc/braswell: Disable SD card detect simulation in FSP | Divya Sasidharan |
| 2016-01-28 | soc/braswell: Set max frequency to be turbo frequency | Hannah Williams |
| 2016-01-28 | soc/braswell: Fix DSP clock | fdurairx |
| 2016-01-28 | drivers/intel/fsp1_1: Remove extra include references | Lee Leahy |
| 2016-01-27 | soc/braswell: Fix leakage on V1P8S rail | Shobhit Srivastava |
| 2016-01-27 | soc/braswell: Add macro NATIVE_INT_PU20K | Hannah Williams |
| 2016-01-26 | Braswell: Implement Gpio library functions to read RAMID | Subrata Banik |
| 2016-01-22 | mediatek/mt8173: revise cbmem_top | CC Ma |
| 2016-01-22 | mediatek/mt8173: move rtc_boot() to romstage | Yidi Lin |
| 2016-01-22 | mediatek/mt8173: Add usb phy driver | Chunfeng Yun |
| 2016-01-22 | mediatek/mt8173: pll: Add API for enabling USB 3.0 phy reference clock | Chunfeng Yun |
| 2016-01-22 | mediatek/mt8173: configure audio | Koro Chen |
| 2016-01-22 | mediatek/mt8173: add APLL clock setting | Koro Chen |
| 2016-01-22 | mediatek/mt8173: Add mtcmos power-on control for audio and display | CC Ma |
| 2016-01-22 | mediatek/mt8173: Add RTC driver | Tianping Fang |
| 2016-01-22 | mediatek/mt8173: Add I2C driver | Liguo Zhang |
| 2016-01-22 | mediatek/mt8173: Add MMU support | Jimmy Huang |
| 2016-01-22 | mediatek/mt8173: Add gen-bl-img.py for mt8173 bootblock code | Yidi Lin |
| 2016-01-22 | mediatek/mt8173: Add support for verstage | Itamar |
| 2016-01-22 | mediatek/mt8173: add watchdog driver | Itamar |
| 2016-01-22 | mediatek/mt8173: Add SPI support | Leilk Liu |
| 2016-01-22 | soc/braswell: Add method for Wifi regulatory domain | Felix Durairaj |
| 2016-01-22 | intel/skylake: Fix klockwork violation | Naresh G Solanki |
| 2016-01-22 | intel/skylake: Thermal Design Power PL1 and PL2 Config Changes | pchandri |
| 2016-01-21 | intel/skylake: remove third paragraph of license header | Martin Roth |
| 2016-01-21 | broadwell: gpio.asl: Make GWAK method serialized | Duncan Laurie |
| 2016-01-19 | Braswell: add code to support customization of I2C data hold time | Kane Chen |
| 2016-01-19 | intel/skylake: Fix issues found by klockwork | Naresh G Solanki |
| 2016-01-19 | intel/skylake: Adding provision to set voltages to the I2C ports | Naresh G Solanki |
| 2016-01-19 | intel/skylake: Disable SaGv in recovery mode | haridhar |
| 2016-01-19 | soc/braswell: Remove the unneccessary functions from pcie.c | Shaunak Saha |
| 2016-01-19 | intel/skylake: Add support for IV feedback loop capture blob | Sathya Prakash M R |
| 2016-01-18 | intel/skylake: Change in UPD name from SkipMpInit to FspSkipMpInit | Barnali Sarkar |
| 2016-01-18 | intel/skylake: Remove unused devicetree configuration variables | Duncan Laurie |
| 2016-01-18 | intel/skylake: provide default VR configuration | Aaron Durbin |
| 2016-01-18 | intel/skylake: Add devicetree setting for DDR frequency limit UPD | Duncan Laurie |
| 2016-01-18 | intel/skylake: Add elog event for THERMTRIP | Duncan Laurie |
| 2016-01-18 | header files: Fix guard name comments to match guard names | Martin Roth |
| 2016-01-17 | intel/skylake: disable heci1 if psf is unlocked | Archana Patni |
| 2016-01-17 | intel/skylake: During RO mode after FSP reset CB lose original state | Subrata Banik |
| 2016-01-16 | intel/skylake: Fix uninitialized variable warning | Martin Roth |
| 2016-01-16 | intel/skylake: Add kconfig option to skip Native SD Controller | Subrata Banik |
| 2016-01-16 | intel/skylake: Add VrConfig UPD parameters from coreboot | Rizwan Qureshi |
| 2016-01-16 | intel/skylake: Enable SkipMpInit token | Rizwan Qureshi |
| 2016-01-15 | intel/skylake: Init variable so GCC knows it's set | Martin Roth |
| 2016-01-15 | intel/skylake: More UPD params are added for PCH policy in FSP | Rizwan Qureshi |
| 2016-01-15 | intel/skylake: Update UPD parameters as per FSP 1.8.0 | Barnali Sarkar |
| 2016-01-15 | intel/skylake: Add GPIO ACPI Apis. | Subrata Banik |
| 2016-01-15 | intel/skylake: add nhlt support | Aaron Durbin |
| 2016-01-14 | soc/braswell: Add CPUID for D0 stepping | Divya Sasidharan |
| 2016-01-14 | soc/braswell: Fix P-state table | Subrata Banik |
| 2016-01-14 | intel/skylake/pcr.c: error out on invalid size in pcr read/write | Martin Roth |
| 2016-01-13 | tree: drop last paragraph of GPL copyright header from new files | Martin Roth |
| 2016-01-12 | intel/skylake: Remove check for Microcode loaded by ME | Martin Roth |
| 2016-01-08 | fsp_baytrail: Add additional PCI space above 4GB | Martin Roth |
| 2016-01-07 | intel/braswell: Disable IFD & ME by default so abuild can build | Martin Roth |
| 2016-01-07 | Correct some common spelling mistakes | Martin Roth |
| 2016-01-06 | intel/braswell: Build in both C0 and 'other' vbios | Martin Roth |
| 2015-12-31 | imgtec/pistachio: disable default RPU gate register values | Ionela Voinescu |
| 2015-12-31 | imgtec/pistachio: memlayout: update GRAM size | Ionela Voinescu |
| 2015-12-31 | imgtec/pistachio: I2C: fix base address for I2C clock setup | Ionela Voinescu |
| 2015-12-31 | imgtec/pistachio: identity map SOC registers region | Ionela Voinescu |
| 2015-12-31 | imgtec/pistachio: Add SOC_REGISTERS memory region | Ionela Voinescu |
| 2015-12-31 | imgtec/pistachio: Use SYS PLL in integer mode | Ionela Voinescu |
| 2015-12-29 | mips: add coherency argument to identity mapping | Ionela Voinescu |
| 2015-12-27 | mainboard/google/urara: change SYS PLL to 700MHz | Ionela Voinescu |
| 2015-12-27 | soc/intel/broadwell: Add back support for EHCI debug setup | Duncan Laurie |
| 2015-12-27 | broadwell: Fix SATA Gen3 DTLE configuration registers | Duncan Laurie |
| 2015-12-27 | broadwell: Fix CONFIG_SPI_CONSOLE usage | Duncan Laurie |
| 2015-12-26 | ACPI: Add hack to avoid IASL warning when reading back registers | Martin Roth |
| 2015-12-22 | soc/intel/fsp_baytrail: Make sure i2c bus is < 7 | Martin Roth |
| 2015-12-21 | imgtec/pistachio: DDR2, DDR3: DLL reset set | Ionela Voinescu |
| 2015-12-21 | imgtec/pistachio: DDR2, DDR3: DQS gate early | Ionela Voinescu |
| 2015-12-21 | imgtec/pistachio: increase CBFS cache | Ionela Voinescu |
| 2015-12-20 | soc/intel/broadwell: Init var before use, only use when needed | Martin Roth |
| 2015-12-17 | Drop src/cpu/ indirection for MIPS | Stefan Reinauer |
| 2015-12-17 | soc/imgtec/pistachio: add implementation for system reset | Ionela Voinescu |
| 2015-12-17 | soc/imgtec/pistachio: Implement hard_reset() | Stefan Reinauer |
| 2015-12-17 | soc/intel/fsp_baytrail: Adjust root port INT routing | Martin Roth |
| 2015-12-16 | intel/fsp_baytrail: change indent to use tabs | Ben Gardner |
| 2015-12-16 | intel/fsp_baytrail: rename include folder baytrail to include/soc | Ben Gardner |
| 2015-12-16 | intel/fsp_baytrail: Fix PCI_DEV_PIRQ_ROUTE macro ending | Ben Gardner |
