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path: root/src/soc
AgeCommit message (Expand)Author
2016-02-09nhlt: add api to override oem_id and oem_table_id of acpi_header_tFang, Yang A
2016-02-09chromeos: Remove CONFIG_VBNV_SIZE variableDuncan Laurie
2016-02-08soc/intel/quark: Add TempRamInit supportLee Leahy
2016-02-08soc/intel/quark: Enable ESRAMLee Leahy
2016-02-04intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdownArchana Patni
2016-02-04intel/skylake: unconditionally set SPI controller BARAaron Durbin
2016-02-04intel/skylake: implement vboot_platform_prepare_reboot()Aaron Durbin
2016-02-04intel/skylake: implement vboot_platform_is_resuming()Aaron Durbin
2016-02-04intel/skylake: Display ME firmware status before os bootDhaval Sharma
2016-02-04soc/intel/quark: Add minimal Quark SoC X1000 filesLee Leahy
2016-02-04soc/marvell/armada38x: Add i2c driver for armada38xRuilin Hao
2016-02-04soc/marvell/armada38x: Add gpio driver for armada38xRuilin Hao
2016-02-04soc/marvell/armada38x: Add spi driver for armada38xRuilin Hao
2016-02-04soc/marvell/armada38x: Add generic support for armada38xRuilin Hao
2016-02-02soc/intel/common: Use SoC specific routine to read/write MTRRsLee Leahy
2016-02-02Kconfig: indent with tabs, not spaces.Martin Roth
2016-01-31drivers/intel/fsp1_1: Fix spelling error in API and copyrightLee Leahy
2016-01-30soc/intel: Add skeleton infrastructure for Apollolake SOCAlexandru Gagniuc
2016-01-29soc/braswell: Fix Global NVS base addressHannah Williams
2016-01-29src/: Chmod 644 all .c, .h, .asl, .inc, .cb, .hex, & Kconfig filesMartin Roth
2016-01-29intel/skylake: Implement native Cache-as-RAM (CAR)Subrata Banik
2016-01-28soc/braswell: Add interface to program USB2_COMPBG registershkim
2016-01-28soc/braswell/acpi/DPTF: Write TCHG state on AC connect.Jenny TC
2016-01-28soc/braswell/acpi: Fix CID1 offset in commentHannah Williams
2016-01-28soc/braswell: Fix issues found during static code analysisRavi Sarawadi
2016-01-28Braswell: Separate L1 Sub State init procedure for boards.Kenji Chen
2016-01-28Strago: Enable CA MirrorShobhit Srivastava
2016-01-28soc/braswell: Disable SD card detect simulation in FSPDivya Sasidharan
2016-01-28soc/braswell: Set max frequency to be turbo frequencyHannah Williams
2016-01-28soc/braswell: Fix DSP clockfdurairx
2016-01-28drivers/intel/fsp1_1: Remove extra include referencesLee Leahy
2016-01-27soc/braswell: Fix leakage on V1P8S railShobhit Srivastava
2016-01-27soc/braswell: Add macro NATIVE_INT_PU20KHannah Williams
2016-01-26Braswell: Implement Gpio library functions to read RAMIDSubrata Banik
2016-01-22mediatek/mt8173: revise cbmem_topCC Ma
2016-01-22mediatek/mt8173: move rtc_boot() to romstageYidi Lin
2016-01-22mediatek/mt8173: Add usb phy driverChunfeng Yun
2016-01-22mediatek/mt8173: pll: Add API for enabling USB 3.0 phy reference clockChunfeng Yun
2016-01-22mediatek/mt8173: configure audioKoro Chen
2016-01-22mediatek/mt8173: add APLL clock settingKoro Chen
2016-01-22mediatek/mt8173: Add mtcmos power-on control for audio and displayCC Ma
2016-01-22mediatek/mt8173: Add RTC driverTianping Fang
2016-01-22mediatek/mt8173: Add I2C driverLiguo Zhang
2016-01-22mediatek/mt8173: Add MMU supportJimmy Huang
2016-01-22mediatek/mt8173: Add gen-bl-img.py for mt8173 bootblock codeYidi Lin
2016-01-22mediatek/mt8173: Add support for verstageItamar
2016-01-22mediatek/mt8173: add watchdog driverItamar
2016-01-22mediatek/mt8173: Add SPI supportLeilk Liu
2016-01-22soc/braswell: Add method for Wifi regulatory domainFelix Durairaj
2016-01-22intel/skylake: Fix klockwork violationNaresh G Solanki
2016-01-22intel/skylake: Thermal Design Power PL1 and PL2 Config Changespchandri
2016-01-21intel/skylake: remove third paragraph of license headerMartin Roth
2016-01-21broadwell: gpio.asl: Make GWAK method serializedDuncan Laurie
2016-01-19Braswell: add code to support customization of I2C data hold timeKane Chen
2016-01-19intel/skylake: Fix issues found by klockworkNaresh G Solanki
2016-01-19intel/skylake: Adding provision to set voltages to the I2C portsNaresh G Solanki
2016-01-19intel/skylake: Disable SaGv in recovery modeharidhar
2016-01-19soc/braswell: Remove the unneccessary functions from pcie.cShaunak Saha
2016-01-19intel/skylake: Add support for IV feedback loop capture blobSathya Prakash M R
2016-01-18intel/skylake: Change in UPD name from SkipMpInit to FspSkipMpInitBarnali Sarkar
2016-01-18intel/skylake: Remove unused devicetree configuration variablesDuncan Laurie
2016-01-18intel/skylake: provide default VR configurationAaron Durbin
2016-01-18intel/skylake: Add devicetree setting for DDR frequency limit UPDDuncan Laurie
2016-01-18intel/skylake: Add elog event for THERMTRIPDuncan Laurie
2016-01-18header files: Fix guard name comments to match guard namesMartin Roth
2016-01-17intel/skylake: disable heci1 if psf is unlockedArchana Patni
2016-01-17intel/skylake: During RO mode after FSP reset CB lose original stateSubrata Banik
2016-01-16intel/skylake: Fix uninitialized variable warningMartin Roth
2016-01-16intel/skylake: Add kconfig option to skip Native SD ControllerSubrata Banik
2016-01-16intel/skylake: Add VrConfig UPD parameters from corebootRizwan Qureshi
2016-01-16intel/skylake: Enable SkipMpInit tokenRizwan Qureshi
2016-01-15intel/skylake: Init variable so GCC knows it's setMartin Roth
2016-01-15intel/skylake: More UPD params are added for PCH policy in FSPRizwan Qureshi
2016-01-15intel/skylake: Update UPD parameters as per FSP 1.8.0Barnali Sarkar
2016-01-15intel/skylake: Add GPIO ACPI Apis.Subrata Banik
2016-01-15intel/skylake: add nhlt supportAaron Durbin
2016-01-14soc/braswell: Add CPUID for D0 steppingDivya Sasidharan
2016-01-14soc/braswell: Fix P-state tableSubrata Banik
2016-01-14intel/skylake/pcr.c: error out on invalid size in pcr read/writeMartin Roth
2016-01-13tree: drop last paragraph of GPL copyright header from new filesMartin Roth
2016-01-12intel/skylake: Remove check for Microcode loaded by MEMartin Roth
2016-01-08fsp_baytrail: Add additional PCI space above 4GBMartin Roth
2016-01-07intel/braswell: Disable IFD & ME by default so abuild can buildMartin Roth
2016-01-07Correct some common spelling mistakesMartin Roth
2016-01-06intel/braswell: Build in both C0 and 'other' vbiosMartin Roth
2015-12-31imgtec/pistachio: disable default RPU gate register valuesIonela Voinescu
2015-12-31imgtec/pistachio: memlayout: update GRAM sizeIonela Voinescu
2015-12-31imgtec/pistachio: I2C: fix base address for I2C clock setupIonela Voinescu
2015-12-31imgtec/pistachio: identity map SOC registers regionIonela Voinescu
2015-12-31imgtec/pistachio: Add SOC_REGISTERS memory regionIonela Voinescu
2015-12-31imgtec/pistachio: Use SYS PLL in integer modeIonela Voinescu
2015-12-29mips: add coherency argument to identity mappingIonela Voinescu
2015-12-27mainboard/google/urara: change SYS PLL to 700MHzIonela Voinescu
2015-12-27soc/intel/broadwell: Add back support for EHCI debug setupDuncan Laurie
2015-12-27broadwell: Fix SATA Gen3 DTLE configuration registersDuncan Laurie
2015-12-27broadwell: Fix CONFIG_SPI_CONSOLE usageDuncan Laurie
2015-12-26ACPI: Add hack to avoid IASL warning when reading back registersMartin Roth
2015-12-22soc/intel/fsp_baytrail: Make sure i2c bus is < 7Martin Roth
2015-12-21imgtec/pistachio: DDR2, DDR3: DLL reset setIonela Voinescu
2015-12-21imgtec/pistachio: DDR2, DDR3: DQS gate earlyIonela Voinescu