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The SMU mailbox interface gets accessed over the SMN register space, so
factor out those access functions into a separate common code SMN access
building block.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iabac181972c02ae641da99f47b2aa9aa28dae333
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Even though the implementation is different on Stoneyridge compared to
Picasso and Cezanne, the function prototypes are identical, so move them
to the AMD SoC common reset header file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Convert the lines starts with whitespace with tab as applicable.
TEST=Built google/brya0 and ADLRVP with BUILD_TIMELESS=1: no changes.
Change-Id: Ibd11ad12caa1be866a851a8cd4bd23349e8ffbbe
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51375
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to Intel EmmitsBurg EDS, doc# 606161:
* Add PCI devid for SPI.
* Add PCI devid for ESPI (LPC).
EmmitsBurg (EBG) PCH is used in the chipset with Sapphire Rapids
Scalable Processor (SPR-SP).
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ie8925cb739c95c34febf9002149de437d19c8234
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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BUG=b:180529005
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I16de0869abd1eff4e89cf1b8128775858702acb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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PSP_SHAREDMEM_BASE made the assumption that _psp_sharedmem_dram would
only match once. With CB:49332 there are now two symbols, and it was
grabbing the wrong one.
This change makes it so we match the exact symbol. It also switches to
using awk to simplify the code.
The bootblock.elf target that is added to the list of prerequisites also
creates the bootblock.map file that gets used to extract the base
address of the _psp_sharedmem_dram symbol.
BUG=b:181354692
TEST=Boot zork past bootblock
Fixes: 82d16b150ce3 ("memlayout: Store region sizes as separate symbols")
Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I79675bd73f964282b54bca858830e26de64037c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Some of the previous binaries were incorrect and should not be used
for Majolica because they are templates instead of APCBs specifically
built for the board. This APCB update also places the UMA region under
4G and size 32 MB which is essential for video output.
TEST=Boot with UEFI BIOS and verify we can get to OS. Also verify memory
region size, base and alignment.
Change-Id: Id797e2ad5bd67815c09752aedc19dad7dcf8ad12
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Even though AMD does not need VBT we still need to implement the
vbt_get() function to not break the build with GOP driver enabled
(see fsps_return_value_handler() in fsp2_0/silicon_init.c
BUG=b:171234996
BRANCH=Zork
Change-Id: I80a5131a9852a05998b55b847243748d24cf535f
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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BUG=b:182269526
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ib33a46a6eead84eaff2c4ac320800b7993f5c3f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add the UPD updating hook in early stage for customization.
BUG=b:117719313
BRANCH=zork
TEST=build,check the hook function been executed.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4954a438a51b29b086015624127e651fd06f971b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51181
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:181766974
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I660f19d18810c35dafcd75bcd1993216b7b09644
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51268
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib317493fe938fe961aed06557e655ed8498e2694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I388cdb1fb9b3decaa6eb6e0e4e538c620d3048a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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When the SCI_EN bit is set, PM1 and GPE0 events will trigger a SCI
instead of a SMI#. However, SMI_STS bits PM1_STS and GPE0_STS can
still be set. Therefore, when SCI_EN is set, ignore PM1 and GPE0
events in the SMI# handler, as these events have triggered a SCI.
Do not ignore any other SMI# types, since they cannot cause a SCI.
Note that these bits are reserved on APL and GLK. However, SoC-specific
code already accounts for it. Thus, no special handling is needed here.
Change-Id: I5998b6bd61d796101786b57f9094cdaf0c3dfbaa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove unused boot status settings.
Reset the power-off sequence to zero to meet hardware requirement.
BUG=b:179000151
BRANCH=none
TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: Ie9d39be532ec378bd6df6bf1b93307dae4068fc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51246
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We saw EXT_PMIC_EN1 and PPVAR_DVDD_PROC_BC power off sequence
failure, and after checking MT6315 MT6315 PMIC protection key
summary.xlsx and MT6315 Top and CLK programming guide.docx,
we found there are something wrong about the sequence of magic
key protection flow and clk setting. Update correct initial
flow.
BUG=b:179000151
BRANCH=none
TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I1b7f970a44904fda09a97f4064eef7c95feefad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51245
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The initial settings for MT6315 were not applied correctly
because the setup process didn't specify correct slave id
(incorrectly always sending 0), and may cause failure in
power off sequence.
BUG=b:179000151
BRANCH=none
TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: Ifd04da8ac55bcc9f9fdbc088d430522c2725ad47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I674cff3352cd9f5d20b3d8f7e77339d045cadbb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51357
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6bad684bc6a36bb4a2b83d10ff9da1c136f8bbd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51356
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If4f75eadca101593cf37faf2722f4ea8f509a1f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51355
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This also replaces the southbridge_ prefix of the handler functions with
a handle_ prefix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib6ea1f4e2700c508a8bf72c488043e276ba4a062
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51354
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:181766974
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I99d5984da82cfc98a106fc5c27e32fdc3cc13b3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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TEST=Timeless build of amd/mandolin results in identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Raul Rangel <rrangel@chromium.org>
Change-Id: Ie0e69532b7d13df87e2d9333ed34dbb008d2cc84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Prevent writes to Global SMI enable as recommended by the BWG.
Change-Id: I7824464e53a2ca1e860c1aa40d8a7d26e948c418
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add SOC_INTEL_COMMON_PCH_LOCKDOWN and PMC_GLOBAL_RESET_ENABLE_LOCK
to meet device security requirements.
LOCKDOWN has dependencies on SOC_INTEL_COMMON_PCH_BASE and
several other common block devices. Add COMMON_PCH_BASE and
COMMON_PCH_SERVER to pick up LOCKDOWN and the dependencies.
COMMON_PCH_SERVER adds the following common devices that were not
previously included by XEON_SP:
SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
SOC_INTEL_COMMON_BLOCK_CSE
SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
SOC_INTEL_COMMON_BLOCK_ITSS
SOC_INTEL_COMMON_PCH_LOCKDOWN
SOC_INTEL_COMMON_BLOCK_SATA
SOC_INTEL_COMMON_BLOCK_SMBUS
SOC_INTEL_COMMON_BLOCK_XHCI
Change-Id: Iab97123e487f4f13f874f364a9c51723d234d4f0
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add a server Kconfig option to select a subset of common PCH devices.
Client devices are included if server isn't selected. This maintains
the current Kconfig behavior.
Change-Id: If11d1a51192dd87ad770b8aa53ce02b6a28b8da8
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This file is common for all the AMD platforms.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I10ee600b4bcd7aaff39bfab075eb4dbc9096b435
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51299
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch pulls control of the memory pool serving allocations from the
CBFS_CACHE memlayout area into cbfs.c and makes it a core part of the
CBFS API. Previously, platforms would independently instantiate this as
part of boot_device_ro() (mostly through cbfs_spi.c). The new cbfs_cache
pool is exported as a global so these platforms can still use it to
directly back rdev_mmap() on their boot device, but the cbfs_cache can
now also use it to directly make allocations itself. This is used to
allow transparent decompression support in cbfs_map().
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I0d52b6a8f582a81a19fd0fd663bb89eab55a49d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Mainboards can configure gpios in their smihandler.
BUG=b:180507707
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I6c2b28f981f580cfb6f982a2d7e4c309d6f82e0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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BUG=b:180507937
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ic29fa569899e7b77819ce7f72c6a748621684c40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change will allow for GEVENTs to be used in ASL code.
BUG=b:180507937
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I77abd134555c21a32a302ee92cd080284cd2e634
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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GOP needs to register the new framebuffer.
BUG=b:171234996
BRANCH=Zork
Change-Id: I17b6533520b0628df9529d09f70d5fc28339d522
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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If bit 0 of byte 0x47 is set FSP will perform full memory training
even if previously saved data is supplied.
Up to and including FSP 2021 WW01 it was reset internally at the end
of PostMemoryInit. Starting with WW03 this is no longer the case and
Intel advised that this bit should be reset externally if valid MRC
data is present.
Change-Id: I9c4191d2fa2e0203b3464dcf40d845ede5f14c6b
Signed-off-by: Deomid "rojer" Ryabkov <rojer9@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The default value for the LidStatus is "LidClosed" mean 0
Because of this GOP skips graphics initialization assuming
lid is closed even though lid is open. This Patch is to set
LidStatus UPD to 1 whenever RUN_FSP_GOP config is selected.
BUG=b:178461282
BRANCH=None
TEST=Build and boot ADLRVP and verify eDP is coming up in
depthcharge
Change-Id: I1648ae0f06e414b2a686e325acf803deb702b7a5
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Move PRERAM_CBMEM_CONSOLE to SRAM L2C and increase its size from 15K to
400K. With this change, most part of the DRAM full calibration log can
be stored in CBMEM console.
BUG=b:181933863
TEST=emerge-asurada coreboot
TEST=Hayato boots
BRANCH=none
Change-Id: I896884d298e197149f75865e9d00579124a34404
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Many header files and helper macros have been moved to the
common folder and we want to use them in mt8173/mt8183
DRAM calibration code.
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: Ifa483dcfffe0e1383cb46811563c90f0ab484d5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51224
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Mediatek has released the reference implementation for DRAM
initialization in vendorcode/mediatek/mt8192/dramc (CB:50294)
so we want to use it to replace the derived calibration code
in soc folder.
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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To reduce duplicated dram sources on seperate SOCs,
add dpm, dram_init, dramc_params, memory(fast-k or full-k)
implementations, also add dramc log level macro header files.
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I557c96b3d09828472b8b6f932b0192a90894043e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Also rename mrc_cache to apob_cache.
BUG=b:181766974
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4877b05443452c7409006c1656e9d574e93150a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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BUG=b:181843816
Change-Id: I25309a8f0900070a8307fbce90ccb6d47f9c3dfc
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51261
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TCSS muxes being left uninitialized during boot is causing some USB3
devices to downgrade to USB2 speed. To properly configure the Type C ports
the muxes should be set to disconnected state during boot so that the port
mapping of USB2/3 devices is properly setup prior to Kernel initializing
devices.
BUG=b:180426950
BRANCH=firmware-volteer-13672.B
TEST= Connected USB3 storage device and rebooted the system multiple
times to verify that devices were no longer downgrading to USB2 speed.
Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Done to ease diffing against Lynxpoint.
Change-Id: Ib4280b26799eab6d4a2bb41a14a76695caa31e86
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Continue unifying Lynx Point and Wildcat Point (PCH for Broadwell) code.
Define the WPT-LP SMBus PCI device ID, add it to smbus.c of Lynx Point,
and drop all now-unnecessary SMBus code from Broadwell.
Change-Id: I864d7c2dd47895a3c559e2f1219425cda9fd0c17
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The datasheet indicates that this bit is reserved. However, subsequent
patches need to use this macro in common code, or else builds fail. To
iron out this difference, mask out the bit in `soc_get_smi_status`, so
that common code always sees it as zero. Finally, add an entry for the
bit in `smi_sts_bits` for debugging usage, noting that it is reserved.
Change-Id: Ib4408e016ba29cf8f7b125c95bfa668136b9eb93
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Convert the lines starts with whitespace with tab as applicable.
Change-Id: Ife7b27360661cbfd2c90e2b643ed31225ded228c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51250
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The original implementation of early tcss resulted in calling to mainboard
then back to soc then back to mainboard to properly configure the muxes.
This patch addresses that issue and instead just gets all the mux
information from mainboard and does all config in the soc code.
BUG=none
BRANCH=firmware-volteer-13672.B
TEST=Verified functionality is not effected and early TCSS still functions
Change-Id: Idd50b0ffe1d56dffc3698e07c6e4bc4540d45e73
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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`pmc_send_ipc_cmd()` expects the caller to pass in a pointer to a valid
request and response buffer. However, early_tcss driver was passing in
a NULL pointer for response buffer which would result in invalid
access by `pmc_send_ipc_cmd()`.
Currently, the response buffer is not used in `update_tcss_mux()`. So,
this change drops the passing of `rbuf` parameter to `send_pmc*`
helpers and instead uses a local `rsp` variable in the respective
functions. All the PMC functions used in early_tcss driver return some
kind of response. These should be checked to return appropriate
response code back to the caller. However, this needs to be done as a
separate change.
Change-Id: I215af85feed60b6beee17f28e3d65daa9ad4ae69
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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With the aliases some of the comments are redundant. I'm still not sure
if the Ethernet controller on the embedded SKUs supports 10G or only 1G.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1e432c12f92a622f8ee05be19acb2c304dd74afb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Since the support for the GSMI ELOG isn't implemented in the SMI handler
yet, the corresponding code isn't added to fch_slp_typ_handler in this
patch.
BUG=b:181766974
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia27b2486dde1a373607ce895a975e873d9026ba1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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BUG=b:181766974
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5b9b4c3d57945ea7c3287cf47f3d9704f42ff24b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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When printing error information during DRAM training, be more verbose
by printing the channel number.
Change-Id: If4109bd0573e3d9f90d699d89350ddbcc48714d3
Signed-off-by: Moritz Fischer <moritzf@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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There is no need for explicit 0 comparison, any return value not equal
to 0 is treated as error.
Change-Id: I72612af4108a616b6247ee68c8ac2a53242b0853
Signed-off-by: Moritz Fischer <moritzf@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Renoir/Cezanne have two SATA controllers with 2 ports each, so call them
sata_0 and sata_1.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ebfd3a85f9b513901f205bc299e92564fa329e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51190
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add memory part MT53E2G32D4NQ-046 to LP4x global list. Attributes
are derived from data sheets.Also, regenerate the SPD files for ADL
SoC using the newly added parts.
BUG=b:181378727
TEST=Compared generated SPD with data sheets and checked in SPD
Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: Iafa7d40fc21e62f99dbdc2001ab6525a2a77ff50
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44865
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Guard against unintended operator precedence and associativity issues.
Change-Id: I342682a57fde9942cdf7be10756ee21c10af802a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50917
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To allow unifying bootblock.c in follow-ups, move a function call.
Change-Id: I0f40ee7fd47f7f9f582f314dfcd1b4b93b1db791
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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There are seven identical copies of the same file. One is enough.
Change-Id: I68c023029ec45ecfaab0e756fce774674bb02871
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50937
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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State of ME firmware SKU is independent of power-down mitigation.
Change-Id: I014c1697213efaefcb0c2a193128a876ef905903
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Use LZ4 algorithm to compress FSP-S. This saves ~40 KiB and reduces the
boot time by ~7 ms. LZMA would save a further ~1 KiB, but adds ~9 ms to
the boot time.
LZMA size:
fsps_lzma.bin 0xb0dc0 fsp 146578 LZMA (188416 decompressed)
LZMA decompression time:
15:starting LZMA decompress (ignore for x86) 388,716 (47,646)
16:finished LZMA decompress (ignore for x86) 406,167 (17,450)
LZ4 size:
fsps_lz4.bin 0x242dc0 fsp 147442 LZ4 (188416 decompressed)
LZ4 decompression time:
17:starting LZ4 decompress (ignore for x86) 384,736 (47,864)
18:finished LZ4 decompress (ignore for x86) 384,796 (59)
Change-Id: Idace01227cfd2312b2c4c4ea1e6aaac8c21cd6b0
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add wake events to the elog for: HDA, GbE, SATA, CSE, south XHCI,
south XDCI, CNVi WiFI, TCSS XHCI, TCSS XDCI, and TCSS DMA ports.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icd50dc7ee052cf13b703188c0fd3d8b99216cb4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Change-Id: I5cf54ae0456147c88b64bd331d4de5ca2e941f8a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47413
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Log PCIe root port wake events in the elog.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I2867b1fa12f639cd6c49a58f698b51b089e2b483
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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TEL_CFG_BAR variables have the same value as PCI_BASE_ADDRESS.
This fix re-uses an already existing variable in crashLog.
BUG=None
TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: If063d1ea4189dbc5a75f37d86ce158e8f1bd808d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The `FORCE_ENABLE` and `FORCE_DISABLE` names do not match what FSP UPDs
say, and can be confused with the `PchHdaTestPowerClockGating` UPD.
Replace the enum with a bool, and drop the confusing names. Note that
the enum for Ice Lake was incorrect, but no mainboards used the option.
Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51154
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Backport commit 0cded1f116 (soc/intel/tigerlake: Add SMRR Locking
support) to other client platforms. The SMRR MSRs are core-scoped on
Skylake and Ice Lake, at least. Older platforms do not support SMRR
locking, but now there's seven copies of the same file in the tree. A
follow-up will deduplicate smmrelocate.c files into common CPU code.
I cannot test Jasper Lake nor Elkhart Lake, but they should still work.
As per documentation I do not have access to, Elkhart Lake seems to
support SMRR locking. However, Jasper Lake documentation is unclear.
Tested on Purism Librem Mini v1 (WHL-U i7-8565U), still boots and SMRR
MSRs have the same value on all cores/threads (i7-8565U supports HT).
Change-Id: Icbee0985b04418e83cbf41b81f00934f5a663e30
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The legacy DMA is not used by linux. This change frees up those IO
ports.
When FSP-S runs, it re-enables the legacy DMA IO region, so we need to
disable it again.
BOOTBLOCK: PMx00: 0xe3060bf3
ROMSTAGE - Before FSP: PMx00: 0xe3060bf3
ROMSTAGE - After FSP: PMx00: 0xe3060bf7
BUG=b:180949454
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7792d1f8ea40eb1c7f6cca67e9907208884ac694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51076
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:180528708
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Iecc75afd7a914651ca15b811163d3559bf73ac9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The serirq enable bit defaults to true, so if we want it disabled, we
need to explicitly disable it.
BUG=b:180631748
TEST=Boot majolica and see spurious IRQ 9 gone.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7f1e18f836f29cb75334dd88c91ad047f5bdfb10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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For consistency with newer platforms, do this in pch.c instead.
Change-Id: Ie7a1d3e106553388df55044be91c7837061c42da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Just call `fast_spi_cache_bios_region()` directly instead.
Change-Id: I99f6ed4cf1a5c49b078cfd05e357c2d4c26ade45
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50952
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The MRC cache driver assumes BOOT_DEVICE_MEMORY_MAPPED=y already. This
is to ease factoring out common code across seven Intel platforms.
Change-Id: I0598cb18b456e10789b2a42792fbfa2639cdd2c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50951
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I8f48765ad99dad49f9d94c45aa4af6aff2ed702c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50950
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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RAM is not yet configured in bootblock. This function was copy-pasted
from Broadwell. Also, Skylake no longer uses FSP 1.1 and the stubs in
there can be removed as nothing else uses them.
Change-Id: I22cb7e63ed1e9565934296fd40771130ba91d227
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50949
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Done for consistency with newer platforms. Also clean up includes.
Change-Id: Ib78717c6fbd49a5bd79bd564add8849ad21fa9e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50948
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It only calls `smbus_common_init()`, so just call that directly.
Change-Id: I0237f52bb9b0503e83f5dbf31c4064bd0f5bae28
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50947
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Backport commit 03ed5bff5c (soc/intel/cannonlake: Move tco_configure to
bootblock), commit bb50c67227 (soc/intel/tigerlake: Move tco_configure
to bootblock) and commit 60c619f6a3 (soc/intel/jasperlake: Move
tco_configure to bootblock) to other platforms. This is for consistency.
Change-Id: I31fd0ceb67eacf30aefa457d757bf0d7f4cd7e87
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50946
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There's two instances of the same function, one for the bootblock and
another for romstage. Prefix them with the stage they are executed in.
Change-Id: I35e87cd47f3cef8952481d25b54558a546aebb60
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50944
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I1b08b31876d6c10ac155fd67d4a505e8c272a15c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50943
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I31bb406bd2cf371ee935aa31777307043b2ee61a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50942
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to document 332691-003EN (SPT-H datasheet volume 2), the
hardware defaults to 0x44, which matches what newer platforms use.
Change-Id: I494587b0074ab3675c3e88676375f667e757cdf0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50941
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The definitions are identical across seven platforms. Unify them.
Change-Id: I32bbd0777f8ca9d0362d210b43e0ba8dd0c8d79b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50940
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Done for consistency with newer platforms.
Change-Id: I1250c4514e1512e748bfc65c3f9f9da4ff1ef78e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50939
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I27f198d403f6ba05ba72ae0652da224d4cbf323a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50938
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is to align with newer platforms.
Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I92c9c06c606215a4bd9b44b3b4b1f0acced8a252
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50962
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The iGPU is on the northbridge or system agent, not the southbridge.
Change-Id: Ic63a7ad532fd1faa8e90d44bf7269040fa901757
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe3136682d2a9d248d5c6f26957e69013e4847ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Idc96b99da9f9037267c0bec2c839014b13ceb8cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51106
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This function returns true if any GPIO pad is programmed to route the
given IRQ to the IO-APIC. It does so by keeping track of which pads are
routed to IOxAPIC and looking this up in the new function.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iceda89cb111caa15056c204b143b4a17d59e523e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Both files are equivalent. Drop Broadwell's ctdp.asl and use Haswell's.
Change-Id: Ida17d030d6022af18078321ee76b425095fe9f5c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Fill the ECC type in `struct memory_info` in romstage, and in SoC code.
The SMBIOS override is unnecessary, and this is not mainboard-specific.
Change-Id: I8370b3ee7d75914b895946b53923598adf87b522
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50179
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are platforms that support error correction types other than
single-bit ECC. Extend meminfo to accomodate additional ECC types.
It is assumed that `struct memory_info` is packed to save space. Thus,
use `uint8_t` instead of an enum type (which are usually 4 bytes wide).
Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50178
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a method to disable decoding the legacy DMA IO ports.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I979445cfa8317334e62e9ebf12256ece9f8058bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51075
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, this function is only invoked for the SPI device through
common SoC code. Since both Intel Harcuvar and Scaleway Tagada have
enabled the SPI device in the devicetree, there's no need to use the
debug version of `pcidev_path_on_root`.
Change-Id: I4340d5860d23c2fa230105f7a7d345c367b2b2aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50128
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Suresh Bellampalli <suresh.bellampalli@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With this change NMI works in the kernel:
----------------
| NMI testsuite:
--------------------
remote IPI: ok |
local IPI: ok |
--------------------
Good, all 2 testcases passed! |
---------------------------------
See setup_lapic() for where this gets configured.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia391ec5a015d909462ff8aaf3cb047c6fd45fe0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
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This function should be using the RK_CLRSETBITS() macros to access the
special Rockchip write-mask registers, like the rest of our code. Also,
there were already existing bit field definitions for these bits that
should be used (although it makes sense to adjust them a bit to allow
passing in the channel number).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If1f5c06aabb16045d890df3bbd271f08a2cdf390
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51080
Reviewed-by: Moritz Fischer <moritzf@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This has been tested on the OCP Delta Lake platform.
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
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CB:50863 refactored the data_training() function to split out read gate
training into a separate function, but in the course of this forgot to
correctly initialize the local obs_err varible in the new function to 0.
This means that it will be used uninitialized, and when it happens to be
non-zero it makes the training process fail. Due to the convoluted
control flow in the function, it seems that GCC's static analyzer
couldn't pick up on this uninitialized use.
The whole variable is unnecessary anyway, all it's used for is to force
the function to return two lines below without doing anything with
side-effects in between. This patch removes the variable and simplifies
the code in all three training functions to avoid this uninitialized use
issue and make everything a bit more readable. (Also restore the
original pre-clang-format continuation line intendations for more
readability.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia475d64c06f2ec1bf9295742d173ce66717b821c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51079
Reviewed-by: Moritz Fischer <moritzf@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This causes the linux kernel to complain:
32/64X address mismatch in FADT/Pm1aEventBlock: 0x00000400/0x00000000FED80800
32/64X address mismatch in FADT/Pm1aControlBlock: 0x00000404/0x00000000FED80804
32/64X address mismatch in FADT/PmTimerBlock: 0x00000408/0x00000000FED80808
32/64X address mismatch in FADT/Gpe0Block: 0x00000420/0x00000000FED80814
The linux kernel also verifies that the PM Timer block only uses IO
ports.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I612b6bfb67d8559127ab2ee8a2fb828493820e31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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