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2022-11-10/: Remove "ERROR: "/"WARNING: " prefixes from log messagesElyes Haouas
It is no longer necessary to explicitly add "ERROR: "/"WARNING: " in front of every BIOS_ERR/BIOS_WARN message. Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-10sb,soc/intel: Use register_new_ioapic_gsi0()Kyösti Mälkki
Change-Id: I6b0e4021595fb160ae3bf798468f4505b460266f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10sb,soc/intel: Use acpi_create_madt_ioapic_from_hw()Kyösti Mälkki
Change-Id: I9fd9cf230ce21674d1c24b40f310e5558e65be25 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10soc/intel/xeon_sp: Move SMBIOS type 4 override functions from mainboardJingleHsuWiwynn
to soc Move SMBIOS type 4 override functions from mainboard to soc so that all xeon family cpus share same functions without implementing again. Tested=On OCP Deltalake, dmidecode -t 4 shows expected info. Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com> Change-Id: I17df8de67bc2f5e89ea04da36efb2480a7e73174 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-10soc/nvidia/tegra124: Fix building with clangArthur Heymans
This kind of allocation without '=' is not working with clang. Change-Id: I2d3e9eb44c3e0e25e5a67c5386e5ddde1487cc74 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63063 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10soc/sifive/ux00ddr.h: Remove set but unused variablesArthur Heymans
It looks like this code was not finished so it's left commented out for now. Change-Id: I442a42e297f2968dd2c824a93a9a1e2bc74ea2f4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63074 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09device/xhci: Factor out `struct xhci_usb_info`Robert Zieba
This commit factors out `struct xhci_usb_info` from intel specific code as it will be useful on other platforms. BUG=b:186792595 TEST=Builds for volteer Change-Id: I5b4cc6268f072c6948f11c7498a564d7a5c0a190 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-09device/xhci: Factor out common PORTSC codeRobert Zieba
This commit factors out some code for XHCI port status values. BUG=b:186792595 TEST=Built coreboot for volteer device Change-Id: I045405ed224aa8f48f6f628b7d49ec6bafb450d7 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-09soc/amd/picasso/acpi: include pci_int_defs.asl from soc.aslFelix Held
Instead of including pci_int_defs.asl in each board's DSDT, include it in the common soc.asl. This moves the PRQM OperationRegion and the PRQI IndexField defined in pci_int_defs.asl into the \_SB scope, but those are defined inside the \_SB scope both in the Picasso reference code and for the AMD SoCs from Cezanne on. TEST=Both Linux and Windows still boot and don't show ACPI errors on Mandolin after moving this inside the \_SB scope Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-11-09soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.aslFelix Held
This aligns Picasso more with the newer AMD SoCs and also makes it a bit clearer what this file does. Also remove the unneeded tabs at the beginning of each line. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-11-09soc/intel/common/xhci: Fix building for 64bitArthur Heymans
Tested with clang on prodrive/hermes: Boots to payload Change-Id: I66392bcb4ed94c97dde43342dd29dab15d1dd9ea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69234 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09soc/intel/elkhartlake: Correct I2C base clock to 100 MHzWerner Zeh
According to measurements Elkhart Lake seems to drive the internal I2C controllers with 100 MHz instead of the common 133 MHz. The datasheet itself is quite vague on this definition, just one place mentions that it is 100 MHz (register description for offset 0x94). This patch changes the I2C controller base frequency to 100 MHz. The verification was done by measuring the set up resulting I2C clock for both 100 and 400 kHz. Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-09soc/amd/common/block/spi: Mainboard to override SPI Read ModeKarthikeyan Ramasubramanian
On certain mainboards due to hardware design limitations, certain SPI Read Modes eg. (Dual I/O 1-2-2) cannot be supported. Add ability to override SPI read modes in boards which do not have hardware limitations. Currently there is an API to override SPI fast speeds. Update this API for mainboards to override SPI read mode as well. BUG=b:225213679 TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of ~25 ms with 100 MHz SPI speeds. Before: 11:start of bootblock 688,046 14:finished loading romstage 30,865 16:FSP-M finished LZMA decompress (ignore for x86) 91,049 Total Time: 1,972,625 After: 11:start of bootblock 667,642 14:finished loading romstage 29,798 16:FSP-M finished LZMA decompress (ignore for x86) 87,743 Total Time: 1,943,924 Change-Id: I160b56f6201a798ce59e977ca40301e23ab63805 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-11-08vboot: Add VBOOT_CBFS_INTEGRATION supportJakub Czapiga
This patch introduces support signing and verification of firmware slots using CBFS metadata hash verification method for faster initial verification. To have complete verification, CBFS_VERIFICATION should also be enabled, as metadata hash covers only files metadata, not their contents. This patch also adapts mainboards and SoCs to new vboot reset requirements. TEST=Google Volteer/Voxel boots with VBOOT_CBFS_INTEGRATION enabled Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I40ae01c477c4e4f7a1c90e4026a8a868ae64b5ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/66909 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-08soc/intel/xeon_sp: accomodate xeon_sp FSPX_CONFIG definitionsJonathan Zhang
Intel FSPs of XEON server platforms define FSPX_CONFIG instead of FSP_X_CONFIG, which is expected by coreboot. Re-define in the common code. Update coreboot code to use FSP_X_CONFIG consistently. Tested=On OCP Delta Lake, boot up OS successfully. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-08vboot: Introduce handy vboot reboot functionsJakub Czapiga
This patch groups vboot context, recovery reason and subcode saving, and reboot calls into two handy functions: - vboot_save_and_reboot() - save context and reboot - vboot_fail_and_reboot() - store recovery reason and call function above Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ie29410e8985e7cf19bd8d4cccc393b050ca1f1c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69208 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-08/: Remove unused <inttypes.h>Elyes Haouas
Change-Id: I16aa756039973e164c887ff5237bda69d042a235 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-08soc/ti/am335x/cbmem.c: Use MiB macroElyes HAOUAS
Use "* MiB" instead of "<< 20". Change-Id: Iab6592804961a34fae6dc8012bfbc70023421a49 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-08soc/intel/meteorlake: Remove PM Energy Report WARavi Sarawadi
Disable Pch PM Energy Report WA was added to enhance boot time with HFPGA only. SoC needs reporting enabled. BUG=None TEST=Build and Boot Google, Rex and Intel, MTLRVP without any boot time regression.. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: If5f1f9c6ab31652977d436a49a3531edffbd60c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69042 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-11-08soc/intel: Use `PWRMBASE` over static `Index 0` for PMCSubrata Banik
This patch replaces static index 0 for PMC read resources with PCI configuration offset 0x10 (PWRMBASE). TEST=Able to build and boot Google, Rex to OS. Without this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 With this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 10 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iee2523876a8045e70effd5824afc327d1113038b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-07soc/qualcomm/sc7280: Move AOP load and reset handle to RomstageSudheer Kumar Amrabadi
As AOP takes 500 msec delay to get up, moving aop load and reset to romstage improves the performance. BUG=b:218406702 TEST=reboot from AP console (on CRD3) prior to fix (from cbmem dump): 1000:depthcharge start 1,139,809 (152,679) after fix (from cbmem dump): 1000:depthcharge start 1,041,109 (46,353) Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org> Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-11-07soc/amd/mendocino: Enable x86 SHA acceleratorKarthikeyan Ramasubramanian
Enable x86 SHA accelerator for use by VBOOT library. This is useful when CBFS verification verifies the hash of the file being loaded in x86. BUG=b:227809919 TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of ~10 ms with CBFS verification enabled. Change-Id: I14efe7be66f28f348330580d2e5733e11603a023 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68954 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07soc/intel/common/block/pcie/rtd3: Skip Power On if _STA returns 1Kane Chen
RTD3,_ON method sometimes can create delays during system boot. Even when the power is already up, kernel still tries to call _ON method to power up device, but it's unnecessary. RTD3._STA returns device power, so _ON method can check _STA and see if the power on process can be skipped BUG=b:249931687 TEST=system can boot to OS with RTD3 pcie storage and save ~80 ms on Crota. Suspend stress test passes 100 cycles Change-Id: I296ce1b85417a5dbaca558511cd7fc51a3a38c84 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-07soc/intel/meteorlake: Implement SOC Die lock down configurationRavi Sarawadi
This patch implements a function to enable IOSF Primary Trunk Clock Gating. BUG=b:253210291 TEST=Able to build and boot rex to OS. Also needed for S0ix, tested with Sandbox OS + Firmware combination for S0ix entry/exit. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I02e191336e99f97f4db58b27f4414001b642ad02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68430 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07soc/intel/meteorlake: Fix incompatible function pointersArthur Heymans
const void is a meaningless return type and clang complains about incompatible function pointer signatures. Change-Id: Ia00706b9cd718e590819621986dbd20555f6c226 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-07soc/amd/common/include/gpio_defs.h: Add comment for accuracyFred Reitberger
The GPIO debounce timebase bit 4 is only 183uS on Picasso. On the other SoCs it is 244uS. This affects the 1mS and 2mS actual debounce times slightly. Time PCO Others 1mS 0.915mS 1.220mS 2mS 2.013mS 2.684mS Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id84bef75e6ab134778721ca269d763a4bb2ddde5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69209 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07soc/intel/cannonlake: Fix GPIO reset mappingAngel Pons
According to document 337348-001 (Intel® 300 Series and Intel® C240 Series Chipset Family Platform Controller Hub Datasheet - Volume 2 of 2), the only GPIOs that support PWROK reset are those in the GPD group. The mappings themselves are correct, but they're assigned to the wrong communities. Change-Id: Ib586c987f768ddff31b053f4c108a8526326a7dc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69214 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-05soc/intel/block/power_limit: Avoid MSR read if it is not neededWerner Zeh
In function 'set_power_limits' there is a path to bail out early if the Kconfig switch SOC_INTEL_DISABLE_POWER_LIMITS is selected. In this case reading the MSR PLATFORM_INFO is useless and can be avoided. So read it right before the value is needed. This was found by the scanbuild. In addition, fix an unnecessary line break to increase code readability. Change-Id: Ibdededdfd56287fb9b9223e78033a3cd6425e1a2 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-04src/soc/amd/mendocino: Enable override of MAINBOARD_BLOBS_DIRNikolai Vyssotski
When using site-local we need to have ability to override MAINBOARD_BLOBS_DIR with a different location (presumably somewhere in site-local). site-local Makefiles.inc should be pulled in first (different CL) allowing MAINBOARD_BLOBS_DIR to be overwritten. Change-Id: I028042b947887d1182642ad4482dd1bba7ad8e23 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-04soc/amd/*/data_fabric: Use common device opsFred Reitberger
Use the common device ops instead of an soc-specific device ops. TEST=builds for each soc Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I1804200c3c3f5ab492d237f4b03484c383862caf Reviewed-on: https://review.coreboot.org/c/coreboot/+/69174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04soc/amd/common/data_fabric: Make common device opsFred Reitberger
Add the generic data_fabric_acpi_name function and device ops to common code. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I12053389a12081ddd81912a647bb532b31062093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04soc/amd/mendocino/data_fabric.c: Make function more genericFred Reitberger
Make the data_fabric_acpi_name function more generic, in preparation to move it to common. TEST=build chausie, dump ACPI tables, and inspect DFD0 to DFD7 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I77140d8d0d6bf3e048b737de03d18142a6e23c1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04soc/amd/*/data_fabric: Move register offsets to socFred Reitberger
Morgana/Glinda have a different register mapping for data fabric access, although the registers themselves are mostly compatible. The register layouts defined by each soc capture the differences and the common code can use those. Move the register offsets to soc headers and update the offsets for morgana/glinda per morgana ppr #57396, rev 1.52 and glinda ppr #57254, rev 1.51 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9e5e7c85f99a9afa873764ade9734831fb5cfe69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04soc/amd/common/block/data_fabric: Use register bitslice structsFred Reitberger
Now that the socs have defined the DF FICAA and MMIO Control registers, update the common code to use them. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia5566f7af6cf5444fc8c627e004dd08185468c77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04soc/intel/meteorlake: Provide mitigation support for CNVi RFIzhaojohn
The DDR RFIM is a frequency shifting RFI mitigation feature required by the Intel integrated Wi-Fi firmware(CNVi) for Meteor Lake. Please refer to Intel technical white paper 640438_Intel_DDR_Mem_RFIM_Policy_Enable once it is externally available. This change has backport changes from commit hash 6f73a20 (soc/intel/alderlake: Move CnviDdrRfim property to drivers) and provides the CNVi RFIM support for Meteor Lake. BUG=b:248391777 TEST=Booted to OS on Rex. Looked the DDR_DVFS_RFI_CONFIG_PCU_REG register at the offset 0x5A40 of Mchbar and verified the BIT0 (RFI_DISABLE bit) is 0. Change-Id: I87110bc10b98a27a8f274680597b15a1df488824 Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67789 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04lib/coreboot_table: Rename lb_fill_pcieArthur Heymans
By convention 'fill_lb_xxx' is used. Change-Id: I046016b3898308bb56b4ad6a5834ab942fdd50f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69183 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04lib/coreboot_table: Simplify API to set up lb_serialArthur Heymans
Instead of having callbacks into serial console code to set up the coreboot table have the coreboot table code call IP specific code to get serial information. This makes it easier to reuse the information as the return value can be used in a different context (e.g. when filling in a FDT). This also removes boilerplate code to set up lb_console entries by setting entry based on the type in struct lb_uart. Change-Id: I6c08a88fb5fc035eb28d0becf19471c709c8043d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-11-04Revert "soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility function"Felix Held
This reverts commit 3bc9fbb496c7e1ae346c8d7e98d2bcabbbbe8673. The patch that added hob_enhancedwarningloglib.h was marked as private after the Jenkins run, so I didn't see and submit it before submitting the patch that gets reverted by this commit. Temporary revert this patch to fix the coreboot tree until the issue with the missing patch is sorted out. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If56609dd2d91a70fe7e99ce86e0341f2b3fee3d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69229 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04soc/intel/alderlake: Add IBECCMaximilian Brune
Add In Band Error Correction Code to Alderlake SOC's. It's currently needed and tested for the Prodrive Atlas mainboard. After enabling it in the UPD, FSP-M takes care of enabling IBECC. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I9cc2ed6defa1223aa422b9b0d8145f8f8b3dd12e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68756 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: I7da9c672ee230dfaebd943247639b78d675957e4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-04soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility functionJohnny Lin
Change-Id: I8f949e9c881099c3723fca056e2c4732ca8b64cf Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69144 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2022-11-04soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-MJohnny Lin
EWL (Enhanced Warning Log) is a FSP HOB generated by FSP-M that may contain several warnings/errors related to core, uncore and memory, etc. mainboard can override it in its romstage.c for its own Enhanced Warning Log check. Change-Id: I6f542e71d20307397c398fd757d9408438f681ed Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69143 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04soc/mediatek/mt8188: Disable input-gating for big-core SRAMLiju-Clr Chen
The input-gating is an experimental feature (but unfortunately default enabled) and would lead to crash on MT8188, so we have to disable it in the firmware stage. BUG=b:233720142 TEST=CPUfreq in kernel test pass. Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69089 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driverLiju-Clr Chen
When enabling cpufreq-hw driver, it is required for MCUPM to access secure registers. Therefore, we enable side-band to allow MCUPM to access the secure registers. BUG=b:236331463 TEST=It works well after boot to login shell. Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69088 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2022-11-04soc/intel/**/fast_spi.c: Drop spurious whitespaceAngel Pons
Drop 1 (one) newline and 1 (one) space. Change-Id: I1972d173f99507dd167bd86c73d99434b04701ab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69167 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-04soc/intel/skylake: Clean up includesElyes Haouas
Change-Id: I505ef39487b2677993423e5952b54e008e24fcc5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04Revert "soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM registers"Liju-Clr Chen
This reverts commit a8172c329fe309f3b5b409c1a59a227186400dd4. In the aforementioned patch, we allowed MCUPM to access secure registers and set the domain to DOMAIN_2. Additional attribute settings are also required when a hardware is set to a specific domain. Otherwise, there would be violation between hardware. Since MT8188 is in bring-up stage, we simply enable access register permission for the DOMAIN_0 by default. So remove the wrong setting for MCUPM, SCP and SSPM. We will complete DEVAPC setting when the settings are confirmed. Change-Id: I5d9809f6e84b8d10bc2e6f2ea5a442e676ad3bf9 Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69139 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-04soc/amd: Specify memory types supported by each chipMartin Roth
This change disables support for memory types not used by each of the chips. This will in turn remove the files for those memory types from the platform builds. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8c7f47b43d8d4a89630fbd645a725e61d74bc2a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04soc/amd/common: Only call into enabled memory typesMartin Roth
Don't call into disabled memory type code, it won't work. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie239039b3dd2b5d0a6f8e9230fd3466bb8309761 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/glinda/data_fabric: Add register bitslice structFred Reitberger
Add structs to define the data_fabric register bitfields, updated per glinda ppr #57254, rev 1.51 Update IOMS0_FABRIC_ID and DF_MMIO_NP per referenced ppr. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I509eaf5910d8d65ce0956200d7c00451ff9ce864 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/morgana/data_fabric: Add register bitslice structFred Reitberger
Add structs to define the data_fabric register bitfields, updated per morgana ppr #57396, rev 1.52 Update IOMS0_FABRIC_ID and DF_MMIO_NP per referenced ppr. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: If64c875026b643c584975f7abffad9b35f1a7b44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/mendocino/data_fabric: Add register bitslice structFred Reitberger
Add structs to define the data_fabric register bitfields. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I01dcea783542ecc0a761191907c1273016f854c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/picasso/data_fabric: Add register bitslice structFred Reitberger
Add structs to define the data_fabric register bitfields. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: If7cc94681cd5e282e09455c0ac7d3675884c3cf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/cezanne/data_fabric: Add register bitslice structFred Reitberger
Add structs to define the data_fabric register bitfields. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib5045812fb05eb8c3fb818d807e34decf69c6fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/69068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/*/data_fabric: move data_fabric_set_mmio_np to commonFred Reitberger
The data_fabric_set_mmio_np function is effectively identical, so move it to common code. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I58e524a34a20e1c6f088feaf39d592b8d5efab58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: Iea29938623fe1b2bcdd7f869b0accbc1f8758e7a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/intel/alderlake: Hook up GMA ACPI brightness controlsTim Crawford
Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Tested by adding gfx register on system76/lemp11. Backlight controls work on Windows 10 and Linux 6.1. Change-Id: I1cc33bf0121ff44aea68a7e3615c5e58e2ab6ce2 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-02soc/intel/common: provide display hook in PEP for ECsMichael Niewöhner
Provide PEP display notification hook for ECs. Change-Id: Icbfd294cdd238e63eb947c227a9cf73daca702ef Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-02soc/intel/common/acpi: provide PTS/WAK hooks for ECsMichael Niewöhner
Provide PTS/WAK hooks for ECs like we do for mainboards. Change-Id: I687254362a896baa590959bd01ae49579ec12c94 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68788 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-31soc: Add SPDX license headers to MakefilesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic875708697f07b6dae09d27dbd67eb8b960749f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-29soc/amd/common: Initialize STB Spill-to-DRAMMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I547671d2bcfe011566466665b14e151b8ec05430 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-10-29soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide AAHB deviceFelix Held
Don't set bit 2 in _STA in order for Windows not to show a warning about an unknown device in the device manager for this device. Since the _STA object just returns a constant, a name definition can be used instead of a method definition. TEST=The unknown device with device instance path ACPI\AAHB0000\0 disappeared from the device manager in Windows 10 build 19045 on a Mandolin board with a Picasso APU. Just shutting down and then booting it again won't clear some internal state in Windows, so a reboot is needed instead for the change to become visible. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8cb1712756c3623cc3ea16210af69cde0fa18f62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-29soc/intel/meteorlake: Move P2SB PCI resource into P2SB deviceSubrata Banik
This patch ensures the P2SB PCI device resource is getting reserved so that the resource allocator is not assigning this resource to any other PCI device during the PCI enumeration. BUG=b:254207628 TEST=Able to ensure on the Google/Rex device, the PCI enumeration is not assigning the P2SB BAR (0xE000_0000) to TBT Root Port3. Instead the 0xE000_0000 address is being assigned to the P2SB PCI device. Without this patch: [SPEW ]     PCI: 00:07.3 resource base e0000000 size c200000 align 20 gran 20 limit ec1fffff flags 60080202 index 20 [DEBUG]      GENERIC: 1.0 [DEBUG]      NONE [SPEW ]      NONE resource base e0000000 size c200000 align 12 gran 12 limit ec1fffff flags 40000200 index 10 With this patch: [SPEW ]     PCI: 00:07.3 resource base e1000000 size c200000 align 20 gran 20 limit ed1fffff flags 60080202 index 20 [DEBUG]      GENERIC: 1.0 [DEBUG]      NONE [SPEW ]      NONE resource base e1000000 size c200000 align 12 gran 12 limit ed1fffff flags 40000200 index 10 ...... [DEBUG]     PCI: 00:1f.1 [SPEW ]     PCI: 00:1f.1 resource base e0000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index 10 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib0789b442af23f6be81c666e284633ef342dffe0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-10-29soc/intel/common: Fix potential NULL pointer dereferenceShaik Shahina
BUG=NONE TEST=Boot to OS on Nivviks Change-Id: I154011963e945b54dfca07f884e473d44dc4e813 Signed-off-by: Shaik Shahina <shahina.shaik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68903 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-29soc/amd/glinda: Don't add amdfw.rom to cbfs in SOC MakefileMartin Roth
CB:66943 - commit 8d66fb1a705 (soc/amd: Add amdfw.rom in coreboot.pre) changed the build flow for the amd firmware binary after glinda was branched from morgana. Update glinda to match the other SoCs. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5b0ccaa8c33e59f7146edd6a86f107480c152008 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-28soc/amd/common: Add coreboot post codes to STBMartin Roth
Adding coreboot's postcodes to the smart trace buffer lets us see the entire boot flow in one place. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8eb9f777b303622c144203eb53e2e1bf3314afaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/68546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-28soc/amd/mendocino: Add code for printing STB to boot logMartin Roth
This adds the mendocino specific code for printing the STB data to the boot log. It still needs to be enabled in the mainboard to be used. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I249507a97ed6c44805e9e66a6ea23f200d62cf66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-28soc/amd/common: Add code to print AMD STB to boot logMartin Roth
This allows platforms that support AMD's STB (Smart Trace Buffer) to print the buffer at various points in the boot process. The STB is roughly a hardware assisted postcode that captures the time stamp of when the postcode was added to the buffer. Reading from the STB clears the data. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8d78c0e86b244f3bd16248edf3850447fb0a9e2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-28soc/amd/mendocino: Expand extra 5 DPTC thermal related profilesEricKY Cheng
Expand extra 5 DPTC thermal related profiles for Dynamic Thermal Table Switching support. BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: Ie03de155325cbb340fce09848327ff7fa33ab1fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/68469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2022-10-28soc/intel/xeon_sp: Remove unused madt setup functionArthur Heymans
Change-Id: I248974c5a88768ee12f63fa77f3fa67a72ea510e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-10-28soc/amd/cezanne/Kconfig: Enable APOB_HASHFred Reitberger
Enable the APOB_HASH feature. This improves boot times by ~9.5ms. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9261d101eb23465208affbf815385d3f1bdbcd69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-27soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPLSubrata Banik
This patch helps to save 10.200ms of booting time without any issue seen during MP Init. All cores are out from reset and alive. Additionally, no performance degradation is observed while running benchmarks. Refer to Intel Technical White Paper number:751003 for more details. BUG=b:211770003 TEST=Able to boot to ChromeOS with all cores are enabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1886bc5e60c2f6bc1e2f9d3c8d9c11799d2b53c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-10-27Revert "soc/intel/systemagent.c: Fix memory type reporting"Arthur Heymans
This reverts commit 9c2f3cc9d9b3b3b7cfe1e62a70ea3061ca6c15ac. This broke the smihandler for no clear reason on some platforms. Change-Id: I72da99c019241b627ce8b543937364a53a5fe97b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-27soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFSMeera Ravindranath
a) Add LTR disqualification in D3 to ensure PMC ignores LTR from UFS IP as it is infinite. b) Remove LTR disqualification in _PS0 to ensure PMC stops ignoring LTR from UFS IP during D3 exit. c) Add Kconfig (SOC_INTEL_UFS_LTR_DISQUALIFY) check to apply this LTR WA. BUG=b:252975357 TEST=build and boot nirwen and see no issues in PLT runs Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-27soc/intel/{adl, cmn}: Allow config to select the OCP workaroundSubrata Banik
This patch introduces a config option for SoC code to choose the applicable SoC workaround. For now, we have introduced `SOC_INTEL_UFS_OCP_TIMER_DISABLE` to apply UFS OCP timeout disable workaround. At present ADL SoC only selects so, and in future MTL and others should check with Intel prior selecting this kconfig. It's the placeholder to add more workaround in required going forward. BUG=none TEST=Able to build and boot Google/Brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia2364d2de9725256dfa2269f2feb3d892c52086a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68309 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-26soc/amd/mendocino: Enable GPP clk req disabling for disabled devicesRobert Zieba
Enable GPP clk req disabling for disabled PCIe devices. If a clk req line is enabled for a PCIe device that is not actually present and enabled then the L1SS could get confused and cause issues with suspending the SoC. BUG=b:250009974 TEST=Ran on skyrim proto device, verified that clk reqs are set appropriately Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68139 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-26soc/amd/cezanne: Update GPP clk req code to use ARRAY_SIZERobert Zieba
Currently the GPP clk req configuration code assumes that the size of the config array is `GPP_CLK_OUTPUT_COUNT`. This commit changes that code to use the `ARRAY_SIZE` macro instead. BRANCH=guybrush BUG=b:250009974 TEST=Ran on nipperkin device, verified that clk req settings are correct. Change-Id: I3ff555843c6f5aa38acd8300e0dc2da4e33fb4b7 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-26soc/amd/cezanne: Factor out common GPP clk req codeRobert Zieba
Factor out the `gpp_dxio_update_clk_req_config` function as it will be useful for other AMD SoCs. BUG=b:250009974 TEST=Ran on nipperkin device, verified clk req settings match enabled devices Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-26soc/amd/common/include: introduce and use FCH_IRQ_ROUTING_ENTRIESFelix Held
Instead of using magic constants for the fch_pic_routing and fch_apic_routing array sizes, define FCH_IRQ_ROUTING_ENTRIES in the common code headers and use this definition. This also allows to drop the static assert for the array sizes. In the Stoneyridge mainboard code the equivalent arrays are named mainboard_picr_data and mainboard_intr_data; also use FCH_IRQ_ROUTING_ENTRIES as fixed array size there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d7ee46bd013ce413189398a144e46ceac0c2a10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68818 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26mb/amd,google: move fch_irq_routing struct definition to soc/amdFelix Held
Define the fch_irq_routing struct once in a common header file instead of in every mainboard's code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I11d9000b6ed7529e4afd7f6e8a7332c390da6dab Reviewed-on: https://review.coreboot.org/c/coreboot/+/68817 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26soc/amd/common/psp_verstage: Pass SRAM buffer to Crypto EngineKarthikeyan Ramasubramanian
Crypto engine prefers the buffer from SRAM. CBFS verification may pass the mapped address of a CBFS file from SPI flash. This causes PSP crypto engine to return invalid address. Hence if the buffer is from SRAM, pass it directly to crypto engine. Else copy into a temporary buffer before passing it to crypto engine. BUG=b:b:227809919 TEST=Build and boot to OS in skyrim with CBFS verification enabled using both x86 verstage and PSP verstage. Change-Id: Ie9bc9e786f302e7938969c8093d5405b5a85b711 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26soc/amd/mendocino: Add GSVCD rangeKarthikeyan Ramasubramanian
Add region/range of SPI ROM to be verified by Google Security Chip (GSC). BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled. Change-Id: If8a766d9a7ef26f94e3ab002a9384ba9d444dd1f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26soc/amd/mendocino: Update build rules for PSP BIOS imageKarthikeyan Ramasubramanian
Do not compress PSP BIOS image when CBFS verification is enabled. Otherwise when a file is added to CBFS, cbfstool is not able to find the metadata hash anchor magic in the compressed PSP BIOS image. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled for both x86 and PSP verstage. Change-Id: Iaed888b81d14ede77132ff48abcfbeb138c01ce4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26soc/amd/mendocino: Reserve more space for metadataKarthikeyan Ramasubramanian
With CBFS verification enabled, CBFS file header + file name + metadata consumes more than 64 bytes. Hence reserve additional space aligned to the next 64 bytes. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled. Change-Id: I2b7346e2150835443425179048415f3b27d89d89 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66944 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26soc/amd: Add amdfw.rom in coreboot.preKarthikeyan Ramasubramanian
This change ensures that amdfw.rom binary containing metadata hash anchor is added before any file is added to CBFS. This will allow to verify all the CBFS files that are not excluded from verification. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled using x86 and PSP verstages. Change-Id: Id4d1a2d8b145cbbbf2da27aa73b296c9c8a65209 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26soc/amd: Add an optional unsigned section in PSP verstageKarthikeyan Ramasubramanian
To enable RO CBFS verification in AMD platforms with PSP verstage, metadata hash for RO CBFS is kept as part of verstage. This means any updates to RO CBFS, before WP is enabled, requires updating the metadata hash in the verstage. Hence keep the metadata hash outside the signed range of PSP verstage. This means the metadata hash gets loaded as part of loading PSP verstage while still being excluded from the verification of PSP verstage. This change keeps the metadata hash outside the PSP footer data. This will help to keep it outside the signed range of PSP verstage & aligned to 64 bytes. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled with both x86 and PSP verstage. Change-Id: I308223be8fbca1c0bec8c2e1c86ed65d9f91b966 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68135 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26util/amdfwtool: Add build rules for amdfwreadKarthikeyan Ramasubramanian
Add build rules to build amdfwread tool. Also mark this as a dependency either while building tools or amdfw.rom. BUG=None TEST=Build and boot to OS in Skyrim with CBFS verification enabled. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I3fee4e4c77f62bb2840270b3eaaa58b894780d75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66939 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26coreboot_tables: Drop uart PCI addrArthur Heymans
Only edk2 used this to fill in a different struct but even there the entries go unused, so removing this struct element from coreboot has no side effects. Change-Id: Iadd2678c4e01d30471eac43017392d256adda341 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-26mb/google/rex: Move `DRIVERS_INTEL_USB4_RETIMER` configSubrata Banik
This patch moves DRIVERS_INTEL_USB4_RETIMER config from Meteor Lake SoC to Rex mainboard to maintain the symmetry with previous generation ChromeOS devices (Brya and Volteer). BUG=none TEST=Able to build and boot to Google/Rex with USB4 functionality remaining intact. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I38360f6f1f2fcb4b0315de93c68f00d77e63003c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-25soc/amd: Add framework for Glinda SoCMartin Roth
This adds the initial framework for the Glinda SoC, based on what's been done for Morgana already. I believe that there's more that can be made common, but that work will continue as both platforms are developed. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I43d0fdb711c441dc410a14f6bb04b808abefe920 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-25soc/intel/alderlake: Add Raptor Lake device IDsLawrence Chang
Add system agent ID for RPL QDF# Q271 TEST=Tested by ODM and "MCH: device id a71b (rev 01) is Unknown" msg is gone Signed-off-by: Lawrence Chang <lawrence.chang@intel.corp-partner.google.com> Change-Id: I6fd51d9915aa59d012c73abc2477531643655e54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-25soc/intel/common: Clean up includesElyes Haouas
Change-Id: I0081fcf3c842d8772a7045f8dc5754a2e6c039b8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-25soc/intel/tigerlake: Clean up includesElyes Haouas
Change-Id: I9c75e900d05d16de830c750f074df84bb17f64dc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-10-25soc/intel/xeon_sp: Add functions to store/restore uart state in smmTim Chu
When CONFIG_DEBUG_SMI is enabled SMM handler performs console hardware initialization that may interfere with OS. Here we store the state before console initialization and restore state before SMM exit. Tested=On not public yet system, after exiting smm, uart console can still work well. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Ifa5042c24f0e3217a75971d9e6067b1d1f56a484 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-10-25soc/intel/elkhartlake: Fix incorrect divider for MDIO clockWerner Zeh
After some measurements it turned out that Elkhart Lake uses a higher CSR clock internally from which the MDIO clock is derived. In order to stay compliant with the specification, the MDIO clock needs to be lower than 2.5 MHz. Therefore, the divider needs to be 102 and not 62. This patch changes the define to match the new divider value and uses this new define at the appropriate place. Test=Measure the MDIO clock rate on mc_ehl2 which results in 2 MHz. Change-Id: Idf498c3547530dfa395f54488ef244e787062e34 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-10-25soc/intel/eklhartlake: Provide an option to disable the L1 prefetcherWerner Zeh
Depending on the real workload that is executed on the system the L1 prefetcher might be too aggressive and will populate the L1 cache ahead with data that is not really needed. In the end, this will result in a higher cache miss rate thus slowing down the real application. This patch provides a devicetree option to disable the L1 prefetcher if needed. This can be requested on mainboard level if needed. Change-Id: I3fc8fb79c42c298a20928ae4912ee23916463038 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68667 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25soc/mediatek/mt8188: replace SPDX identifiers to GPL-2.0-only OR MITRex-BC Chen
For MT8188, the SPDX identifiers are all GPL-2.0-only OR MIT, so replace "GPL-2.0-only" with "GPL-2.0-only OR MIT". Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I5ef6c488b7ef937f6e298670ea75d306b9fe7491 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68759 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25soc/mediatek/mt8188: Update mtcmos settings for display and audioBo-Chen Chen
- For display, only vdosys0_pwr_con and edp_tx_pwr_con settings are required. - For audio, it requires powering on adsp_ao_pwr_con, adsp_infra_pwr_con and audio_pwr_con. - Add new power domain data `ext_buck_iso_bits` for buck isolation control. BUG=b:244208960 TEST=access display registers successfully. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I7f00bda0cc5c7f8dea55a564a0ff10ae601115b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-10-25soc/mediatek/mt8188: Add eDP support for firmware displayBo-Chen Chen
MT8188 supports eDP as internal display interface. BUG=b:244208960 TEST=emerge-geralt coreboot. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6441a36557b097e041bc081b907eb60b56c9fbe6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2022-10-25soc/mediatek/mt8188: Add ddp driver to support eDP outputNathan Lu
Add DDP (display data path) driver that supports overlay, read/write DMA, etc. The output goes to display interface DP_INTF0 directly. Add ddp gclast and output_clamp settings to MT8188 to support multi-layer display. BUG=b:244208960 TEST=emerge-geralt coreboot. Signed-off-by: Nathan Lu <nathan.lu@mediatek.com> Change-Id: Icc0a878c609818fedd298c141bb39469fd2f6388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68487 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 18:26:49 +0000