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Each bit in the GPIO wake status index registers is set to 1 when at
least one of 4 corresponding GPIO pins has its wake status register set.
Added the comment since the gpio_base + i * 4 in the next line looked as
if it calculates some absolute register value which is not what the code
does or should be doing.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2fc8e9c5bd7c1b011f364b05d0cfdeb0df88ada6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56703
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the parameter the variable gets compared with is size_t type, use
size_t as type for that variable too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If82a948bf71079d456616f4438f4b754e0d7262d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56702
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With the addition of the remote GPIO support, the GPIO number won't fit
into 8 bit any more, so use the gpio_t type instead which is an uint32_t
typedef.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3de93fd3a2f2af3c1e3b335fef84019c56482051
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56693
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I75f1e45ead4a5f04cba1eecb220ef027a8bfd09e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56678
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The offsets of all GPIOs in the up to four regular banks are all
calculated relatively to ACPIMMIO_GPIO0_BANK, so we can just drop the
unused defines for ACPIMMIO_GPIO1_BANK and ACPIMMIO_GPIO2_BANK.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I832ffdca479c1f07219a23b4a7f9be69322dfe03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56675
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPIO bank 3 isn't used in coreboot, but the existence is documented in
both the Picasso PPR #55570 Rev 3.16 and Cezanne PPR #56569 Rev 3.01 and
for those two SoCs all 4 banks are covered by the corresponding
Memory32Fixed region in the DSDT.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id444a97a398d7e3abfd1f5c4a32e762ee6ff68f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56674
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As EHL UART source clock is 120MHz, update the clock divider
parameters (M & N) to reflect the right value.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I30c21bc4d1ef901a318a12664b61be75c1acf23b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for ADL:
1. H54G46CYRBX267
2. H54G56CYRBX247
3. K4U6E3S4AB-MGCL
4. K4UBE3D4AB-MGCL
BUG=b:194686484 b:194765811
TEST=build.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If85088f843ab11cc531a3975b5cac3e36b573970
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This reverts commit 4c569b52f6053fc39cb07eed4a0753ade567c5b6. This has
introduced a regression in mainboards using JSL SoC such that it
overrides the soft straps for all the GPIOs. This in turn has led to
some of the peripherals not working.
BUG=None
TEST=Build and boot to OS in Storo. Ensure that the regressed
peripherals are working back again.
Change-Id: Ibfeed1075fe28051b926ddd7ca771693dc19dae8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56613
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 16f2c5082c92ceb4defc252819aaeca96d801543.
Change-Id: Id0f960fdeca5895afc22809ff3f0236d6dbe82f4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56614
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This dev tree config controls the Vnn/Vcc1P05 bypass mode for Jasperlake.
BUG=b:191691430
BRANCH=dedede
TEST=Build fw and confirm FSP setting are set properly by log
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Change-Id: I10bc203d3fed32ab65f325978426b7d0fca6f392
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This patch adds device tree settings to control pcie modphy tuning
FSP UPDs. With this patch, the pcie modphy can be tuned per board.
BUG=b:192716633
BRANCH=NONE
TEST=build dedede variant coreboot with fw_debug enable and check if
these settings have been changed successfully on fsp debug log.
Change-Id: I80a91d45f9dd8ef218846e1284fdad309313e831
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The biosram accessor support in soc/amd/common/block/acpimmio/biosram.c
is only used on Stoneyridge and the old amd/southbridge code and not on
Picasso or Cezanne. It also only builds as a 32 bit binary and breaks
when trying to build as a 64 bit binary, since the size of an uintptr_t
is different on those two. There is no support for using the 32 bit
binaryPI with a 64 bit coreboot while there is code to use a 32 bit FSP
with 64 bit coreboot, so not building this for FSP-based SoC support
moves us one step closer to be able to build coreboot as 64 bit binary
for Picasso and Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d87ec2fa1b217eaf55d865e4390308812502e56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol
more than once. This is done in `src/Kconfig`, along with its prompt.
Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Jasperlake is one of the few SoCs that support programmable VCCIO
selection and this support is used by Dedede mainboard.
BUG=b:194120188
TEST=Build and boot to OS in Gallop. Ensure that the VCCIO selection is
configured as expected and probing the GPIO reads the configured
voltage.
Change-Id: I54def27a499ccba7fd25cab1048fdca06dbc535f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56536
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some of the Intel SoCs with more than 2 PAD configuration registers
support programming VCCIO selection. Add a pad configuration macro to
program VCCIO selection when the GPIO is an output pin.
BUG=b:194120188
TEST=Build and boot to OS in Gallop. Ensure that the VCCIO selection is
configured as expected and probing the GPIO reads the configured
voltage.
Change-Id: Icda33b3cc84f42ab87ca174b1fe12a5fa2184061
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56507
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Verstage even fits in 44K so one can comfortably increase the
bootblock size. This is need for the followup patches that turn
console methods into drivers, which increase the bootblock a little,
but still too much for the the bootblock to fit in the alloted size on
this platform.
Change-Id: If1eaf2b495e3032d156433fd0728134a66f4e49b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56521
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Provide an option to set xHCI LFPS period sampling off time
(SS_U3_LFPS_PRDC_SAMPLING_OFFTIME_CTRL in JSL EDS revision 2.0).
If the option is set in the devicetree, the bits[7:4] in
xHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated.
The host will sample LFPS for U3 wake-up detection when suspended, but
it doesn't sample LFPS at all time due to power management, the
default xHCI LFPS period sampling off time is 9ms. If the xHCI LFPS
period sampling off time is not 0ms, the host may miss the
device-initiated U3 wake-up and causes some kind of race condition for
U3 wake-up between the host and the device.
BUG=b:187801363, b:191426542
TEST=build coreboot with xhci_lfps_sampling_offtime_ms and flash
the image to the device. Run following command to check the bits[7:4]:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Ben Kao <ben.kao@intel.com>
Change-Id: I0e13b7f51771dc185a105c5a84a8e377ee4d7d73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Log the GPE and PM1 wake events into the event log using the SMI handler
platform callback.
BUG=b:186792595, b:186800045
TEST=Build and boot to OS in Guybrush. Ensure that the wake sources are
logged into the event logs.
5 | 2021-07-15 16:26:43 | S0ix Enter
6 | 2021-07-15 16:26:49 | S0ix Exit
7 | 2021-07-15 16:26:49 | Wake Source | GPE # | 22 <- Trackpad
8 | 2021-07-15 16:27:07 | S0ix Enter
9 | 2021-07-15 16:27:13 | S0ix Exit
10 | 2021-07-15 16:27:13 | Wake Source | RTC Alarm | 0
25 | 2021-07-15 16:38:13 | S0ix Enter
26 | 2021-07-15 16:38:17 | S0ix Exit
27 | 2021-07-15 16:38:17 | Wake Source | GPE # | 5 <- Fingerprint
Change-Id: Icec6fc03f4871cc46b32886575a7054bc289f4bf
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Move the event logging helpers defined in acpi into a separate library.
This will allow logging power management and GPE events for both S3 and
Modern Standby. Introduce a single helper acpi_log_events function to
log both PM and GPE events.
BUG=None
TEST=Build and boot to OS in Guybrush.
Change-Id: I96df66edfc824eb3db108098a560d33d758f55ba
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I16c41031718e1c3e41d0a128c8b254e2f6f94093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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TEST=Checked on amd/mandolin with PCO APU and google/guybrush with CZN
APU that the McaXEnable bit is set in the CONFIG registers of all used
MCAX banks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia4515ba529e758f910d1d135cdce819f83ea0b5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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It appears the pspp_policy enum is not the same as the FSP definition
currently being used. This means that the incorrect PSPP value setting
would get read by FSP. For Zork programs this meant we actually were
setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE.
This change adds DXIO_PSPP_DISABLED as the first enum value to properly
match the FSP definition and adjusts non AMD Customer Reference Boards
that reference the enum to still send the same value even though it has
now change definitions. If we actually want DXIO_PSPP_POWERSAVE for
those boards that can be adjusted in a future change.
BUG=b:193495634
TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi
with other server on local network.
Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
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Update comment section to add space before comment delimiter to
follow coding style.
Change-Id: I883aeaa9839fa96fd7baf0c771b394409b18ddca
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56547
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I49a27eb084b59db455153dd662d564a95940a0ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Stoneyridge has an integrated FCH and no south bridge, so change the sb
prefix to fch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5154ae1158f864d4a2aca55e6bcce6a742c6afe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56527
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Picasso has an integrated FCH and no south bridge, so change the sb
prefix to fch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I82aed68104ea9570827646c818e100bd7e04d1af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56526
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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sb_clk_output_48Mhz is only used in fch.c where it is also implemented,
so no need to have it visible outside of that compilation unit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2b0d10ff26bdf54ea791aa66bf400578466d54cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56525
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: Ic6c70f917a59e233f6ea518d9c39f73fe84991c3
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47284
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The common gpio driver can be re-used for SC7180,
thus remove the existing gpio driver support and
also clean up the common macro definitions.
Add GPIO pin details specific to SC7180 chipset
for the consumers to be able to request for the
gpio functionality as per their requirement.
TEST=Validated on qualcomm sc7180 development board
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Ifd206e6bc9a549706e7a2c4bde0b7d5527ca6268
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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This enables the MCAX checking and BERT entry generation for Cezanne.
TEST=When printing all registers of all MCAX banks of core 0 on a
google/guybrush device, the registers have values that look correctly
and there is no general protection fault, so all MCAX MSRs that could be
accessed exist on Cezanne.
BUG=b:192997706
Change-Id: Ibe8047ce5bb5e7136a8786693bcced4d2225b1fd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56345
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable RSA and SHA for cezanne since support has been added to the PSP.
Also picasso and cezanne have different enums definitions for
hash algorithm, so split that out into chipset.c.
BUG=b:187906425
TEST=boot guybrush, check cbmem -t and the logs
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I725b0cac801ac0429f362a83aa58a8b9de158550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This allows keeping track of how long it takes to load the microcode.
BUG=b:179699789
TEST=Boot guybrush
112:started reading uCode 990,448 (10,615)
113:finished reading uCode 991,722 (1,274)
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I86b67cf9d17786a380e90130a8fe424734e64657
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Use the gpio offset macro instead of a constant value.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Ia9e4b9ca7216092665f0a06ce467da01963c2364
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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As part of GPIO driver cleanup across qcom chipsets,
GPIO_OUTPUT_ENABLE has been renamed to GPIO_OUTPUT.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I51eedc722a91c5ea8e009fb8468a60667d374b49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Defining a macro for the gpio offset instead of a constant value.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Iefdde8f8331cf1df2e88a2c8915aefb4fa091d65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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With the new definition of mt6360_regulator_id,
merge the MT6360 LDO and PMIC interfaces into one.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7ccc32cb0a9481d5f55349c152267a44fe09d20a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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On MT8195 platforms with BC1.2, we have to use EC to control
MT6360 so the mt6360_regulator_id is redefined to match the
numbers defined in EC driver.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I9437edb9776442759ce04c31d315c3760078ffb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56434
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As per the EDS revision 1.3 add support for I2C6 and I2C7.
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Id918d55e48b91993af9de8381995917aef55edc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55996
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I6eb0881ab05730b094caef2a9258c4d4d827195b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: I4726ba4f19807adf872aaf04764cc19492febd59
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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If we don't escape the $ then the actual $(obj) path will be written
into the .config file. With this change `$(obj)` is written into the
.config file. The Makefile then does:
PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE))
Since this is a recursive assignment the $(obj) will be expanded at that
point.
This change makes it easier to compare full .config files.
BUG=none
TEST=Build ezkinil
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic961df148d3f22585f3441d75c3f2454329c678a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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This change allows preloading the payload.
BUG=b:179699789
TEST=Boot guybrush and see payload read/decompress drop by 20 ms. We
now spend 7ms decompression from RAM. By switching to LZ4 we drop that
to 500us.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3ec78e628f24f2ba0c9fcf2a9e3bde64687eec44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Rename PMC_EPOC to SOC_INTEL_COMMON_BLOCK_PMC_EPOC to maintain
common naming convention.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: If8a264007bbb85a44bbdfa72115eb687c32ec36e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This enables COOP_MULTITASKING (i.e., multiple stacks single CPU). This
will allow the APOB to start loading while FSP-S executes.
BUG=b:179699789
TEST=Boot guybrush and verify APOB read timestamp has dropped from 10ms
to a few uS.
Starting APOB preload
APOB thread running
spi_dma_readat_dma: start: dest: 0xcb7aa640, offset: 0x0, size: 65536
took 0 us to acquire mutex
start_spi_dma_transaction: dest: 0xcb7aa640, offset: 0x0, remaining: 65536
<ramstage doing work>
spi_dma_readat_dma: end: dest: 0xcb7aa640, offset: 0x0, size: 65536, remaining: 0
<more work..>
waiting for thread
took 0 us
APOB valid copy is already in flash
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4b5c1ef4cad571d1cbca33b1aff017a3cedc1bea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56234
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This CL adds a method that can start the processes of reading the APOB
from SPI. It does require more RAM in ramstage since we no longer mmap
the buffer in the happy path. This will allow us to reduce our
boot time by ~10ms. The SoC code will need to be updated to call
start_apob_cache_read at a point where it makes sense.
BUG=b:179699789
TEST=With this and the patches above I can see a 10 ms reduction in
boot time on guybrush.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I930d58b76eb4558bc4f48ed928c4d6538fefb1e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56232
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Using fmap_locate_area is discouraged.
BUG=b:179699789
TEST=Boot guybrush and verify APOB got updated, then reboot and verify
APOB was valid.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7f58eace8adb4b7ddaf9047d9b8153405d3941a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56390
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is no telling when the next udelay will be, so explicitly call
`thread_yield()` after completing a transaction. This will allow any
pending transactions to immediately start.
BUG=b:179699789
TEST=Verify new transaction is enqueued right after another.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9c1272bde46c3e0c15305b76c2ea7a6dde5ed0b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56321
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Once we enable COOP_MULTITASKING, we need to guarantee that we don't
have multiple threads trying to access the DMA hardware.
BUG=b:179699789
TEST=Boot guybrush with APOB patches.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibb8e31c95d6722521425772f4210af45626c8e09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56231
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change will make it so the standard rdev readat call will use the
SPI DMA controller if the alignment is correct, and the transfer size is
larger than 64 bytes.
There is a magic bit that needs to be set for the SPI DMA controller to
function correctly. This is only available in RN/CZN+.
BUG=b:179699789
TEST=Boot guybrush to OS. This reduces loading verstage by 40ms,
verifying RW by 500us and loading romstage by 500 us.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Also rename the existing PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU
definition to PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_CEZANNE to clarify
that that is the one for Cezanne.
BUG=b:193888172
Change-Id: I1c5446c1517f2e0cd708d3275b08d2bce4be0ea8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56396
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Barcelo uses the same VBIOS image as Cezanne, but uses a different PCI
ID, so we need to implement map_oprom_vendev for the SoC.
BUG=b:193888172
Change-Id: I2eed43705f497245bd953659844b3fb461aa0b3b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56392
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Alder Lake supports IGD Opregion version 2.1.
BUG=b:190019970
BRANCH=None
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I95a6f3df185003a4e38faa920f867ace0b97ab2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Elkhart Lake provides option to configure FIVR (Fully Integrated
Voltage Regulators) via parameters in FSP-S.
This CL removes fixed FIVR config values and expose these parameters
to the devicetree so that they can be configured on mainboard level
as needed.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ie1b0e0cc908ba69805dec7682100dfccb3b9d8b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I8621a38214686b359ee0e7cdf7e92154af3cbc81
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56381
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.
Change-Id: I129f169e5dc394a11d8f7b07486cca4894dbec8e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.
Change-Id: Ieb8063116bee59f6f6bf1f6b0b2349ce22bd67bd
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
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Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.
Change-Id: Iefc19bc81125f422b8d4fc2f4af60622e7d28c0f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.
Change-Id: I00ebb9a124eb3b8b893c2b176e14773c05851c18
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.
Change-Id: I97f4d9715f3205678acca8fcdfb1a62714dfaa53
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.
Change-Id: I2123a081baaf6fd254fe81d64eaeee1e3248dd34
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56371
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.
Change-Id: I773114a703d62bf469aa74b128c697cc0924cc3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.
Change-Id: Ib62ad6a5381d346011fbc838dcd64b095fccd67b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch removes all local `CPUID_` macros from SoC directories and
creates a common cpu_ids.h inside include/cpu/intel/cpu_ids.h. SoC
users are expected to add any new CPUID support into cpu_ids.h and
include 'cpu/intel/cpu_ids.h' into respective files that look for
`CPUID_` macro.
Note: CPUIDs for HSW, BDW and Quark are still inside the respective
directory.
Change-Id: Id88e038c5d8b1ae077c822554582410de6f4a7ca
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch removes leading zero from CPUIDs as below:
0x05065a -> 0x5065a
0x05065b -> 0x5065b
Change-Id: I240a06e3b3d7e3dc080f9a9ed1539fadc982495d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Change-Id: Iff19ae495fb9c0795dae4b2844dc8e0220a57b2c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This leverages the existing Collaborative Processor Performance Control
(CPPC) support and adds CPPC init for AMD/Cezanne.
BUG=b:185814875
TEST=under Linux/ChromeOS, acpidump ssdt2, find expected CPPC entries
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Also move the registers in the order they are in the hardware.
Change-Id: If018e746e58c14475caeda76feb8b5281d7732f1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56315
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Only when ACPI_BERT is selected the BERT functionality needs to be
included in the build.
Change-Id: I8a21562f4535fb0ea3c53f2ea8df50f66cc6a64c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56314
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since we don't need to skip the MCA check on cold boot on MCAX capable
systems, add a mca_skip_check implementation that always returns false.
Change-Id: Id8fc4b6f02b6c02b03172fe11f0451a9893e514d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This will allow moving mca_check_all_banks to mca_common.c.
Change-Id: I58e100c1447907bab984a2fdff6c6e0181910c23
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This aligns the mca_check_all_banks implementation in the common mca.c
with the one in the common mcax.c file. Do the MCA bank count check
before the !is_warm_reset() check, so that a mismatch also gets printed
on the cold boot path.
Change-Id: Idbd3e9ce9c7483f84f87adab7adac47335cd59aa
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Since those functions are implemented and used only inside the common
MCA(X) code, there's no need to have them in the header file that gets
included in the SoC-specific code.
Change-Id: Ia84e149d67ac7d80de595379c73a6cf08730719d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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For Cezanne stubs are added for the functions that the SoC-specific code
needs to provide. Since the mca_is_valid_bank stub on Cezanne always
returns false, the checks get skipped for it at the moment. The actual
functionality will be added in a later patch.
Change-Id: Ic31e9b1ca7f8fac0721c95935c79150d7f774aa4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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To factor out the rest of the common MCAX code, mca_bank_name[] may only
be accessed by accessor functions, so implement this for the last place
that still accessed mca_bank_name[] directly.
Change-Id: Ic6548d3ceeb9c00ad344fc0bb3d97893e17a43a9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56294
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I03365c3820cbe7277f14adc5460e892fb8d9b7a5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56284
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I960a2f384f11e4aa5aa2eb0645b6046f9f2f8847
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56283
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Alder Lake SoC has virtual GPIOs for community 1 which was being
programmed by FSP and hence was skipped by coreboot. As part of
moving most of the GPIO programming to coreboot, we're skipping this
programming in FSP now.
TEST=Check register offset to see if programming is correct.
Change-Id: I4d48553d14465df50e5aaaf27ab26c6a1b70d4cf
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55270
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable FSP Crashlog UPDs if SA_DEVFN_TMT is enabled and
SOC_INTEL_CRASHLOG is selected by the SoC user.
Change-Id: Ibcd0259da86c8d9853e6cc4983675ac97df46c2d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56299
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable FSP Crashlog UPDs if SA_DEVFN_TMT is enabled and
SOC_INTEL_CRASHLOG is selected by the SoC user.
Change-Id: I0244e2a3f9c000a5c6ecdade1419aa47f51b1e80
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56298
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I67a88298c19657a5049ab69799be887555ca7240
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Change-Id: I139d1fe41bad5213da8890c2867f275b6847e3e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56281
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This will allow factoring out and moving check_mca() to soc/amd/common.
Change-Id: I92c7657baef17c248a5aef1eda268e9647502837
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56280
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia489dbfba59c334cf29f96a4000cef73b9b797d4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56279
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch changes the way how the not implemented MCA bank 3 gets
skipped. For the not implemented bank 3 the name gets set to NULL
resulting in mca_is_valid_bank returning false causing the bank to get
skipped. This is a preparation for commonizing the MCA(X) handing in the
soc/amd sub-tree.
Change-Id: I40d6a6752504d804c45b445fce7e763e80161211
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I42abff5efcd7c85d2932a7aaacc736d0376cfaa0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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In mca_check_all_banks only check valid MCA banks for errors. This
aligns the Picasso code a bit more with the Stoneyridge code base which
will be updated in a follow-up patch. This is a preparation for
commonizing the MCA(X) handing in the soc/amd sub-tree.
Change-Id: I0c7f3066afd220e6b8bf8308a321189d7a2679f6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56275
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The length of mca_bank_name should match the return value of
mca_get_bank_count which gets the number of MCA banks from an MSR.
TEST=No error message on serial console on amd/mandolin
Change-Id: Ibdad51a7ef27266e110dfbb43188361952618342
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56274
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also use array indices for the initialization.
TEST=Checked with the public Picasso PPR #55570-B1 Rev 3.16
Change-Id: I10a65210da73e64b67d613609fcc0f9a245a81fb
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56273
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id640fd8006c47ce1db8a8729407c1c9a9c1e79c3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56272
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ifbcad4d81fb9f6c359a870be73b05ed86441e7f0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56271
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to the AMD FCH architects, we should be using the default
value for the NO_HOG bit. This fixes a problem where the SPI DMA no
longer functions after the LPC init runs.
BUG=b:179699789, b:192373221
TEST=Boot guybrush and see SPI DMA working
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If015869657f36d3533f4ab9ebd1f54b0d4eb283a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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There is no technical reason this needs to be done in romstage. Moving
it into ramstage allow us (in future CLs) to use threads to pre-load
the apob from SPI.
BUG=b:179699789
TEST=Boot and Ezkinil and Guybrush and verify APOB update still work
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The %p format specifier already prints out 0x, so remove the 0x from the
string. I also updated the other format specifiers to use the %# syntax
to print out the 0x.
BUG=b:179699789
TEST=see correct format.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5b00d2c06687e549f69486eb5e18f7bed560b2ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56225
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently the MCA support for Cezanne only clears the MCA status
registers. The MCA error handling and BERT table generation will be
added in subsequent patches.
Change-Id: Ib9b5174186c28c8c82f57ffd8936c8dad4e63c5b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Add this macro to be able to conveniently access the MC_CTL_MASK
register for each MCA bank. Also drop the unused definitions for
MC1_CTL_MASK and MC4_CTL_MASK.
Change-Id: I23ce1eac2ffce35a2b45387ee86aa77b52da5494
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This MSR isn't an architectural MSR, so it shouldn't be in the common
x86 MSR definition header file. From family 17h on this register has
moved to a different location.
Change-Id: Id11d942876da217034e6f912b1058f00bd15c22c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Since we can use both the old MCA registers and the new MCAX registers
to access the MCA status registers, we can use the common
mca_clear_status function here.
Change-Id: I9ddcc119eca2659361b1496fd7ffe124fb323d26
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Change-Id: I53413b4051b79d7c2f24b1191ce877155e654400
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56259
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: Ic34f29d1692b94284b2cf6c5d91d323df736c76f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56204
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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