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2021-12-13soc/intel/cannonlake: Configure common FSP memory settings only onceFelix Singer
`meminit_memcfg()` does common memory configuration, which is not specific to each DIMM. Thus, move it out of the for-loop and call it once. Change-Id: If74875b45cd0d7a759883eaf564505ebf281bed5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-12soc/intel/elkhartlake: Hook up public microcodeArthur Heymans
Change-Id: I1d975713129d0a7bce823232d225ed17ee28a04d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-12soc/intel/jasperlake: Hook up public microcodeArthur Heymans
Change-Id: I9e511de5e5b79936ed09538b3877655f78de15a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-12soc/intel/cannonlake: Rename SA_DEV_SLOT_DSPFelix Singer
Device 4 was introduced with a wrong name, since it is the SA Thermal Subsystem and it does nothing have to do with DSP. Thus, rename it accordingly. Change-Id: I8edc764413df5f323098e60d0a3f0f87a7e656cb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60049 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-10soc/intel/{skylake/cannonlake}: Fix bug in vr_configAngel Pons
The `cpu_get_power_max()` function returns the TDP in milliwatts, but the vr_config code interprets the value in watts. Divide the value by 1000 to fix this. This also fixes an integer overflow when `cpu_get_power_max()` returns a value greater than 65535 (UINT16_MAX). Change-Id: Ibe9e0db6762eee5cc363f8b371c8538eb92f6308 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-10soc/intel/cse: config to enable oem key manifestRavindra N
CB change will enable the CSE region sub-partition OEMP, where the OEMP binary will be stitched. OEM KM has Audio FW's key hash. So, CSE uses this information to authenticate Audio FW. BUG=b:207820413 TEST: Boot to kernel and check for the audio authentication is successful localhost ~ # aplay -l **** List of PLAYBACK Hardware Devices **** card 0: sofrt5682 [sof-rt5682], device 0: max357a-spk (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 1: Headset (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 2: HDMI1 (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 3: HDMI2 (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 4: HDMI3 (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 5: HDMI4 (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 Cq-Depend: chrome-internal:4286038 Signed-off-by: Ravindra N <ravindra@intel.corp-partner.google.com> Change-Id: I3620adb2898efc002104e0ba8b2afd219c31f230 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2021-12-09soc/intel/tigerlake: Hook up DPTF device to devicetreeFelix Singer
Hook up `Device4Enable` FSP setting to devicetree state and drop its redundant devicetree setting `Device4Enable`. The following mainboards enable the DPTF device in the devicetree despite `Device4Enable` is not being set. * google/deltaur Thus, set it to off to keep the current state unchanged. Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/intel/tigerlake: Drop unused SataEnable settingFelix Singer
`SataEnable` is set by some boards, but it doesn't have any effect since its related FSP option is hooked up to the devicetree state. Thus, drop it. Change-Id: Id645bfcade7ca1d495fb8df538113b3d10392a82 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-09soc/intel/tigerlake: Hook up SMBus device to devicetreeFelix Singer
Hook up `SmbusEnable` FSP setting to devicetree state and drop its redundant devicetree setting `SmbusEnable`. The following mainboards enable the SMBus device in the devicetree despite `SmbusEnable` is not being set. * google/deltaur * starlabs/laptop Thus, set it to off to keep the current state unchanged. Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/intel/alderlake: Fix value of SA_DEVFN_CPU_PCIE1_0Tim Wawrzynczak
The macro was defined using PCH_DEV_SLOT_CPU_1, which doesn't exist, so replace it with the correct value of SA_DEV_SLOT_CPU_1. Change-Id: If6d294d681907c51ac5678c9251364d4d6df4329 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-12-09soc/amd/stoneyridge: use common fch_spi_early_initFelix Held
All SPI interface setup related functionality that Stoneyridge implemented in its southbridge code is already present in the common AMD SoC code, so use that code instead. The common fch_spi_early_init function requires the SPI controller's base address to be set, so call lpc_set_spibase(SPI_BASE_ADDRESS) right before it. fch_spi_early_init then calls lpc_enable_spi_rom and lpc_enable_spi_prefetch which can be removed from the board code now. Next it calls fch_spi_configure_4dw_burst which does the same as the now removed sb_disable_4dw_burst function when SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST is set to n which is the default. This option can also only be set to y for SoCs that aren't Stoneyridge. Finally fch_spi_early_init calls fch_spi_config_modes which configures the SPI mode and speed settings according to the Kconfig settings and the settings in the amdfw part. On Kahlee this was done by calls to sb_read_mode and sb_set_spi100 before. The previous patch added the remaining Kconfig settings, so the resulting register values don't change in the non-EM100 case. In the EM100 case the TPM speed is changed from 64 to 16 MHz. TEST=Both the non-EM100 mode with a real SPI flash and the EM100 mode with a first-generation EM100 results in Google/Barla reaching the payload and the show_spi_speeds_and_modes call in bootblock prints the expected settings: relevant bootblock console output in non-EM100 case: SPI normal read speed: 33.33 MHz SPI fast read speed: 66.66 Mhz SPI alt read speed: 66.66 Mhz SPI TPM read speed: 66.66 Mhz SPI100: Enabled SPI Read Mode: Dual IO (1-2-2) relevant bootblock console output in EM100 case: SPI normal read speed: 16.66 MHz SPI fast read speed: 16.66 MHz SPI alt read speed: 16.66 MHz SPI TPM read speed: 16.66 MHz SPI100: Enabled SPI Read Mode: Normal Read (up to 33M) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f37a3b040808d6a5a8e07d39b6d4a1e1981355c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-09soc/amd/common/block/psp: add psp_efs.c to build for both PSP GEN1&2Felix Held
The PSP EFS code to get the SPI mode and speed from the amdfw part of the firmware image also works for Stoneyridge which is the one SoC that selects SOC_AMD_COMMON_BLOCK_PSP_GEN1. Also amdblocks/psp_efs.h already handles the SOC_AMD_STONEYRIDGE case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibddd3f9237e561d9f0f6b4ad70f59cce1f956986 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-09soc/mediatek/mt8186: Enable ARM Trusted Firmware integrationRex-BC Chen
Enable configuration to build with MT8186 arm-trusted-firmware drivers. TEST=build pass BUG=b:202871018 Cq-Depend: chromium:3189573 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ib23b112a0bf3d056b932a87b86aaff79508ef50c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-08soc/intel/common/pch: Fix return value documentation for CHIPSET_LOCKDOWNJingle Hsu
Fixed according to the declaration in soc/intel/common/block/include/intelblocks/cfg.h. Change-Id: I50dbc00806fefda8f4dac8bfa21dc714a9504566 Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-08soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resumeRaul E Rangel
According to https://uefi.org/specs/ACPI/6.4/04_ACPI_Hardware_Specification/ACPI_Hardware_Specification.html#pm1-event-grouping > For ACPI/legacy systems, when transitioning from the legacy to the G0 > working state this register is cleared by platform firmware prior to > setting the SCI_EN bit (and thus passing control to OSPM). For ACPI > only platforms (where SCI_EN is always set), when transitioning from > either the mechanical off (G3) or soft-off state to the G0 working > state this register is cleared prior to entering the G0 working state. This means we don't want to clear the PM1 register on resume. By clearing it the linux kernel can't correctly increment the wake count when the power button is pressed. The AMD platforms implement the _SWS ACPI methods, but the linux kernel doesn't actually use these methods. BUG=b:172021431 TEST=suspend zork and push power button and verify power button wake_count increments. Verified other wake sources still work. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-08soc/amd/stoneyridge/southbridge: drop ENV_X86 checkFelix Held
Stoneyridge selects ARCH_X86 unconditionally and all coreboot code will run on the x86 cores. On Picasso and later, the Chromebooks run verstage on the PSP which is an ARM V7 core which needs some special handling cases in the code, but this doesn't apply to Stoneyridge. TEST=Timeless build results in an identical image for Google/Careena. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I013efd13b56c0191af034a8c4b58e9b26a31c6e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-08soc/amd/{cezanne,picasso,stoney}: Clear PM/GPE when enabling ACPIRaul E Rangel
According to https://uefi.org/specs/ACPI/6.4/16_Waking_and_Sleeping/sleeping-states.html?highlight=power%20states# > For ACPI/legacy systems, when transitioning from the legacy to the G0 > working state this register is cleared by platform firmware prior to > setting the SCI_EN bit. This change makes sure we clear the PM/GPE blocks are cleared before enabling the SCI_EN bit. BUG=b:172021431 TEST=Boot guybrush and morphius to OS and verify suspend resume still works. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icc6f542185dc520f8d181423961b74481c0b5506 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-08soc/amd/stoneyridge/southbridge: fix setting SPI_USE_SPI100Felix Held
Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities of the SPI interface. The reference code for Stoneyrige also only sets the SPI_USE_SPI100 bit and doesn't zero out the other bits. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4d32fc2084bb34ea57924bae68511c6836587790 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-08soc/amd/common/block/spi: fix setting SPI_USE_SPI100 in SPI100_ENABLEFelix Held
Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities of the SPI interface. The reference code for both Picasso and Cezanne also only sets the SPI_USE_SPI100 bit and doesn't zero out the other bits. TEST=Verified that Mandolin still boots. It didn't show any signs of possibly related instabilities before though, so this test doesn't say much. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71c2ec1729d5cb4cdff6444b637af29caaa6f1c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-08soc/amd/common/block/include/spi: update fch_spi_early_init descriptionFelix Held
commit 90ac882a32075b44435aa19ea664b89b79cac76e (soc/amd/common/block/ spi: introduce SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST) introduced a Kconfig option to enable/disable the 4DW burst support in the SPI flash data prefetcher, but missed to update the documentation above the fch_spi_early_init prototype, so update the outdated documentation now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I07c4b0b02251da63d34a172e2636894e99845d6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-08soc/mediatek/mt8186: Correct SPI_HZ for PLLRex-BC Chen
The SPI speed is 218.4MHz, so correct the value of SPI_HZ. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I6e8ba10a851e1507405cdd41939a176462734487 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-08soc/mediatek/mt8186: revise SPI NOR GPIO selectionRex-BC Chen
The setting of SPI NOR GPIOs should be: CS: pull up. CLK/IO0/IO1: pull down. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ideacb797a1dc9999ab6ba00cf33adbbbc24213dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-08mb/google/zork,soc/amd/psp_verstage: Add verstage_mb_{tpm/espi}_initRaul E Rangel
These functions can't be weak, because they actually need to configure the GPIOs for eSPI and the TPM. With this change zork boots again. I also noticed that zork doesn't use the early table in bootblock. This means that zork will only boot if psp_verstage is enabled. BUG=b:209465425 TEST=boot zork to ramstage Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I384fd578efe7da0a3d74829cccf38c3ed524f130 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-08soc/amd: use KiB and MiB definitionsFelix Held
Use KiB and MiB instead of multiplying/dividing with/by the numeric value when doing region size calculations. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I56c380190b11aa3214cce31b82974327e3d15000 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-07soc/intel/alderlake: enable gpio lockingNick Vaccaro
This change supplies a list of ADL gpios that are connected to non-host (x86) controllers and should be locked after initial configuration. Set SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS to enable GPIO locking. BUG=b:210430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brya0 boots successfully to kernel. Change-Id: I457bab39f945ab31a89542c6498a73af70cbf9ee Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-07soc/intel/common: add generic gpio lock mechanismNick Vaccaro
For added security, there are some gpios that an SoC will want to lock once initially configured, such as gpios attached to non-host (x86) controllers, so that they can't be recofigured at a later point in time by rogue code. Likewise, a mainboard may have some gpios connected to secure busses and/or devices that they want to protect from being changed post initial configuration. This change adds a generic gpio locking mechanism that allows the SoC to export a list of GPIOs to be locked down and allows the mainboard to export a list of GPIOs that it wants locked down once initialization is complete. Use the SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS Kconfig option to enable this feature. BUG=b:201430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify brya0 boots successfully to kernel. Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06soc/intel/alderlake: Add ADL-P 6+8+2 (28W) VR configCurtis Chen
We only have ADL-P 6+8+2 (45W) VR configuration now. Based on the power map, fill in correct ADL-P 6+8+2 (28W) VR configuration. BUG=b:202486131 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: Ie8dbd95b2d8e49b5898b2a97aff72e0e64868c8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06soc/mediatek/mt8195: complete devapc settingsNina Wu
In previous patch (CB:56764), only basic settings were added. Now complete devapc settings on MT8195. 1. Update permission setting 2. Updtate master domain setting: - domain 1: PCIE0, PCIE1 - domain 2: SPM, SSPM, CPU_EB 3. Set domain remap - MMSYS (4-bit to 2-bit) - TINYSYS (4-bit to 3-bit) - TINYSYS (3-bit to 4-bit) - TINYSYS to EMI (3-bit to 4-bit) - INFRA2 (3-bit to 4-bit) 4. Set SCP domain and ADSP domain - domain 3: SCP - domain 4: ADSP BUG=b:204347737 TEST=sanity test pass Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59746 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-06soc/intel/alderlake: Add support for ADL-N CPU TypeUsha P
Add Alder Lake-N case for adl_cpu_type and get_supported_lpm_mask. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: If2917ac356fd80f84bcaf70ed710d329e77f7a6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-12-06soc/intel/common: Refactor cpu_set_p_state_to_max_non_turbo_ratioSridhar Siricilla
The patch refectors cpu_set_p_state_to_max_non_turbo_ratio(). The function is updated to use cpu_get_max_non_turbo_ratio(). TEST=Build the code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: If73df17faaf7b870ae311460a868d52352683c0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06soc/intel/common: Add CPU related APIsSridahr Siricilla
The patch defines below APIs : cpu_is_hybrid_supported() : Check whether CPU is hybrid CPU or not. cpu_get_bus_frequency() : Get CPU's bus frequency in MHz cpu_get_max_non_turbo_ratio() : Get CPU's max non-turbo ratio cpu_get_cpu_type() : Get CPU type. The function must be called if executing CPU is hybrid. TEST=Verified the APIs on the Brya board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I680f43952ab4abce6e342206688ad32814970a91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.hTim Wawrzynczak
This enum is useful to have around for more than just the one file, so move it to a common header file, and while we're there, also add an option for UNKNOWN. TEST=boot test on brya0 Change-Id: I9ccf0ed9504dbf6c60e521a45ea4b916d3dcbeda Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-12-03soc/intel/adl: Add override skip_cse_sub_part_update() for alderlakeKrishna Prasad Bhat
Check the Alderlake CPU ID to determine if cse sub-paritition update is required or not. BUG=b:202143532 Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03soc/intel/common: Add support for CSE IOM/NPHY sub-parition updateKrishna Prasad Bhat
This patch adds the following support to coreboot 1. Kconfig to add IOM/NPHY in the COREBOOT/FW_MAIN_A/FW_MAIN_B partition of BIOS 2. Helper functions to support update. Pre-requisites to enable IOM/NPHY FW Update: 1. NPHY and IOM blobs have to be added to added COREBOOT, FW_MAIN_A and FW_MAIN_B through board configuration files. CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE: IOM blob Path SOC_INTEL_CSE_NPHY_CBFS_FILE: NPHY blob path 2. Enable CONFIG_CSE_SUB_PARTITION_UPDATE to enable CSE sub-partition NPHY/IOM update. coreboot follows below procedure to update NPHY and IOM: NPHY Update: 1. coreboot will navigate through the CSE region, identify the CSE’s NPHY FW version and BIOS NPHY version. 2. Compare both versions, if there is a difference, CSE will trigger an NPHY FW update. Otherwise, skips the NPHY FW update. IOM Update: 1. coreboot will navigate through the CSE region, identify CSE's IOM FW version and BIOS IOM version. 2. Compares both versions, if there is a difference, coreboot will trigger an IOM FW update.Otherwise, skip IOM FW update. Before coreboot triggers update of NPHY/IOM, BIOS sends SET BOOT PARTITION INFO(RO) to CSE and issues GLOBAL RESET commands if CSE boots from RW. coreboot updates CSE's NPHY and IOM sub-partition only if CSE boots from CSE RO Boot partition. Once CSE boots from RO, BIOS sends HMRFPO command to CSE, then triggers update of NPHY and IOM FW in the CSE Region(RO and RW). coreboot triggers NPHY/IOM update procedure in all ChromeOS boot modes(Normal and Recovery). BUG=b:202143532 BRANCH=None TEST=Build and verify CSE sub-partitions IOM and NPHY are getting updated with CBFS IOM and NPHY blobs. Verified TBT, type-C display, NVMe, SD card, WWAN, Wifi working after the update. Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03soc/intel/common: Add check before sending HMRFPO_ENABLE commandSridhar Siricilla
This patch adds a check to determine if the CSE's current operation mode is ME_HFS1_COM_SECOVER_MEI_MSG or not before sending HMRFPO_ENABLE command to CSE. If CSE is already in the ME_HFS1_COM_SECOVER_MEI_MSG, coreboot skips sending HMRFPO_ENABLE command to CSE to unlock the CSE RW partition. TEST=Verify sending HMRFPO_ENABLE command on Brya system. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I387ac7c7296ab06b9bb440d5d40c3286bf879d3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03soc/intel/common: Rename compare_cse_version() function nameSridhar Siricilla
The patch renames the compare_cse_version() function to the cse_compare_sub_part_version(). It makes the function generic so that it can be used to compare version of any CSE sub-partition like IOM, NPHY etc. TEST=Verified build for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I88a44a3c0ba2ad8a589602a35ea644dab535b287 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59689 Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03soc/intel/alderlake: Add support for ADL-N PCHUsha P
Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and use it to specify the correct amount of PCIe I/O. Document number 645550 indicates that Alder Lake-N has 12 PCH root ports and no CPU root ports. Document number 645548 indicates ADL-N has 5 clock sources and 5 clock request signals. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03soc/intel/alderlake: Add the CnviDdrRfim configurationRonak Kanabar
FSP v2422_01 introduced new FSPM UPD CnviDdrRfim. Add CnviDdrRfim config to control the CnviDdrRfim UPD from devicetree. Setting CnviDdrRfim to 1 enable CNVi DDR RFIM BUG=b:201724512 BRANCH=None TEST=Build and boot brya with debug FSP and verify CnviDdrRfim UPD value. Change-Id: Ia06c9ed77d78821fd4724046bae2f31c9d771518 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03soc/intel/alderlake: Add TDP to give correct VR configurationCurtis Chen
The VR configuration should be based on the different Soc SKU type. And we also have different SKU in the same SA PCI ID. Therefore, add TDP to recognize the correct SKU and give the correct power setting. BUG=b:202486131 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: I4d31e7afc76d9a8c772781671f92ec08f9d8713f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03soc/amd/cezanne: Enable secure countersKarthikeyan Ramasubramanian
Guybrush uses secure counters to protect against High Definition (HD) protected content rollback. These secure counters are hosted in TPM NVRAM. Enable secure counters so that they are defined in PSP verstage. BUG=b:205261728 TEST=Build and boot to OS in Guybrush. Ensure that the secure counters are defined successfully in TPM NVRAM. Change-Id: I6818c6f7905aa2eb815059e23c4f79437593f8ca Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-02soc/intel/alderlake: Add Kconfigs for all PCH typesAngel Pons
The Alder Lake code currently supports the PCH-M and PCH-P types, which have some differences (so far, only the amount of PCIe I/O). Mainboards can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which PCH type they use: select the option to choose PCH-M, do not select the option to choose PCH-P. While this works, it can be confusing once more PCH types are added. Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards have to explicitly choose a PCH type. Also, use this option to restrict the PCH-P defaults for PCH-dependent settings to avoid unintended reuse of the PCH-P defaults when adding a new PCH type. To make sure only one PCH type is selected, add some preprocessor in `bootblock.h` to provoke a build-time error if this requirement is not met. Kconfig doesn't seem to have a mechanism to describe sets of mutually-exclusive bool options that allows said options to be selected (a `choice` block doesn't allow its elements to be selected). Finally, adapt the ADL boards accordingly. Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-12-01soc/intel/common/pmc: Drop unnecessary pmc_ipc.c entrySubrata Banik
This patch drops unnecessary `pmc_ipc.c` from Makefile as this file is getting included upon CONFIG_PMC_IPC_ACPI_INTERFACE selection. Change-Id: Ie66f0833daf033ec16210221610508f9fbb1e6c7 Signed-off-by: Subrata Banik <subi.banik@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-30soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1Felix Held
Despite Stoneyridge being one only SoC in soc/amd that uses the first generation of the PSP mailblox interface, this code is common for all SoCs that use the first PSP mailbox interface generation, so move it to the common PSP generation 1 code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59701 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-30soc/amd/cezanne: add missing PM_ACPI_* bit definitionsFelix Held
This part was copied from Picasso but Cezanne has some more bits used so add the definitions now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icd128dca1ec30e7c70501c0e64482159be71cc7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-30soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defsFelix Held
Both SPI_ROM_BIOS_SEMAPHORE and SPI_ROM_EC_SEMAPHORE bits in the LPC_PCI_CONTROL are defined in the Stoneyridge BKDG #55072 Rev 3.04, Raven1 and Picasso PPR #55570 Rev 3.18, Raven2 PPR #55772 Rev 3.08 and Cezanne PPR #56569 Rev 3.03 which are all platforms that use this code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I855e640d020daf21c9f5b2f62a2ad0fd0274a575 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-30intel: cse_lite: Use cbfs_unverified_area APIJulius Werner
This patch replaces the use of the deprecated cbfs_locate_file_in_region() API with the new cbfs_unverified_area_map(). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If4855280d6d06cf1aa646fded916fd830b287b30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-29sc7280: Add support for USBRavi Kumar Bokka
Adding USB addressmap for sc7280. Use common USB driver for sc7280. BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Change-Id: Ib92b74c8035a8c0148a9aa48e7870b261b832a33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-29soc/qualcomm/common/usb: Add support for common USB driverSandeep Maheswaram
Add common USB driver for qualcomm soc sc7180 and sc7280. This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy. BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7180 and sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Change-Id: I1013ded22855286220cfa747cb25418070fe85a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-29soc/amd/common/block/lpc: use 32 bit accesses in lpc_enable_port80Felix Held
When using 32 bit PCI accesses in lpc_enable_port80, we can use the LPC_IO_OR_MEM_DECODE_ENABLE and DECODE_IO_PORT_ENABLE4 defines and don't need to re-define bits with offsets from the beginning of the third byte within this 32 bit register. This allows to drop the LPC_IO_OR_MEM_DEC_EN_HIGH register definition which points to LPC_IO_OR_MEM_DECODE_ENABLE + 2 and to drop the re-definitions of the bit re-definitions with a different offset. The code in lpc_enable_port80 was originally copied from sb/amd/agesa/ hudson/early_setup.c which might be sort-of a copy from what the AGESA reference code does. TEST=When commenting out SOC_AMD_COMMON_BLOCK_USE_ESPI in the Kconfig of Mandolin and selecting AMD_LPC_DEBUG_CARD, all POST codes still get shown on the POST code LED display when this patch is applied. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I001bb1c2ccf99e36d4fbd73d3bf96b78ddb87d67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-29soc/amd/common/block/lpc/lpc_util: drop lpc_enable_pci_port80Felix Held
This function is unused and none of the SoCs using this code has a physical PCI interface any more, so drop this function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia5c5a8ec29264a075fefe75038ef2a84684d6427 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-29src/cpu,soc/amd/common/block/cpu: Add preload_microcodeRaul E Rangel
This will enable preloading the microcode. By preloading the file, into cbfs_cache we reduce boot time. BUG=b:179699789 TEST=Boot guybrush with CL chain and see microcode preloading and a reduction of 1 ms. | 112 - started reading uCode | 1.041 | 1.204 Δ( 0.16, 0.01%) | | 113 - finished reading uCode | 1.365 | 0.011 Δ( -1.35, -0.10%) | Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If0c634c692c97769e71acd1175fc464dc592c356 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-29soc/amd/stoneyridge/psp: use PSP_MAILBOX_BAR defineFelix Held
PSP_MAILBOX_BAR is defined as PCI_BASE_ADDRESS_4, so use it instead of PCI_BASE_ADDRESS_4 in the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8658b674b9adea85dfc71d7036ccf3ae17464b58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-29soc/amd/common/block/psp/psp_def: drop PSPV2_STATUS_* definesFelix Held
PSPV2_STATUS_ERROR and PSPV2_STATUS_RECOVERY aren't used and the bit definitions are also wrong, so drop those defines. For the PSP mailbox interface version 2, struct pspv2_mbox is used to access the correct status bits. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8e2aadfde00e2f7b0f99b462b8e3d6954959a584 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-29soc/mediatek: move bustracker_init before watchdog resets againRex-BC Chen
The checking register will be cleared after EC resets, so we move bustracker dump from ramstage to bootblock, before triggering EC reset. TEST=bustracker shows status before watchdog resets BUG=b:207743045 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic18dc9742cd9f657a035a374e28371dfc5f04ac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-29soc/mediatek: Flush cache before triggering EC resetRex-BC Chen
There will be no log in cbmem if we trigger ec reset on bootblock stage. Therefore, call dcache_clean_all() before triggering ec reset to flush cache to store logs on cbmem. BUG=b:207743045 TEST=show logs on cbmem Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I1bd900beb4cc84f7121c5fb66907fa73b62517fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/59683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-29soc/intel/common: Include Alder Lake-N device IDsUsha P
Add Alder Lake-N specific CPU, System Agent, PCH (Alder Point aka ADP), IGD device IDs. Document Number: 619501, 645548 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I0974fc6ee2ca41d9525cc83155772f111c1fdf86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-11-29soc/intel/alderlake: Trigger cse_fw_sync before DRAM InitSridhar Siricilla
The patch enables cse_fw_sync() before DRAM initialization. cse_fw_sync() sends HECI commands in order to set CSE's boot partition and to trigger CSE firmware update. As part of CSE firmware update, coreboot sends HMRPFO_ENABLE HECI command. Since CSE supports the command after DRAM Initialization, cse_fw_sync() is called after DRAM initialization. Starting from CSE Litev16.0.15.1545, CSE support HMRFPO_ENABLE command before DRAM initialization too. So, cse_fw_sync() is called before DRAM initialization. BUG=b:175516533 TEST=Dependency with CSE Litev16.0.15.1545 integration Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55364 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-29cpu/x86: Rename X86_AMD_INIT_SIPI to X86_INIT_NEED_1_SIPISubrata Banik
This patch renames X86_AMD_INIT_SIPI Kconfig to leverage the same logic (to skip 2nd SIPI and reduce delay between INIT and SIPI while perform AP initialization) even on newer Intel platform. Change-Id: I7a4e6a8b1edc6e8ba43597259bd8b2de697e4e62 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56651 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-29soc/medaitek: add prompt string to config MTK_DFDRex-BC Chen
Add prompt string to allow selecting MTK_DFD manually. TEST=Select and enable MTK_DFD then successfully built firmware images. BUG=b:207450135 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ied711321efa592cf1bf7b318fe4d0aa155c15c70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26soc/mediatek/i2c: Return negative values on errorYu-Ping Wu
Following coreboot's convention, return negative error codes from platform_i2c_transfer(). BUG=none TEST=emerge-asurada coreboot BRANCH=none Change-Id: I955b9aae11e20d75fac414d15714330e364dad2f Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-26soc/medaitek/mt8186: fix wrong condition of RTC driversRex-BC Chen
We need to report error while rtc_xosc_write() returns false. TEST=error logs for RTC disappear BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I5fdf4de0383ef373dd45e8d8741aa861c9c4bdc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26mb/google/corsola: Raise little CPU frequencyRex-BC Chen
Raise little CPU to 2GHz at romstage. TEST=check little core cpu frequency is 2GHz BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If4c983d15beb2b588230f3db7416cb767b29978d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26mb/google/corsola: Add VPROC12/VSRAM_PROC12 to regulator interfaceRex-BC Chen
Add VPROC12/VSRAM_PROC12 to adjust power for raising little CPU frequency. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I59b4627220022a51a116716036a8ba0048039508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26soc/mediatek/mt8186: fix variable typeRex-BC Chen
The types of pwrap_read_field()'s return value and pwrap_write_field()'s `val` argument are u16, so correct the usage in MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ie05ab65ecd9b8ea1379ef74393285c4f5d2db8a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26soc/mediatek/mt8186: Add support for regulator VPROC12/VSRAM_PROC12Rex-BC Chen
To raise little CPU frequency, add support for VPROC12 and VSRAM_PROC12 of MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com> Change-Id: I718fdf36d34969a6e21ddc8c1ec6f525e0e20904 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26soc/mediatek: log watchdog statusRex-BC Chen
Reveal watchdog status value on bootblock stage. BUG=b:207646327 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I2c5ad222a41085616565dd5c10b0e967bb64ec63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-25soc/intel/alderlake: Add ADLP 4+4+2 power configurationsCurtis Chen
Map existing PCI_DEVICE_ID_INTEL_ADL_P_ID_1 to ADLP 4+4+2 45W SKU power related settings. Per doc#626774 ADL_MOW_WW46_2021, update PD optimization relaxation for ADL-P 482(28W) and 442(45W). BUG=b:193864533 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25soc/amd/*/data_fabric: use DF_ prefix for bit and shift definesFelix Held
Adding the DP_ prefix to the defines for MMIO_NP, MMIO_WE and MMIO_RE clarifies the scope of those definitions. For consistency also add this prefix to MMIO_DST_FABRIC_ID_SHIFT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3a509ccc071aa51a67552fb9e7195358a76fe4dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/*/include/data_fabric: make MMIO_NP definition SoC-specificFelix Held
On Picasso the MMIO_NP bit in the D18F0_MMIO_CTRL0 data fabric register is bit 12, but that has changed to bit 16 in Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I64c06b84e2c0737b259077e7932f418306638e19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/aoac: fix typo in FCH_AOAC_REF_CLK_OK_STATE definitionFelix Held
The bit is called REF_CLK_OK_STATE and not RST_CLK_OK_STATE, so change the name of the define to FCH_AOAC_REF_CLK_OK_STATE. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iae26db94d83ebb2cb799f6d3e0bec37c8e849219 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: add missing de-glitching definesFelix Held
There were only definitions for removing low, high or both glitches, but not to not remove glitches, so add this too for completeness. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I650f7754546935539339c02bb6a94bb3f855d4ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/59631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: rework de-glitching definesFelix Held
I found the name of the DEB_GLITCH_NONE definition a bit misleading, so change it to DEB_GLITCH_REMOVE which should clarify what this will do. The description for this value in the PPR/BKDG is "Remove glitch". This also puts the define in line with GPIO_DEB_REMOVE_GLITCH which is the only place where DEB_GLITCH_NONE/DEB_GLITCH_REMOVE is used. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I59648710e0ff28c2026e1b2cc7e433cafb2f2807 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: use tabs for indentationFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibf7482d20c6d27b2314ec8a31c349eb90c8a8feb Reviewed-on: https://review.coreboot.org/c/coreboot/+/59629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25commonlib/cbmem_id.h: Fix typo in macro nameAngel Pons
Rename `CMBMEM_ID_ACPI_HEST` to `CBMEM_ID_ACPI_HEST`. Change-Id: I3e680244c9573f566b51298462c324e062ab4657 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59616 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-25soc/amd/common/block/gpio: drop unused gpio_get_addressFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5b47324af368f81288e9e9be65fe0f1ae2fa3697 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/acpi/gpio_bank_lib: drop unused methodsFelix Held
Those methods were only in the non-common Stoneyridge GPIO ACPI code that got dropped, so drop those unused methods too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I519d88ffa1d5d4823cce4876ecf59b9019f676e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: drop unused GPIO_PIN_IN/OUTFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idf00879701b223ecaca74aef2a51a1b86d2c6ce3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_ACPI_GPIOFelix Held
Stoneyridge uses the same GPIO bank peripheral as Picasso and Cezanne so we can use the common AMD SoC GPIO ACPI code. TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifa1fc923cd5b779765917b171b5a7222f18a176a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: de-duplicate pin status bit defsFelix Held
De-duplicate the definitions for the pin status bit and use this new definition in both the C and the ACPI code. TEST=Timeless build results in identical image for amd/mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8b0fe7dbec5dac176cdfa9690862433f202fb552 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: drop duplicate wake bit defsFelix Held
The GPIO_WAKE_* definitions are the ones that are used in the code, so drop the unused GPIO_*_WAKE_EN definitions for the same bits. Also move the GPIO_WAKE_* definitions to the place the GPIO_*_WAKE_EN ones were before this patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I622673cc72107908b525a65212061062f32e13dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: use bit definitions for masksFelix Held
All bits covered by the bit masks GPIO_INT_ENABLE_MASK, GPIO_PULL_MASK, GPIO_STATUS_MASK and GPIO_WAKE_MASK already have definitions in the code so use those instead of magic numbers. TEST=Timeless build results in identical image for amd/mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0bc9e1cecf2f063b42de3f8875fee421dd256648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: remove unneeded line breakFelix Held
The definitions of GPIO_INT_ENABLE_STATUS_DELIVERY and GPIO_TIMEBASE_62440uS fit into 96 characters, so remove the unneeded line breaks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b9c3885259b9acf0539eed14e23fbbb0deccea7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: drop 8k pullup defineFelix Held
The corresponding bit is marked as reserved in the following versions of the documentation for all SoCs using this code: Mullins: BKDG #52740 Rev 3.05 Stoneyridge: BKDG #55072 Rev 3.04 Raven1, Picasso: PPR #55570 Rev 3.16 & 3.18 Raven2: PPR #55772 Rev 3.08 Cezanne: PPR #56569 Rev 3.03 The old Rev 3.14 of the Picasso PPR #55570 had the bit 19 defined as PullUpSel, but this is no longer the case in newer versions. It is unclear if this got de-featured or if it was never present in the silicon. To be consistent with the current documentation, drop this define. This patch also change the definition of GPIO_PULL_MASK to only cover the bits used for the feature. The Cezanne PPR #56569 Rev 3.03 states a default value of 0 for this bit after reset, so the resulting values in the register aren't expected change. The other PPRs/BKDGs don't specify a reset value for this bit, but it's likely safe to assume that all SoCs that use the new GPIO interface use the same GPIO building block. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaf2d4eec7a13e558c75d7edea343b876909a5b33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/intel/adl: Modify SOC_INTEL_ALDERLAKE_DEBUG_CONSENT default valueKane Chen
On ADL, we actually use debug consent 2 for soc debug by DBC Change-Id: Ie6fbf3cdcf5dcd1a11a895ea83f55157a2ac4eb9 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25soc/intel/elkhartlake: Update SA DIDs TableRick Lee
Update SA table as per latest EDS (Doc no: 601458). Add extra SKUs accordingly. Signed-off-by: Rick Lee <rick.lee@intel.com> Change-Id: Ia2bb9e54456dbea634c2b8e192f9fe813b9e6706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
2021-11-25soc/intel/graphics/Kconfig: Guard optionsArthur Heymans
Change-Id: I3c252e31867e4560fb5aaf12273288f4ff18ae3d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-11-25soc/intel/common/thermal: Refactor thermal block to improve reusabilitySubrata Banik
This patch moves common thermal API between chipsets with thermal device as PCI device and thermal device behind PMC into common file (thermal_common.c). Introduce CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV to let SoC Kconfig to select as applicable for underlying chipset. +------------------------------------------------------+--------------+ | Thermal Kconfig | SoC | +------------------------------------------------------+--------------+ | CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV | SKL/KBL, CNL | | | till ICL | +------------------------------------------------------+--------------+ | CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC | TGL onwards | | | ICL | +------------------------------------------------------+--------------+ Either of these two Kconfig internally selects CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL to use common thermal APIs. BUG=b:193774296 TEST=Able to build and boot hatch and adlrvp platform. Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-24soc/amd/common/block/include/acpi: fix reference to main acpi includeFelix Held
commit e0844636aca974449c7257e846ec816db683d0b9 (acpi: Move ACPI table support out of arch/x86 (2/5)) moved the main acpi header file from arch/x86/include/acpi/acpi.h to include/acpi/acpi.h, so change the comment in here to point to the current location. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5fddd1cd5eefd83816b1c966b5c7edf53eb2486d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-24soc/amd/common/block/include/gpio_defs: add GPIO IRQ status registersFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I585691038690f1d6855ab09f1ca5791a18cfdbfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/59590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-24soc/amd/common/block/include/gpio_defs: use lower case in hex numbersFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icb1c7b243f655225347ba2a78c80e6e8653e8cda Reviewed-on: https://review.coreboot.org/c/coreboot/+/59589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-24soc/amd/picasso,stoneyridge/acpi: use define for RTC_DATE_ALARMFelix Held
Cezanne already uses a define for this and it's better to define and use constants instead of magic values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifa4b3b3cdb161670128b284a3396fc5a85545608 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-24soc/intel/elkhartlake: Disable Intel PSE by defaultLean Sheng Tan
Disable PSE loading by default. If left enabled (current default), the EHL coreboot will end up in endless restart loop, due to FSP unable to locate PSE FW image and trigger global reset. However disabling this flag (PchPseEnable) will cause the coreboot to trigger a single reset due to CSE signal (HECI: CSE does not meet required prerequisites). The reason behind this is that FSP need to perform static disabling (power gate) to fully shut down PSE HW, and to do this will need to global reset entire system including CSE. Then PMC will power gate PSE from the start. To avoid this behavior, the best way to disable PSE is to disable via IFWI FIT softstrap (For specific detail can refer to Intel EHL coreboot MR2 release notes). With this, PMC will power gate PSE from the first cold boot and system will boot happily without single reset behavior. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Iccc0ab1c2e4ebb53013795933eb88262f70f456f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-11-23soc/intel/alderlake: remove tmp bar assignment for cpu crashlogKane Chen
When the cpu_cl_discovery is called, coreboot actually assigns a BAR to cpu crashlog pci device. Hence, we don't need to assign a tmp BAR for cpu crashlog pci device BUG=b:195327879 TEST=Found BERT table is created and the tcss function is ok in depthcharge Change-Id: Ib7e6772be51ec4f26ef31fed6cb2bddef8ffc6be Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22soc/amd/psp_verstage: Init TPM on S0i3 resumeRob Barnes
Add option to initialize the TPM in PSP verstage during s0i3 resume. This is needed if the TPM is reset in s0i3. FSDL is handling restoring everything else, so only the minimum TPM initialization is done. Move aoac and i2c init before psp_verstrage_s0i3_resume becasue i2c needs to be ready before attempting to restore tpm. BUG=b:200578885,b:197965075 TEST=Multiple cycles of S0i3 suspend resume. ~66ms of additional delay. BRANCH=None Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-22soc/intel/cannonlake: Fix PEG1 _PRT generationArthur Heymans
Some weird things happen inside FSP and the routing is not correctly applied, with PIN D being used but lacking a proper routing in ACPI. To work around this issue generate _PRT for all 4 INT pins. Change-Id: I5be6e4514f8c6a47bb887d9f9b95181c9f426a51 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22soc/intel: Allow enable/disable ME via CMOSSean Rhodes
Add .enable method that will set the CSME state. The state is based on the new CMOS option me_state, with values of 0 and 1. The method is very stable when switching between different firmware platforms. This method should not be used in combination with USE_ME_CLEANER. State 1 will result in: ME: Current Working State : 4 ME: Current Operation State : 1 ME: Current Operation Mode : 3 ME: Error Code : 2 State 0 will result in: ME: Current Working State : 5 ME: Current Operation State : 1 ME: Current Operation Mode : 0 ME: Error Code : 0 Tested on: KBL-R: i7-8550u CML: i3-10110u, i7-10710u TGL: i3-1110G4, i7-1165G7 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22soc/intel/{adl,ehl,jsl,tgl}: Remove unused header `thermal.h`Subrata Banik
This patch removes unused header inclusion as <intelblocks/thermal.h> from several SoC finalize.c files. Change-Id: Ic9ac0ffb352686af22cc9d11b61f904238eef278 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-11-20soc/intel/alderlake: Hook up common code for thermal configurationSubrata Banik
Thermal configuration registers are now located behind PMC PWRMBASE for Alder Lake Point PCH. Hence, ADL SoC to select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC to let thermal low threshold is being set as per mainboard provided `pch_thermal_trip`. Note: These thermal configuration registers are RW/O hence, setting those early prior to FSP-S helps coreboot to set the desired low thermal threshold for the platform. BUG=b:193774296 TEST=Dump thermal configuration registers PWRMBASE+0x150c etc. prior to FSP-S shows that registers are now programmed based on 'pch_thermal_trip' and lock register BIT31 is set. Change-Id: I0f972f47845c123f4f74fd75091c9703d54db796 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59271 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-20soc/intel/alderlake: Set `pch_thermal_trip` for Dynamic Thermal ShutdownSubrata Banik
Set low maximum temp threshold value used for dynamic thermal sensor shutdown consideration. BUG=b:193774296 Change-Id: I7ee199c19a9d926a4135eeef3b3b481fbff74a79 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-11-20soc/intel/common/thermal: Allow thermal configuration over PMCSubrata Banik
Thermal configuration has evolved over PCH generations where latest PCH has provided an option to allow thermal configuration using PMC PWRMBASE registers. This patch adds an option for impacted SoC to select the Kconfig for allowing thermal configuration using PMC PCH MMIO space. BUG=b:193774296 TEST=Able to build and boot hatch and adlrvp platform. Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59209 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 23:57:43 +0000