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2016-06-30soc/apollolake: Expose a function to read pmc barShaunak Saha
This patch exposes a function to read pmc bar. PMC bar is read in function read_pmc_mmio_bar which is defined static in file pmutil.c. This patch exposes that functionality to call it from other files. BUG=chrome-os-partner:53438 TEST= Read the PMC bar value properly from outside pmutil file. Change-Id: I26ee13e6ab95d3a8991c7f8ea4b3856ceb015d10 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15460 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-30fsp_broadwell_de: Enable Super I/O address range decodeWerner Zeh
If there is an external 16550 like UART, one needs to enable the appropriate address ranges before console_init() is called so that the init sequence can reach the external UART. Otherwise the UART will only start working in ramstage and will produce unreadable characters in romstage due to the lack of initialization. Tested-on: Siemens MC_BDX1 Change-Id: Iafc5b5b6df14916c5ed778928521d4a8f539cf46 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15495 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-30soc/intel/apollolake: fix space indention in pm.hAaron Durbin
More spaces missed in review. Change-Id: I842da05ca6ad4f2c13d2d42433e41da57ccf7f96 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15500 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-29soc/intel/{common,skylake}: provide common NHLT SoC supportAaron Durbin
The nhlt_soc_serialize() and nhlt_soc_serialize_oem_overrides() functions should be able to be leveraged on all Intel SoCs which support NHLT. Therefore provide that functionality and make skylake use it. Change-Id: Ib5535cc874f2680ec22554cecaf97b09753cacd0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15490 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-29soc/intel/skylake: refactor nhlt supportAaron Durbin
Utilize the new NHLT helper functions by driving the NHLT endpoints through data descriptors. Change-Id: I80838214d3615b83d4939ec2d96a4fd7050d5920 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15488 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-29soc/intel/skylake: fix nhlt/ssm4567.c indentionAaron Durbin
Whitespace fix for improper space usage for indention. Change-Id: Ia6470bf152c57786d2d7f3d35bbf0609a2ee3ba2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15487 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-29soc/intel/apollolake: Change PCI macros to match SkylakeAndrey Petrov
Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-29soc/intel/apollolake: Update Upd header files for FSP Label 143_10Brandon Breitenstein
New UPDs added to header files as well as many comment fixes. Memory infor is now defined in FspmUpd.h and added ability to skip CSE RBP for coreboot. Removes some UPDs that are no longer available from source. BUG=chrome-os-partner:54677 BRANCH=none TEST=built and tested with FSP 143_10 version Change-Id: I7e1f531ebbe343b45151a265ac715ae74aeffcad Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/15459 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-29intel romstage: Use run_ramstage()Kyösti Mälkki
Change-Id: I22a33e6027a4e807f7157a0dfafbd6377bc1285d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15461 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-28soc/intel/apollolake: Add NHLT table region to ACPI global nvsSaurabh Satija
Add address and length of NHLT table in ACPI. Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Reviewed-on: https://review.coreboot.org/15025 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-28apollolake: Add ACPI device for audio controllerSaurabh Satija
Add the audio controller device to ACPI and define the _DSM handler to return the address of the NHLT table, if set in NVS. Change-Id: I619dbfb562b94255e42a3e5d5a3926c28b14db3e Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Reviewed-on: https://review.coreboot.org/15026 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2016-06-28tegra124: Actually align the framebuffer's bytes-per-line to 32Paul Kocialkowski
The previous change with that intent aligned the framebuffer's bytes-per-line to 64 instead of 32: commit 8957dd6b52919ed634aa502dfd5b6316a6e6e055 Author: Paul Kocialkowski <contact@paulk.fr> Date: Sun May 1 18:38:04 2016 +0200 tegra124: Align the framebuffer's bytes-per-line to 32 Change-Id: I88bba2ff355a51d42cab6a869ec1e9c534160b9c Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14816 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-06-28soc/apollolake: Populate fields in FADT to enable\disable SCIHannah Williams
This will allow kernel to trigger a APM SMI to enable\disable SCI Change-Id: I1be79b7a3082c23fbaf204eff55360c46458e325 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15347 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-27soc/intel/apollolake: add code to disable unused deviceJagadish Krishnamoorthy
Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-27intel/apollolake: Set sleep type to S5 on vboot reboot requestFurquan Shaikh
Add support for vboot_platform_prepare_reboot which is called whenever vboot requests reboot of the platform. SLP_TYPE needs to be set to S5 in such conditions since the platform would no longer be in a resuming state after reset. Change-Id: I01392bfda90c9274cd52c1004555d250b1d539b7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15340 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24rk3399: clean up sdram controller initialization codeVadim Bendebury
This is a purely cosmetic change replacing some of the more prominent copy and paste sections of the code with compressed versions of the same. BRANCH=none BUG=none TEST=with the rest of the patches applied stressapptest still runs for an hour on both Kevin and Gru. Change-Id: I492e1898e312473d07d9e5eceb3e3e10b48ee35f Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: eb8043f96457d090dbbee57097bc1d685e7d32d2 Original-Change-Id: I362e0e261209ae4d4890ecb0e08bb1956c172ffd Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353774 Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/15308 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24region: Add writeat and eraseat supportAntonello Dettori
Implement writeat and eraseat support into the region_device_ops struct. Change-Id: Iac2cf32e523d2f19ee9e5feefe1fba8c68982f3d Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15318 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24soc/apollolake: Clear SLP_TYP in PM1_CNTHannah Williams
Change-Id: Id49319ec6b52648b03eaeddfdd1580dd82110fb9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15336 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24soc/intel/apollolake: Add handling of global reset in FspNotify stageAndrey Petrov
Call basic FSP reset handling in FspNotify stage. Handling of reset requests for other stages need to be implemented as well. BUG=chrome-os-partner:54149 BRANCH=none TEST=with FSP that returns reset codes, do cold boot, check that reboot sequence occurs properly. Change-Id: I55542aa37e60edb17ca24ac358b61df72679b83e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15280 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24soc/intel/apollolake: Implement global reset handlingAndrey Petrov
Global reset enable bit is not cleared on reset. Therefore, clear the bit early. Lock down 0xcf9 so that payload/OS can't issue global reset. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I3ddf6dd82429b725c818bcd96e163d2ca0acd308 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15199 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24soc/intel/apollolake: Move PMC BAR setup to bootblockAndrey Petrov
Some features of PMC needs to be accessed before romstage. Hence, move PMC BARs setup into bootblock. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I14493498314ef1a4ce383e192edccf65fed2d2cb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15332 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24soc/intel/apollolake: Add utility functions for global resetAndrey Petrov
Apollolake defines Global Reset where Host, TXE and PMC are reset. During boot we may need to trigger a global reset as part of platform initialization (or for error handling). Add functions to trigger global reset, enable/disable it and lock global reset bit. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I84296cd1560a0740f33ef6b488f15f99d397998d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15198 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24Revert "intel/apollolake: Use custom reset calls"Andrey Petrov
Looks like we need to do real cold reset in some FSP flows, so reverting this. This reverts commit 6f762171de4b8514fddd430052cbf24524e09e5d. Change-Id: Ie948d264c4e2572dab26fdb9462905247a168177 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15331 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24soc/intel/apollolake: Include _PTS, _WAK and _SWSHannah Williams
Change-Id: I3400611095978421c7b35a7ea9c68b8571942ae9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15138 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-23intel/apollolake: Enable prefetching and caching for BIOS readsFurquan Shaikh
Change-Id: I6afcc17ec8511d3fd4c1ac3b15d523d9b6752120 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15321 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23rockchip/rk3399: fix sdram training issueLin Huang
After write leveling for all ranks, check the PHY_CLK_WRDQS_SLAVE_DELAY result, if the two ranks in one slice both meet (0x200-PHY_CLK_WRDQS_SLAVE_DELAY < 0x20) or (0x200-PHY_CLK_WRDQS_SLAVE > 0x1E0), enable PHY_WRLVL_EARLY_FORCE_ZERO for this slice, and trigger write leveling again. BRANCH=none BUG=chrome-os-partner:54144 TEST=run "stressapptest -M 1024 -s 1000" and pass Change-Id: I1a0e4e888eb62b5fae5b5e5437a385e8660a246d Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 717cbac97b2045f2934e99859ce405aa3637b1c4 Original-Change-Id: Ic0d7c59404e870a7108ed64bbf3215fcc2d0973e Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351825 Reviewed-on: https://review.coreboot.org/15300 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23rockchip/rk3399: Clean up voltage rail settingsLin Huang
The CENTER LOGIC should always be 0.9V and can not be adjusted, so use duty_ns = 2860 to correct CENTER LOGIC to 0.9V. And now DDR seems to run stable at 800MHz on the gru board. BRANCH=none BUG=chrome-os-partner:54144, chrome-os-partner:53208 TEST=run "stressapptest -M 1024 -s 1000" and pass Change-Id: Ia900e248c10ddd0ab630446a324cc0446c0fa49b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: f4fb1cefb59ac4099cef8b32a68ed9222e708478 Original-Change-Id: I2238da6c17908d09bc284b321d796901317ed9ef Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/352772 Reviewed-on: https://review.coreboot.org/15297 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23rk3399: add definition for SP0 iomuxVadim Bendebury
This register is described in the TRM in section called GRF_GPIO3D_IOMUX. Added definitions allow to configure the SPI0 interface. BRANCH=none BUG=chrome-os-partner:50645, chrome-os-partner:51537 TEST=with the rest of the patches applied it is possible to communicate over SPI0 Change-Id: Ieee3fcae6095020042b02673c7d863f398ed2eb4 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 8f155e3b47c9f44ad4e5a2513916572e7d5ec0ab Original-Change-Id: Iea92971b0520dc4549cd0fd263dcb2098f80f6d6 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349851 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/15295 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-22intel/apollolake: Add API for get_bios_size and use itFurquan Shaikh
get_bios_size returns the value of bios_size. Use this function to calculate bios_size for caching in bootblock. BUG=chrome-os-partner:54563 Change-Id: I2e592b1c52138bd4623ad2acd05c744224a8e50b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15292 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-22soc/intel/common/acpi: Add _PTS, _WAK methodsHannah Williams
Change-Id: I72f894fd14bf0e333d9fda970397a3c82de598c3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15121 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
Without RELOCATABLE_RAMSTAGE have WB cache large enough to cover the greatest ramstage needs, as there is no benefit of trying to accurately match the actual need. Choose this to be bottom 16MiB. With RELOCATABLE_RAMSTAGE write-back cache of low ram is only useful for bottom 1MiB of RAM as a small part of this gets used during SMP initialisation before proper MTRR setup. Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15249 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21rockchip: gpio: add macro so we can get gpio numberLin Huang
sometimes we need gpio number, so add this macro so we can get the gpio number if we need. BRANCH=None BUG=chrome-os-partner:51924 TEST=Build gru Change-Id: I0c8c6cc0643a66e9ae1f21b02c7364c641b9805d Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: Original-Change-Id: I98e8cf15543179904295a86e9f720c2d7c8b443a Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/349701 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Tested-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15117 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-21intel/apollolake: Calculate BIOS mmap at runtimeFurquan Shaikh
Instead of hard-coding the BIOS region start and end addresses, read BIOS_BFPREG to determine the base and limit for the mapped BIOS region. BUG=chrome-os-partner:54563 Change-Id: Iddd3d4cc945f09e8f147e293bb9144471a6a220d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15269 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-21intel/apollolake: Add helper routine for spi reg readFurquan Shaikh
BUG=chrome-os-partner:54563 Change-Id: I56bc6b5292aec676103a436048abee8577edd961 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15268 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21intel/apollolake: Rename _spi_reg_read/write to _spi_ctrlr_read/writeFurquan Shaikh
This makes it clearer that the read/write operations are being performed on the host controllers registers. Change-Id: Id63d778a4a03c461d97e535c34b85ada3ae469de Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15281 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21commonlib/region: Rename XLATE region device init macroFurquan Shaikh
This makes the name consistent with other region device init macros. Change-Id: I248894ba6c85326b615dcb71e8f498bc8be50911 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15277 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21intel/apollolake/spi: Add support for reading status regFurquan Shaikh
spi_read_status reads the status register using hardware sequencing and returns 0 on success and -1 on error. Use spi_read_status to return appropriate value for get_sw_write_protect. BUG=chrome-os-partner:54283 Change-Id: I7650b5c0ab05a8429c2b291f00d4672446d86e03 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15266 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21intel/apollolake: Disable setting of EISS bit in FSPFurquan Shaikh
chrome-os-partner:54589 Change-Id: I5bdd417ed2f7ec013aeb8a0d4a9de57b1ad564a1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15276 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21intel/skylake: Run spi_init as early as possible in ramstageFurquan Shaikh
spi_init should be run early enough in ramstage so that any init calls (e.g. mainboard_ec_init) that write on flash have right permissions set. Change-Id: I9cd3dc723387757951acd40449d4a41986836d2a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15235 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-21intel/apollolake: Enable SPI properly in bootblock and ramstageFurquan Shaikh
Bootblock: - Temporary BAR needs to be assigned for SPI device until PCI enumeration is done by ramstage which allocates a new BAR. - Call spi_init to allow bootblock/verstage to write/erase on flash. Ramstage: - spi_init needs to run in ramstage to allow write protect to be disabled for eventlog and NVRAM updates. This needs to be done pretty early so that any init calls(e.g. mainboard_ec_init) writing to flash work properly. Verified with this change that there are no more flash write/erase errors for ELOG/NVRAM. BUG=chrome-os-partner:54283 Change-Id: Iff840e055548485e6521889fcf264a10fb5d9491 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15209 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Tested-by: build bot (Jenkins)
2016-06-21lpss_i2c: Set SDA hold and support custom speed configDuncan Laurie
This I2C controller has separate registers for different speeds to set specific timing for SCL high and low times, and then a single register to configure the SDA hold time. For the most part these values can be generated based on the freq of the controller clock, which is SOC-specific. The existing driver was generating SCL HCNT/LCNT values, but not the SDA hold time so that is added. Additionally a board may need custom values as the exact timing can depend on trace lengths and the number of devices on the I2C bus. This is a two-part customizaton, the first is to set the values for desired speed for use within firmware, and the second is to provide those values in ACPI for the OS driver to consume. And finally, recent upstream changes to the designware i2c driver in the Linux kernel now support passing custom timing values for high speed and fast-plus speed, so these are now supported as well. Since these custom speed configs will come from devicetree a macro is added to simplify the description: register "i2c[4].speed_config" = "{ LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30), LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30), LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30), LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30), }" Which will result in the following speed config in \_SB.PCI0.I2C4: Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) Name (FPCN, Package () { 52, 120, 30 }) Name (HSCN, Package () { 38, 90, 30 }) Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15163 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21soc/intel/apollolake: make gpo.h ACPI compatibleFreddy Paul
BUG=None TEST=Build with <soc/gpio.h> included in mainboard.asl Change-Id: Id6fdc50d09c014f930fdfd5c2fde0df827ad5181 Signed-off-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://review.coreboot.org/15272 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-20soc/apollolake: Include PCI _OSC methodHannah Williams
Change-Id: I2545fc184ebfaa006a75783bf3d55f009066eed3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15110 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-20soc/intel/common: Add _OSC methodHannah Williams
Not masking any bits in Operating System Capabilities, which means we support all the capabilities that OS passed in Arg3 Change-Id: Ib87915e18e305db41b52891ac5430201dda64bb5 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15021 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-19intel/broadwell: Remove old USBDEBUG backup store in CARKyösti Mälkki
Required EHCI state is maintained as a CAR_GLOBAL to have it properly migrated. Change-Id: I8df413bec6faae4952670710c8ac804e0331c966 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15236 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-18intel cache_as_ram: Fix typo in commentKyösti Mälkki
Change-Id: I2539e490e160e01cab2ad8d2086d2f242a88c640 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15223 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-17Fix some cbmem.h includesKyösti Mälkki
Change-Id: I36056af9f2313eff835be805c8479e81d0b742bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15196 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-15intel/apollolake: Correct the offsets in gnvsFurquan Shaikh
Offsets start from 0 instead of 1. Fix this in the gnvs definitions. BUG=chrome-os-partner:54342 Change-Id: Id6766a8766ef430d19ffcb801bfab43d38de37db Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15180 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-15intel/apollolake: Add CBMEM console to GNVSFurquan Shaikh
CBMEM console stores all the console logs in CBMEM. Address of this location in CBMEM where console logs are stored needs to be passed up to OS using GNVS. 1. Add CBMC to GNVS fields in globalnvs.asl 2. Add cbmc member to global_nvs_t structure in nvs.h 3. Initialize gnvs->cbmc to address of cbmem console BUG=chrome-os-partner:54342 Change-Id: Idcd4573e626fa433c1623bdcbe29921de64539b2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15177 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-12soc/intel/quark: Add C bootblockLee Leahy
Add a bootblock which builds with C_ENVIRONMENT_BOOTBLOCK selected. This is the first piece in supporting FSP 2.0. Move esraminit from romstage into the bootblock. Replace cache_as_ram with car_stage_entry.S and code in romstage.c TEST=Build and run on Galileo Gen2 Change-Id: I14d2af2adb6e75d4bff1ebfb863196df04d07daf Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15132 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-12bootblock: Declare common bootblock_pre_c_entry routineLee Leahy
Enable uses of a common bootblock_pre_c_entry routine. Pass in TSC value as a uint64_t value. TEST=Build for amenia and Galileo Gen2 Change-Id: I8be2e079ababb2cf1f9b7e6293f93e7c778761a1 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15124 Tested-by: build bot (Jenkins) Reviewed-by: Lee Leahy <lpleahyjr@gmail.com>
2016-06-12soc/intel/common: don't infinitely recurse in busmaster_disable_on_bus()Aaron Durbin
If a bridge has the primary bus equal to the secondary bus the busmaster_disable_on_bus() will infinitely call itself. Avoid the inifinite recursion by checking current bus number against the secondary bus number. BUG=chrome-os-partner:54262 TEST=Ran on reef. Able to actually get the chipset to assert SLP_Sx signals which means no more infinite recursion. Change-Id: I52b21fbba24e6a652ea8f9f87f5f49f60109c8f2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15157 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-12soc/intel/apollolake: save GNVS pointer to SMM handlerAaron Durbin
Like other boards there will likely be information needed from GNVS in the SMM handler. Therefore, it's important that the point is stashed accordingly. BUG=chrome-os-partner:54275 TEST=Noted GNVS messages from SMM console on reef. Change-Id: If12b69731330a1e0af7f8fe880635e5ffd02d715 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15152 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12soc/intel/apollolake: allow DEBUG_SMI to workAaron Durbin
The UART support is needed in SMM in order for DEBUG_SMI to function. BUG=chrome-os-partner:54262 TEST=Ran on reef with DEBUG_SMI enabled. Can observed SMI messages. Change-Id: Ibd6b12e27d5776046b400adf72f24133b9e54af8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15151 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12soc/intel/apollolake: provide fake PM1 SMI status bitAaron Durbin
It appears that PM1 is not wired up to the SMI status register, but it does definitely cause SMIs to trigger. Therefore, provide a fake PM1 status bit by checking the power button status when SMI status is indicating no status as well as the PM1 control indicating that SCI mode is not enabled. BUG=chrome-os-partner:54262 TEST=Smashed power button on reef to cause SMI in firmware. No longer loops infinitely with constant SMIs firing. Change-Id: I9aa1b5f79b651cbc19a2d3353d9ef65429386889 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15155 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12soc/intel/apollolake: add SMI status bit definitons and use themAaron Durbin
Provide the bit definitions for the SMI status register. Also, utilize them which means deleting some of the handlers that can't exist because there are no status bits. BUG=chrome-os-partner:54262 Change-Id: I389c7cb3cad01ba0eca52a337ffee352a2010bfa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15154 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-12intel/apollolake: Use custom reset callsFurquan Shaikh
Due to USB LDO issue in current steppings, cold reboot needs to be temporarily disabled. Thus, hard_reset call should be the same as soft_reset. Once future steppings are available INTEL_COMMON_RESET can be enabled again. Change-Id: If0ec56db3864d500acc93d2b363a78a6cd7632da Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15143 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-12rockchip: rk3399: pass board specific message to BL31Lin Huang
Sometimes we need to pass board specific messages to BL31, so that BL31 can do board specific operation based on common code. BRANCH=None BUG=chrome-os-partner:51924 TEST=Build gru Change-Id: I096878699c6e6933debdf2fb3423734f538691ae Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: af83e1b Original-Change-Id: Ib7585ce7d3bf01d3ce53b388bf9bd60f3b65f5f1 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349700 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15116 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12mt8173: dram: Add more sample points to improve dram timing marginPH Hsu
BRANCH=none BUG=chrome-os-partner:52959 TEST=verified on elm-EVT SKU1/SKU2, Oak-rev5 2GB/4GB models. Change-Id: I228c629d9a3d6cd8fc5c4e8ba24cc52d5283b4e6 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3c19e7d Original-Change-Id: I22356aa8d196c4c126742cfc7e85cc693acd9b39 Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/347716 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15115 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12Kconfig: Set VBOOT_OPROM_MATTERS for relevant non-x86 devicesJulius Werner
The VBOOT_OPROM_MATTERS configuration option signals to vboot that the board can skip display initialization in the normal boot path. It's name is a left-over from a time when this could only happen by avoiding loading the VGA option ROM on x86 devices. Now we have other boards that can skip their native display initialization paths too, and the effect to vboot is the same. (Really, we should rename oprom_matters and oprom_loaded to display_skippable and display_initialized or something, but I don't think that's worth the amount of repositories this would need to touch.) The only effect this still has in today's vboot is to reboot and explicitly request display initialization for EC software sync on VBOOT_EC_SLOW_UPDATE devices (which we haven't had yet on ARM). Still, the vboot flag just declares the capability (for skipping display init), and it should be set correctly regardless of whether that actually makes a difference on a given platform (right now). This patch updates all boards/SoCs that have a conditional path based on display_init_required() accordingly. BRANCH=None BUG=chrome-os-partner:51145 TEST=Booted Oak, confirmed that there's no notable boot time impact. Change-Id: Ic7c77dbd8356d67af7aee54e7869f9ac35241b99 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 9c242f7 Original-Change-Id: I75e5cdda2ba2d111ea50ed2c7cdf94322679f1cd Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/348786 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15113 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12rockchip: gru: Add USB DRD DWC3 controller supportLiangfeng Wu
This patch adds code to initialize the two DWC3 USB host controllers, and uses them to initialize USB3.0 on the gru rk3399 board. BRANCH=none BUG=chrome-os-partner:52684 TEST=boot from USB3.0 on gru/kevin rk3399 platform Change-Id: If6a6e56f3a7c7ce8e8b098634cfc2f250a91810d Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 0306a9e Original-Change-Id: I796fa1133510876f75873d134ea752e1b52e40a8 Original-Signed-off-by: Liangfeng Wu <wulf@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347524 Original-Commit-Ready: Brian Norris <briannorris@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15112 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-10Revert "soc/intel/apollolake: Do not use StackBase FSP-M parameter"Brandon Breitenstein
This reverts commit 5ede3d8ccebde6f26c6b24f6458e57d99d5f3957. No longer needed due to FSP being updated, with the 139_40 release, to accept StackBase field BUG=chrome-os-partner:52784 BRANCH=none TEST=built and booted with FSP 139_40 Change-Id: Ic832d8dc4ca87631f5fef80d4d41558d9a72630a Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/15068 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-10soc/intel/apollolake: FSP Header file update for FSP 139_40Brandon Breitenstein
FSP 2.0 spec has updated the signatures for the FSPM and FSPS blobs with the 139_40 release. In order to successfully pass through memory/silicon init the header files must be updated to the latest versions BUG=chrome-os-partner:52784 BRANCH=none TEST=built and booted Change-Id: Ib60d0d9afa4ee29dff26177826ba59db81b630e8 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/15066 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-09soc/intel/apollolake: Update FSP header filesBora Guvendik
Update autogenerated FSP 2.0 generic header files based on FSP release 136_30. Changes were made to avoid duplicating some of the structs for every SoC. BUG=chrome-os-partner:50765 TEST=Build coreboot Change-Id: I6f3c9270fb67210d6ea87e17ccf52d203fa64b4b Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7145 Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7584 Reviewed-on: https://review.coreboot.org/15081 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09soc/intel/apollolake: Add EMMC DLL APIZhao, Lijian
Starting from 136_30,FSP supports to update all the SDIO DLL programming value through silicon init upd. Implement the interface to pass board specific programming value to fsp silicon init. Change-Id: Ifd901148f3f7f89f966217491c661ec346337c38 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7372 Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7585 Reviewed-on: https://review.coreboot.org/15084 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09skylake: Support common LPSS I2C driverDuncan Laurie
Support the common Intel LPSS I2C driver for the 6 I2C bus controllers that are present on the Skylake-LP PCH with a 120 mHz clock. The required lpss_i2c_base_address() method is implemented separately for verstage/romstage and ramstage environments. This provides methods to convert to and from "struct device" and the I2C controller bus number for that device. These are used to provide support for the "I2C Bus Operations" that are present in the coreboot devicetree. To support the I2C controller before ramstage an early init function is provided to do minimal initializaiton of the PCI device and assign a temporary base address for use before memory. The final base address is assigned during device enumeration and used during ramstage. Because it is usually not necessary to enable I2C controllers before ramstage a config register for the devicetree is provided to perform early initialization of this controller. In addition the bus speed can be set in the devicetree and that speed will be applied when the device is initialized. If not provided the default speed is set to I2C_SPEED_FAST. This was tested with the google/chell mainboard by reading and writing from the trackpad and codec devices during both verstage and ramstage. Change-Id: Ia0270adfaf2843a3be4e00c732c85401a3401ef5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15105 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-09skylake: Move I2C bus configuration to separate structureDuncan Laurie
Move the existing I2C voltage configuration variable into a new structure that is equivalent, similar to how USB ports are configured. This is to make room for additional I2C configuration options like bus speed and whether to enable the bus in early boot which are coming in a subsequent commit. The affected mainboards are updated in this commit so it will build. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id2dea3df93e49000d60ddc66eb35d06cca6dd47e Reviewed-on: https://review.coreboot.org/15104 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-09skylake: gpio: Add support for setting 1.8V tolerantDuncan Laurie
Add the voltage tolerance GPIO attribute for configuring I2C/I2S buses that are at 1.8V. This is currently done by passing in a value to FSP but it is needed earlier than FSP if the I2C bus is used in verstage. This does not remove the need for the FSP input parameter, that is still required so FSP doesn't disable what has been set in coreboot. The mainboards that are affected are updated in this commit. This was tested by exercising I2C transactions to the 1.8V codec while in verstage on the google/chell mainboard. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I93d22c2e3bc0617c87f03c37a8746e22a112cc9c Reviewed-on: https://review.coreboot.org/15103 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-09skylake: Add function to set PRR for protecting flashDuncan Laurie
Add a function similar to broadwell to set the PRR for a region of flash and protect it from writes. This is used to secure the MRC cache region if the SPI is write protected. BUG=chrome-os-partner:54003 BRANCH=glados TEST=boot on chell, verify PRR register is set and that the MRC cache region cannot be written if the SPI is write protected. Change-Id: I925ec9ce186f7adac327bca9c96255325b7f54ec Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Id: abb6f645f5ceef3f52bb7afd2632212ea916ff8d Original-Change-Id: I2f90556a217b35b7c93645e41a1fcfe8070c53da Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349274 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Shawn N <shawnn@chromium.org> Reviewed-on: https://review.coreboot.org/15102 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-09soc/intel/common: Add LPSS I2C driverDuncan Laurie
Add a generic LPSS I2C driver for Intel SOCs that use the Synopsys DesignWare I2C block and have a similar configuration of that block. This driver is ported from the Chromium depthcharge project where it was ported from U-Boot originally, though it looks very different now. From depthcharge it has been modified to fit into the coreboot I2C driver model with platform_i2c_transfer() and use coreboot semantics throughout including the stopwatch API for timeouts. In order for this shared driver to work the SOC must: 1) Define CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ to set the clock speed that the I2C controller core is running at. 2) Define the lpss_i2c_base_address() function to return the base address for the specified bus. This could be either done by looking up the PCI device or a static table if the controllers are not PCI devices and just have a static base address. The driver is usable in verstage/romstage/ramstage, though it does require early initialization of the controller to set a temporary base address if it is used outside of ramstage. This has been tested on Broadwell and Skylake SOCs in both pre-RAM and ramstage environments by reading and writing both single bytes across multiple segments as well as large blocks of data at once and with different configured bus speeds. While it does need specific configuration for each SOC this driver should be able to work on all Intel SOCs currently in src/soc/intel. Change-Id: Ibe492e53c45edb1d1745ec75e1ff66004081717e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15101 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09soc/intel/quark: Pass serial port address to FSPLee Leahy
Pass the serial port address to FSP using a UPD value in the MemoryInit API. TEST=Build and run on Galileo Gen2 Change-Id: I86449d80310b7b34ac503ebd2671a4052b080730 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15079 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-08rockchip: rk3399: Add support i2sXing Zheng
This patch enable and configure the clocks and IOMUX for i2s audio path, and the i2s0 clock is from CPLL. Please refer to TRM V0.3 Part 1 Chapter 3 CRU, P126/P128/P144/P154/P155 for the i2s clock div and gate setting. BRANCH=none BUG=chrome-os-partner:52172 TEST=boot kevin rev1, press ctrl+u and hear the beep voice. Change-Id: Id00baac965c8b9213270ba5516e1ca684e4304a6 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 9c58fa7 Original-Change-Id: I130a874a0400712317e5e7a8b3b10a6f04586f68 Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/347526 Original-Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15034 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08gru: kevin: configure board GPIOsVadim Bendebury
Set board GPIOs as required and add their description into the appropriate section of the coreboot table, to make them available to depthcharge. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the rest of the patches applied it is possible to use keyboard on Gru, which indicates that the EC interrupt GPIO is properly configured. The rest of the pins will be verified later. Change-Id: I5818bfe855f4e7faa2114484a9b7b44c7d469727 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: e02a05f Original-Change-Id: I82be76bbd3211179e696526a34cc842cb1987e69 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/346631 Reviewed-on: https://review.coreboot.org/15031 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08rk3399: add ability to configure SPI5Vadim Bendebury
This defines mux settings for the GPIO bank responsible for SPI interface #5. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the rest of the patches applied it is possible to communicate with the EC on gru: pressing Ctrl-U during boot allows to start Chrome OS from the SD card. Change-Id: Ibc2293b5662892f7b275434f9a672ef68edf4f9e Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4f92452 Original-Change-Id: Idf55c069b05492f8cdc204a8c273e39a19a3aef3 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/346630 Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/15030 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08soc/apollolake: Add SOC specific c-state tableHannah Williams
Please refer Apollolake BIOS Writers Guide Change-Id: I5f82cdc4b34a53b5184ef1e918cae15a1df6cc5e Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-08soc/intel/common: Add common code for acpi c/p/t-state entriesHannah Williams
Change-Id: I87505bb31cd1b46d27cc5c9ba8d086df7393653e Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-07soc/intel/apollolake: Add missing DRAM density constantsAndrey Petrov
Add missing constants for DRAM density. This resolves boot issue, because misconfigured density results in incorrect memory mapping. Change-Id: I3bad911bf406bfc5677059490d0e89fcbf735b70 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15059 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-06-07rockchip: gru: update the hynix lpddr3 config to run at 928MHzShunqian Zheng
Update the DDR config and DRAM driver to allow running at up to 928MHz. Kevin config/clock rate are not being changed, but Gru now runs at 928 MHz. BRANCH=none BUG=chrome-os-partner:51537 TEST=booted Kevin and Gru to Linux prompt. Ran stressapptest for 10 min on Gru, Change-Id: I66c1a171d5c7d05b2878c7bc5eaa0d436c7a1be2 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 8baf0d82816a7ea1c4428e15caeefa2795d001f9 Original-Change-Id: I5e1d6d1025f10203da8f11afc3bbdf95f133c586 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/343984 Original-Reviewed-by: Stephen Barber <smbarber@chromium.org> Reviewed-on: https://review.coreboot.org/15027 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-06rk3288: Remove duplicate timestamp_init()Julius Werner
Fix bug introduced by merging http://review.coreboot.org/9606 and http://review.coreboot.org/10740 in the wrong order. Change-Id: I75dd22cd0cf30c7d91e4fa5171cb482a80eb64ca Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15070 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-06intel/skylake: Fix typo in commentPaul Menzel
Correct the spelling of *firmware* in a comment. Change-Id: I44bcd95f754ff839d582dc2150e1883a6315da9e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/15078 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-04soc/apollolake: Put CSE to low power stateHannah Williams
fsp_notify(END_OF_FIRMWARE) should be sent to FSP to enable putting CSE in low power state Change-Id: I76b8e85ccf077032616ba8e4a333d9264dc65ed2 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15054 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-04soc/apollolake/pmc: Store the ACPI bar during set_resources stageAlexandru Gagniuc
Because the resource for the ACPI BAR is fixed, pci_dev_set_resources does not store it to the device. This means we need to do part of the dance to get the ACPI IO region to work after coreboot. Of course, this BAR can be destroyed later by the OS probing it, but at least we try to get it working out of coreboot. Change-Id: Ibff18d30936f94d4f149a89313254531365f43e6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/15048 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-03rockchip: gru: enable eDP displayLin Huang
This patch enables eDP display by: o. setting HPD pinmux, backlight, vdd for eDP o. setting vop mode o. enabling VGA configs for edid BRANCH=none BUG=chrome-os-partner:51537 TEST=The dev screen is shown on kevin board Change-Id: If8b07307454daa88727d317cc208d6c97de07ad7 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: b1ad9337510f5437f691153dc68883edf273e4c7 Original-Change-Id: Id7006619b5be638b286a5402d892a5361ac1e430 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/340026 Original-Reviewed-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/14858 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-03rockchip: rk3399: initialize display for eDPShunqian Zheng
This patch adds functions to init the display. To set up the display, initialize the eDP and read the EDID. Based on these, we then set the clock for VOP, and finally enable VOP and backlight. For a mainboard, it should set the vop_id, vop_mode and framebuffer_bits_per_pixel in devicetree.cb. For VOP_MODE_AUTO_DETECT, it will try eDP first and then HDMI (which is not supported yet). EDIT: Updated Makefile to only build in new files if MAINBOARD_DO_NATIVE_VGA_INIT is enabled. All of these platforms should have it enabled, so this shouldn't make any difference except now, before the platform code is in place. BRANCH=none BUG=chrome-os-partner:51537 TEST=test with the other patch Change-Id: If935415026c945ab6ee128bd6bbdd792890aa24a Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: c1020cc806775629f4d5dc57bd805a9a12169386 Original-Change-Id: Ic32d0a251cb8e08aa5f0b15b2c06c4e02c08a761 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/342336 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14857 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-03intel/fsp_baytrail/i2c: mask i2c interrupts in i2c_init()Ben Gardner
i2c_init() leaves the I2C device enabled. Combined with the default interrupt mask (0x8ff) and the fact that the interrupt line is shared, this leads to an interrupt storm in the OS until a proper I2C driver is loaded. This change clears the interrupt mask to prevent the interrupt storm. Change-Id: I0424a00753d06e26639750f065a7a08a710bfaba Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/15047 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-06-03intel/apollolake: Clear TSEG reg early in bootblockFurquan Shaikh
TSEG register comes out of reset with a non-zero default value. This causes issues when cbmem_top returns non-zero value based on TSEG read before DRAM is initialized. Thus, clear TSEG reg early in bootblock to avoid unwanted side-effects. Change-Id: Id3c6c270774108e4caf56e2a07c5072edc65bb58 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15049 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-02intel/apollolake: Add car.c to verstageFurquan Shaikh
Verstage on apollolake requires the functions defined in car.c to perform flush of l1d to l2 on loading romstage into CAR. Change-Id: I6d9a0b9dfb58c2126ad70172846e90663e588857 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15046 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02Gale board: Move TPM setup function to verstage.cKan Yan
TPM should be only be reset once in verstage. BUG=chrome-os-partner:51096 TEST=Depthcharge no longer shows TPM error. BRANCH=None Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Commit-Id: 911bdaa83a05fa5c8ea82656be0ddc74e19064c3 Original-Change-Id: I52ee6f2c2953e95d617d16f75c8831ecf4f014f9 Original-Reviewed-on: https://chromium-review.googlesource.com/343537 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: I8047b7ba44c604d97a662dbf400efc9eea2c7719 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14845 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-06-01soc/apollolake: remove _RMV and _DSW methods from xhci.aslHannah Williams
Change-Id: Ic314656f34fda10e58e55bdefeb0a1f0c6ab5ae2 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14966 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-01intel/apollolake: Add support to enable google ChromeECShaunak Saha
ChromeEC is needed for EC controlled features to work properly. This patch adds neccessary support in soc/intel so that mainboard asl files can include the ChromeEC e.g. PNOT method and LPCB and also the nvs fields. BUG = 53096 TEST = This patch is needed by the mainboard specific ASL change to include src/ec/google/chromeec/acpi/ec.asl Change-Id: Icecc437df05cd3efb41579317a353fd22526e0c9 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/14967 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-01soc/intel/apollolake: add support for IFWI regionFurquan Shaikh
On apollolake, the boot media layout is different in that the traditional "BIOS" region contains another data structure with the boot assets such as CSE firmware, PMC microcode, CPU microcode, and boot firmware to name a few. This region is referred to as the IFWI. Add support for writing the IFWI to a specified FMAP region to accommodate such platforms. Change-Id: Ia61f12a77893c3dd3256a9bd4e0f5eca0065de26 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14999 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31quark: Enable HSUART0 as consoleLee Leahy
The use of HSUART0 on galileo requires early initialization of the I2C GPIO expanders to direct the RXD and TXD signals to DIGITAL 0 and 1 on the expansion connector. TEST=None Change-Id: I11195d79e954c1f6bc91eafe257d7ddc1310b2e7 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15010 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31soc/intel/quark: Move UART init into romstage.cLee Leahy
Move UART initialization into romstage.c and eliminate uart.c. TEST=Build and run on Galileo Gen2 Change-Id: I5f2c9b4c566008000c2201c422a0bba63da64487 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15009 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31soc/intel/quark: Split I2C out from driverLee Leahy
Split out the I2C code to allow I2C transactions during early romstage. TEST=Build and run on Galileo Gen2 Change-Id: I87ceb0a8cf660e4337738b3bcde9d4fdeae0159d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15007 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31soc/intel/quark: Set temporary I2C base addressLee Leahy
Set a temporary I2C base address during romstage. TEST=Build and run on Galileo Gen2 Change-Id: I4b427c66a4e7e6d30cc611d4d3c40bb0ea36066d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15006 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31soc/intel/quark: Conditionally define BIT namesLee Leahy
Only define BIT names if they are not already defined. TEST=Build and run on Galileo Gen2 Change-Id: Ief4c4bb7a42a1bb2a7f46f13dc9b8bbb4d233e3c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15002 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31soc/intel/quark: Fix reg_script displayLee Leahy
Remove extra ": " following reigster type. TEST=Build and run on Galileo Gen2 Change-Id: I57dd40a540d7b5371a6c45174f47a311b83a2aab Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14948 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31soc/intel/quark: Clear SMI interrupts and wake eventsLee Leahy
Migrate the clearing of the SMI interrupts and wake events from FSP into coreboot. TEST=Build and run on Galileo Gen2 Change-Id: Ia369801da87a16bc00fb2c05475831ebe8a315f8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14945 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31soc/intel/quark: Rename pmc.c to lpc.cLee Leahy
Rename the file pmc.c to lpc.c to prepare for further additions. TEST=Build and run on Galileo Gen2 Change-Id: If98825d72878f0601f77bff8c766276dbda8a9ae Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14946 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31soc/intel/quark: Add PCIe reset supportLee Leahy
Migrate PCIe reset from PlatformPciHelperLib in QuarkFspPkg into coreboot. Change-Id: I1c33fa16b0323091e8f9bd503bbfdb8a253a76d4 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14944 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 22:19:42 +0000