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2023-08-12soc/amd/common/data_fabric: read PCI bus decoding from DF registersFelix Held
The data fabric also controls which PCI bus numbers get decoded to the PCI root. In order for the resource allocator to know how the hardware is configured, read the corresponding data fabric registers to get the information that then gets passed to the allocator. Picasso, Cezanne, Mendocino and Rembrandt only support one PCI segment with 256 buses while the Phoenix and Glinda data fabric hardware has support for more PCI segments. Due to this change, the register layout is different and incompatible between those two, so introduce the SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT Kconfig option for a SoC to specify which implementation is needed. At the moment, coreboot doesn't have support for multiple PCI segments and the code doesn't support PCI segments other than segment 0. On Picasso the PCI bus number limit read back from the data fabric register is 255 even though CONFIG_ECAM_MMCONF_BUS_NUMBER is set to 64, so also make sure that the bus and limit returned by data_fabric_get_pci_bus_numbers is within the expected limits. TEST=PCI bus allocation still works on Mandolin (Picasso) and Birman (Phoenix). Picasso has 64 PCI buses. coreboot puts this info into the resource producer in _SB\PCI0\_CRS which the Linux kernel reads: * coreboot: PCI0 _CRS: adding busses [0-3f] * Linux: pci_bus 0000:00: root bus resource [bus 00-3f] This matches the information in the ACPI MCFG table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ide5fa9b3e95cfd59232048910cc8feacb6dbdb94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77080 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11soc/amd/glinda/Kconfig: fix commentFelix Held
The SOC_AMD_REMBRANDT_BASE comment at the end of Glinda's Kconfig is probably a leftover from the Mendocino/Rembrandt SoC this file was copied from. Change it to SOC_AMD_GLINDA to match the corresponding 'if SOC_AMD_GLINDA' in the file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85132e4840c1bc713cfc2f3493f800d66edd10ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/77121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-08-11soc/intel/braswell: Adjust status of IOSF ACPI objectMatt DeVillier
Neither Windows nor mainline Linux make use of IOSF on the Braswell platform, so adjust the ACPI status return value based on CONFIG(CHROMEOS) to prevent an unknown device being listed in Windows device manager. TEST=build/boot Win11, Linux 6.2 on google/edgar Change-Id: Ic51624ffd816d48c007c13d510601cf8cbf1edc4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-08-11soc/intel/baytrail: Adjust status of IOSF ACPI objectMatt DeVillier
Neither Windows nor mainline Linux make use of IOSF on the Baytrail platform, so adjust the ACPI status return value based on CONFIG(CHROMEOS) to prevent an unknown device being listed in Windows device manager. TEST=build/boot Win11, Linux 6.2 on google/swanky Change-Id: I249028c57cc704955cf5a11e2088780ef58e16cf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77141 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11soc/intel/alderlake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I83574032ef506a411571e8363f476f322ac13e5e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76686 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11soc/amd/common/data_fabric/domain: set and use max_subordinateFelix Held
Set the maximum subordinate bus number of the domain to the last PCI bus number that is decoded to this PCI root. This makes sure that the resource allocator knows the maximum number of PCI buses on this PCI root to not assign bus numbers to buses below this PCI root that aren't routed to that PCI root. Now that we have this info in the link list structure or the domain device, we can pass the max_subordinate field to the acpigen_resource_producer_bus_number call and can leave the subordinate number after pci_domain_scan_bus is done unchanged instead of setting it to the limit. TEST=On Mandolin both the bus resource producer in _SB\PCI0\_CRS and the PCI bus number allocation remain unchanged. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2ee75b2a7054a306b0c7d98c5357391c029187bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/77112 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11soc/amd: Add definition of SPI ROM remappingZheng Bao
Change-Id: Icafa36ae2e07068c276600067bba1d0377f0824b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74258 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11soc/intel/meteorlake: Add provision to show pre-boot splash screenSubrata Banik
This patch adds the ability to show a pre-boot splash screen on Meteor Lake systems using FSP-S. The patch calls into `fsp_convert_bmp_to_gop_blt()` when the `BMP_LOGO` config is enabled. This function converts a BMP file to a BLT buffer, which is then used by FSP-S to render the splash screen. Additionally, increase the heap size (malloc'able size) upto 512KB (when BMP_LOGO config is enabled) to accommodate high resolution logo file. BUG=b:284799726 TEST=Able to see pre-boot splash screen while booting google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3608bfacc21574e12cde0e2012a16e6388ce54df Reviewed-on: https://review.coreboot.org/c/coreboot/+/76922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-08-11soc/intel/alderlake: Disable PCIe clock gatingPatrick Rudolph
Intel requires that all enabled PCIe PCH ports have a CLK_REQ signal connected. The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1 link-state is also entered on PCI-PM D3, even with ASPM L1 disabled. When no CLK_REQ signal is used, for example when it's using a free running clock the silicon will never wake from L1 link state. This will trigger a MCE. Starting with FSP MR4 the UPD 'PchPcieClockGating' allows to work around this issue by disabling ClockGating. Disabling ClockGating should be avoided as the silicon draws more power when it is idle. TEST: Verified on two boards, one with missing CLK_REQ on a PCH root port, that the code does the right decision to disable UPD PchPcieClockGating and PchPciePowerGating when necessary. Change-Id: I673bbdbadc9afbed6a7bd5ce9f35dc70716d875b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-08-10soc/amd/mendocino/include/data_fabric: fix IOMS0_FABRIC_ID for RembrandtFelix Held
Rembrandt has different data fabric component IDs compared to Mendocino. PPR #56558 Rev 3.04 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3c840a3e071a289d9e02143ee790c26faeda029d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-08-10soc/amd/common/psp_verstage: Enable Legacy IO only on older SoCsKarthikeyan Ramasubramanian
With reference to the Picasso PPR 55570 Rev 3.18, LegacyIoEn bit is 0 on reset and setting it will enable the decoding of the following legacy IO ports: 0x20, 0x21, 0xA0, 0xA1 (PIC); 0x40, 0x41, 0x42, 0x43, 0x61 (8254 timer); 0x70, 0x71, 0x72, 0x73 (RTC); 0x92. Verstage does not use those legacy IO ports. Also newer SoCs like Phoenix do not support Legacy I/O registers to access Power Management registers and accessing them from PSP verstage causes a hang. Hence enable legacy IO only on platforms that support it. BUG=b::284984667 TEST=Build Myst BIOS image with PSP Verstage. Boot to OS successfully with PSP verstage. Change-Id: I5e74b4cd1fa7e942770976e5e2197ded47503660 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76692 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-10soc/intel/jasperlake: Add configs for USB 3.1 Gen2 EV settingsChia-Ling Hou
Add configs for USB 3.1 Gen2 electrical validation (EV) settings so that people can set the EV settings per board in device tree. BUG=b:285811345 TEST=build coreboot and fsp with enabled fw_debug. Flashed to taranza and checked the log. All usb configs were set correctly. Change-Id: Iecd12d3db76b63ad99887dee5991d94d47f138fd Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76246 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-08-09treewide: Get rid of "NO_DDRx" selectionElyes Haouas
Change-Id: I8fa26e7a398eee855c31a76f0f89b4111368c2a6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-09soc/intel/baytrail: Specify supported memory typeElyes Haouas
Change-Id: Ie360ca3640a4774e3baec36468a69f76fcd1217b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-09soc/amd/glinda/include/data_fabric: add DF PCI config map registerFelix Held
PPRs #57254 Rev 1.52 and #57255 Rev 0.33 were used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie54fd6c5a82f368018d0b5fb811a6c9220c2c70b Reviewed-on: https://review.coreboot.org/c/coreboot/+/77079 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09soc/amd/phoenix/include/data_fabric: add DF PCI config map registerFelix Held
PPRs #57019 Rev 3.05 and #57396 Rev 3.06 were used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id0fe478a710ecc1f2c8b36347aaf2d1634ebba9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77078 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09soc/amd/mendocino/include/data_fabric: add DF PCI config map registerFelix Held
PPRs #57243 Rev 3.02 and #56558 Rev 3.04 were used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibabe8faa79e3dcd02f4c885d29b9634645947b98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77077 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-09soc/amd/cezanne/include/data_fabric: add DF PCI config map registerFelix Held
PPR #56569 Rev 3.04 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idfac7d996c6de9ea7c6adf2760de0ad97ffb9ec0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-09soc/amd/picasso/include/data_fabric: add DF PCI config map registerFelix Held
PPR #55570 Rev 3.18 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ide492f4479b85cd885044bbf74d8bf18c12e552b Reviewed-on: https://review.coreboot.org/c/coreboot/+/77075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-09soc/amd/common/include/data_fabric: add missing device/device.h includeFelix Held
device/device.h provides struct device. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie03f6d15d94f2858e293b9f57505034263c03bbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/77074 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-09soc/amd/*: Fix UART ACPI device statusMatt DeVillier
Prior to commit d1c0f958d198 ("acpi: Call acpi_fill_ssdt() only for enabled devices"), uart_inject_ssdt() was used to set the ACPI status (_STA) for both enabled and disabled devices. The aforementioned commit limited it to being called only on enabled devices, which left disabled devices without any _STA method at all -- which the OS assumes means that the device is present and enabled. To fix this, create the _STA method in the UART asl code for each port, and set the return value to a name variable (STAT) which defaults to 0 (not present/disabled). Then, have uart_inject_ssdt() set STAT to present and enabled (0xF) for UARTs actually present on the board. TEST=build/boot google/skyrim (frostflow), dump ACPI tables, and verify that _STA returns 0xF only for UARTs enabled in devicetree. Change-Id: Id89e74c3ea7f53280935898ee35311b7cf3b152a Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77092 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09soc/amd/stoneyridge: use SoC common uart opsMatt DeVillier
Define the UARTs as MMIO devices in the chipset devicetrees. Drop ACPI _STA in asl since now handled by common SSDT generator. Implement wait_for_aoac_enabled() since required by SoC common code, and ensure compiled during all stages necessary. TEST=build/boot google/liara, verify console UART still functional. Change-Id: Ibecafdfa189d9c63a29b63759c5b965d03719009 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77093 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09Revert "soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitions"Jeremy Soller
This reverts commit 5dfec718290609dc0fd0331070ad703107e0b7e7. Reason for revert: This change made it impossible to disable ASPM by FSP parameter. ASPM_DISABLE would result in the FSP parameter not being programmed, causing it to be the FSP default value instead. This additionally fixes MTL to match ADL. Change-Id: I60c0ea08513fcb0035449ea3fef1681de528c545 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75280 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09soc/intel/xeon_sp/spr: Add soc_config_iio to set IIO UPD from mainboardJohnny Lin
To deduplicate mainboard mainboard_config_iio since there are a few SPR-SP mainboards now. The flow would be soc function initialize_iio_upd initializes the table with the default values which are mostly zero, then mainboard can overwrite it by soc_config_iio. Change-Id: I72d74241fcad4c85a95f6d14587418f544caadd9 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76185 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-09soc/intel/xeon_sp/ebg: Add periodic SMI bits definitionMichał Żygowski
Change-Id: Ia906a115538964628958bb4b6e3de3aa71577cce Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76252 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08cpu/amd/pi/00730F01: Use common code for mp_initArthur Heymans
TEST=APU2 still boots and doesn't show any new errors in dmesg. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia9f0eb3df8fd2dfe395f616da981cc3a0cd3b29d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-08-08soc/amd/common/data_fabric/domain: read IO decode windows from registersFelix Held
Before add_io_regions only reported one fixed IO range to the resource allocator that covered the whole IO range from 0x0000 to 0xffff. Instead read the data fabric IO space decode base and limit address register pairs to get the actual IO port decoding from the data fabric registers. This will also help with adding support for multiple PCI root domains to the common data fabric domain code so that Genoa can use it. In that case each PCI root domain will only decode a part of the whole IO port range. Beware that the data fabric IO base and limit fields can contain values that correspond to IO port addresses far outside of the addressable IO port range. In case of Picasso, the IO limit read from the only enabled DF IO range register would be 0x1ffffff after converting the raw data to an IO port address. To not give the resource allocator wrong constraints make sure that the IO limit we report will be at maximum 0xffff. TEST=On Mandolin (Picasso) and Birman (Phoenix) the full range of IO port addresses still gets reported as a domain IO resource producer like before the patch: DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I087d96f7bdaae0d7b53089f6abaf0500a4b064e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08soc/amd/glinda/include/data_fabric: add data fabric IO decode registersFelix Held
PPRs #57254 Rev 1.52 and #57255 Rev 0.33 were used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia58e26caa1ba910b41911991b176a1ac8c4e0065 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08soc/amd/phoenix/include/data_fabric: add data fabric IO decode registersFelix Held
PPRs #57019 Rev 3.05 and #57396 Rev 3.06 were used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I769dc317115981391cf0f4e0b743c600407a6eb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76958 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08soc/amd/mendocino/include/data_fabric: add DF IO decode registersFelix Held
PPRs #57243 Rev 3.02 and #56558 Rev 3.04 were used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic68e73e28362abc5d812839b40282114c7ba25ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/76957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08soc/amd/cezanne/include/data_fabric: add data fabric IO decode registersFelix Held
PPR #56569 Rev 3.04 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifcae9c9ad664d50100cd40692fd9631845f76671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08soc/amd/picasso/include/data_fabric: add data fabric IO decode registersFelix Held
PPR #55570 Rev 3.18 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I61d4fca48d71010bbc4bd94a2fb8889bad08f1cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/76935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-08-08soc/amd/common/data_fabric/domain: rename add_io_regionsFelix Held
Rename add_io_regions to add_data_fabric_io_regions to be consistent with add_data_fabric_mmio_regions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia990cc14dd6dc162ad614a6e9e0b36426cb04670 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-08-08soc/amd/common/data_fabric/domain: factor out report_data_fabric_ioFelix Held
As a preparation to read the IO decode ranges from the data fabric registers instead of having it hard-coded, factor out the report_data_fabric_io function to report one IO producer region from add_io_regions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I51c3f8cd6749623f1a4bad14873d53b8a52be737 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76933 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08soc/amd/*/include/data_fabric: add dst_ prefix to fabric_id fieldFelix Held
Rename the fabric_id struct field in the df_mmio_control union to dst_fabric_id to both better match the register definitions and also be a bit clearer about what this is doing. Also use tabs for indentation in the struct inside the df_mmio_control union. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0a17d82a5d7b66a8f84854f21fbbb319da81ac43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-08-08soc/amd/*/include/data_fabric: reorder register definitionsFelix Held
Order the data fabric register definitions by function number and register offset. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia3066ad0f564520cb322a3e41a413eb3bf51260d Reviewed-on: https://review.coreboot.org/c/coreboot/+/76923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08soc/amd/*/include/data_fabric: rename D18F0_DRAM_* to DF_DRAM_*Felix Held
Now that the data fabric PCI device functions are included in the register definitions, the remaining data fabric device function numbers can be dropped from the define names. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1a26402b8078d288a7e32c1668591d001fa3ede9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76889 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08soc/amd/*/include/data_fabric: rename D18F0_MMIO_* to DF_MMIO_*Felix Held
Now that the data fabric PCI device functions are included in the register definitions, the remaining data fabric device function numbers can be dropped from the define names. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia0355838ac1d513ba562fd6fb4672342dd383498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76888 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-08soc/amd/common/data_fabric_helper: use DF broadcast read/write functionsFelix Held
Instead of open coding the broadcast data fabric PCI register access in the functions for indirect non-broadcast data fabric register access, just use the existing data_fabric_broadcast_[read,write]32 functions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I174c1e6ee4856d97c5ec6d07bb8c217d6df9425f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-08soc/amd/common/include/data_fabric_defs: introduce & use DF_REG_* macrosFelix Held
To have both the PCI function number and the register offset into the config space of that function of the data fabric device in the data fabric register definitions, introduce and use the DF_REG_ID, DF_REG_FN and DF_REG_REG macros. The DF_REG_ID macro is used for register definitions where both the function number and the register offset are specified, and the DF_REG_FN and DF_REG_REG macros are used to extract the function number and the register offset from the register defines. This will allow having one define for accessing an indexed group of registers that are on different functions of the data fabric device. TEST=MMIO resources read from the data fabric's MMIO decode registers don't change on Mandolin and the ACPI CRAT table is also identical. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I63a284b26081c170a217b082b100c482f6158e7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/76886 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-08ACPI: Add helper fill_fadt_extended_pm_io()Kyösti Mälkki
Once platform code has filled in the (legacy) ACPI PM register map, added function will fill in the extended entries in FADT. TEST=samsung/lumpy and amd/mandolin FADT stays unchanged. Change-Id: I90925fce35458cf5480bfefc7cdddebd41b42058 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-06soc/mediatek/mt8188: Support ARM arch timerYidi Lin
Use ARM architectual timer by initializing frequency to 13 MHz. Since system timer is the source of the architectual timer, we also call `timer_prepare` in `init_timer`. BUG=b:229800119 TEST=run `suite:faft_bios` to verify the firmware stability. check timestamps by cbmem. Cq-Depend: chromium:4747539 Change-Id: I8b1348044e4c92984510604b7f61611e13284d86 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76919 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06device, soc: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the device and soc directories that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I89c05c7c1c39424de2e3547c10661c7e3f58b8f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2023-08-06soc/intel/common/tcss: Configure USB-C ports with attached devicesCoolStar
Inspect all type-C USB ports, check if there is a USB device attached, and if so, send the connection request to the PMC. This allows for any attached USB2/USB3 devices to be used for booting by the payload. Since this functionality is only needed by ChromeOS devices with TCSS running upstream coreboot, introduce a new Kconfig to guard its use. Boards needing it will select it in subsequent commits. TEST=tested with rest of patch train Change-Id: I69522dbcc8cae6bbf41659ae653107d0e031c812 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72909 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06soc/intel/common/block/tcss: Fix printk formattingMatt DeVillier
Variable 'i' is unsigned, so use %zu vs %zd. Change-Id: I5f5b28796b30285e81a94c37e686a9e763cab204 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76943 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05src/*/post_code.h: Change post code prefix to POSTCODEYuchen He
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. header="src/soc/amd/common/block/include/amdblocks/post_codes.h \ src/include/cpu/intel/post_codes.h \ src/soc/intel/common/block/include/intelblocks/post_codes.h" array=`grep -r "#define POST_" $header | \ tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2` for str in $array; do splitstr=`echo $str | cut -d '_' -f2-` grep -r $str src | cut -d ':' -f 1 | \ xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g" done Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-04soc/amd/phoenix: Makefile change to include split hash tableKarthikeyan Ramasubramanian
Include multiple hash tables into relevant CBFS. BUG=b:277292697 TEST=Ensure that all multiple hash tables are part of Myst BIOS image with PSP verstage enabled. Change-Id: I1601f4a01db5b2bbf8b5636ef9e69e41c1d9a980 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76589 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04soc/amd/phoenix: Add SVC call to inject v2 hash tablesKarthikeyan Ramasubramanian
On mainboards using Phoenix SoC with PSP verstage enabled, to accommodate growing number of PSP binaries, multiple smaller hash tables are introduced. Also some hash tables are in V2 format identifying the concerned PSP binaries using UUID. Add SVC calls to support multiple hash tables with different versions. BUG=b:277292697 TEST=Build and boot to OS in Myst with PSP verstage enabled. Ensure that all the hash tables are injected successfully. Ensure that PSP validated all the signed PSP binaries using the injected hash tables successfully. Change-Id: I64e1b1af55cb95067403e89da4fb31bec704cd4f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76588 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04soc/amd/common/psp_verstage: Support multiple hash tablesKarthikeyan Ramasubramanian
Currently PSP verstage updates PSP bootloader with one unified hash table containing hashes for all the signed PSP binaries to be validated. With growing number of PSP binaries to validate and memory constraints in PSP, there is a requirement to split and update the hash table into multiple smaller chunks. Hence change the update_psp_fw_hash_table() signature such that the hash tables are updated in a chipset specific way. BUG=b:277292697 TEST=Build and boot to OS in Myst with PSP verstage enabled. Build the Skyrim BIOS image and confirm that the hash table is identical before and after this change. Change-Id: I75aac5bc5e7f61069be25d801d0838fdf565d3d1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76587 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04soc/amd/common/data_fabric_helper: add comment about cfg_inst_acc_enFelix Held
Since all indirect data fabric register accesses will be non-broadcast accesses that target a specific data fabric instance, the cfg_inst_acc_en bit in the DF_FICAA_BIOS register will always be set since that makes the indirect access target only a specific data fabric instance. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9aff01750c2c1e3506141b3ed293a980a64f8fac Reviewed-on: https://review.coreboot.org/c/coreboot/+/76885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-08-04soc/intel/meteorlake: Hook up UPD for C1 C-state auto-demotionSukumar Ghorai
FSP has a parameter to enable/disable c1-state autodemotion feature. Boards/Baseboard can choose to use this feature as per requirement. This patch hooks up this parameter to devicetree. BUG=b:286328295 TEST=Check code compiles & boot google/rex, and correct value has been passed to FSP. Change-Id: I2cc60bd297271fcb3000c0298af71208e3be60fc Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76826 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-08-04soc/intel/mtl: Change default for debug consent from 3 to 6Kane Chen
USB DBC is very helpful for SoC debug. TraceHub needs to be enabled in coreboot if debug consent == 2 or 4. Debug consent == 6 enables USB DBC without TraceHub enabled. This patch updates the Kconfig help text to meet PlatformDebugOption in MTL and changes debug consent to 6 in default to provide basic SoC debug capability. TEST=Boot to OS on screebo and DBC connection is OK. Change-Id: Ic12528bdd8b1feda7f1b65045c863341f932d3a2 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76880 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04soc/sifive/fu540/Kconfig: Fix opensbi platformMaximilian Brune
commit 9a7a677 from opensbi project moved the fu540 platform to generic code and commit 26998f3 from opensbi removed the old non generic platform. Therefore opensbi platform needs to change to generic. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I76aa3d386936b331785a23edb8deb0d73609be47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-04soc/intel/common: Return CB_ERR when cse_data_clear_request() failsKrishna Prasad Bhat
cse_prep_for_rw_update() should return CB_ERR when cse_data_clear_request fails. It was modified to CB_SUCCESS in this commit ad6d3128f87c ("soc/intel/common: Use enum cb_err values") BRANCH=None BUG=None TEST=Verify the system goes to recovery during downgrade when cse_data_clear_request() fails. Change-Id: Ibbccb827765afa54e5ab1b386fa46093b803977a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-04soc/intel/meteorlake: Generate new TME key on each warm bootPratikkumar Prajapati
Enable config TME_KEY_REGENERATION_ON_WARM_BOOT for Intel Meteor Lake SOCs. This config allows Intel FSP to programs TME engine to generate a new key for each warm boot and exclude CBMEM region from being encrypted by TME. Bug=b:276120526 TEST= Boot up the system, generate kernel crash using following commands: $ echo 1 > /proc/sys/kernel/sysrq $ echo "c" > /proc/sysrq-trigger System performs warm boot automatically. Once it is booted, execute following commands in linux console of the DUT and confirm ramoops can be read. $ cat /sys/fs/pstore/console-ramoops-0 S0ix also tested and found working. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I3161ab99b83fb7765646be31978942f271ba1f9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-03soc/intel/common/block/cse/Kconfig: Remove unused symbolsElyes Haouas
Change-Id: I35742721e049102a3e153b857824073a5d257cc3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76693 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/xeon_sp/spr/Kconfig: Remove unused MAX_MC_CHNElyes Haouas
Change-Id: Ia4011a0f29d360fbe46a5e052e2acb3d23d8ceaf Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76695 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/jasperlake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I5ad1a1bf51bb7a451239252f01a90c1d4d94ba49 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76685 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/skylake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: Iea0e55c6c55635976dad0422470f3927bdc26e35 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03soc/intel/tigerlake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: Id268943b9347fdb54e07b55c0a2a18ac77bb3a58 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03soc/intel/xeon_sp/Kconfig: Remove useless USE_FSP2_0_DRIVERElyes Haouas
Change-Id: Ic384ee804e217ba79f7e191f122ec61565abfc40 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03soc/intel/xeon_sp/spr/Kconfig: Remove unused SIPI_FINAL_TIMEOUTElyes Haouas
Change-Id: I915e0e942adf33175fdc9fe055fce013824d6c0f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76698 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/broadwell/Kconfig: Remove dummy SOC_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I4ccb8d38f18cb440f54723cc1f29e25b82dac8ee Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76700 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/meteorlake: Set UPDs for TME exclusion range and new key genPratikkumar Prajapati
Set UPD params GenerateNewTmeKey, TmeExcludeBase, and TmeExcludeSize when TME_KEY_REGENERATION_ON_WARM_BOOT config is enabled. These UPDs are programmed only when INTEL_TME is enabled. Bug=b:276120526 TEST=Able to build REX platform. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: Ib8d33f470977ce8db2fd137bab9c63e325b4a32d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75626 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/common: Merge TME new key gen and exclusion range configsPratikkumar Prajapati
Merge TME_KEY_REGENERATION_ON_WARM_BOOT and TME_EXCLUDE_CBMEM_ENCRYPTION config options under new config option named TME_KEY_REGENERATION_ON_WARM_BOOT. Program Intel TME to generate a new key for each warm boot. TME always generates a new key on each cold boot. With this option enabled TME generates a new key even in warm boot. Without this option TME reuses the key for warm boot. If a new key is generated on warm boot, DRAM contents from previous warm boot will not get decrypted. This creates issue in accessing CBMEM region from previous warm boot. To mitigate the issue coreboot also programs exclusion range. Intel TME does not encrypt physical memory range set in exclusion range. Current coreboot implementation programs TME to exclude CBMEM region. When this config option is enabled, coreboot instructs Intel FSP to program TME to generate a new key on every warm boot and also exclude CBMEM region from being encrypted by TME. BUG=b:276120526 TEST=Able to build rex. Change-Id: I19d9504229adb1abff2ef394c4ca113c335099c2 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76879 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/alderlake/meminit.c: Guard CsPiStartHighinEct properlyMichał Żygowski
Build issue introduced by patch CB:76418 (commit hash 01025d3ae78e02192d389f22abd36747e3d8c63b) for Google boards. Patch has not been rebased to latest master and tested before submission causing the Jenkins jobs to fail. Change-Id: I95bd2485b98be4ab3a39eaaebb9efb34db93bbe8 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76915 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03src/soc/intel/alderlake: add SOC_INTEL_RAPTORLAKE_PCH_S symbolMichał Żygowski
Introduce new symbol SOC_INTEL_RAPTORLAKE_PCH_S that can be selected by board with RPL-S PCH. For now only the IoT variant of RPL-S FSP is available for use with 700 series chipsets. Boards with 600 series chipsets can still use RPL CPUs with the ADL-S C.0.75.10, which contains minimal RPL-S CPU support. Change-Id: I303fac78dac1ed7ccc9d531a6c3c10262f7273ee Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-03soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPOMichał Żygowski
Only the headers on Intel FSP repository have the CnviWifiCore present. Options guarded for RPL like: DisableDynamicTccoldHandshake or EnableFastVmode and IccLimit is also supported by all public FSPs (except ADL-N for the handshake). Options like LowerBasicMemTestSize and DisableSagvReorder have to be guarded when FSP_USE_REPO is not selected, as publci FSPs do not have these options. Use FSP_USE_REPO instead of/in addition to SOC_INTEL_RAPTORLAKE as dependency on the guarded UPDs to make them available for FSPs that support them as well. Also prioritize the headers from FSP repo over vendorcode headers if FSP_USE_REPO is selected. Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-08-01soc/amd/mendocino: select SOC_AMD_COMMON_BLOCK_CPU_SYNC_PSP_ADDR_MSRMatt DeVillier
Select this Kconfig to ensure the PSP_ADD_MSR is properly programmed across all cores. This resolves a Windows BSOD "CRYPTO_LIBRARY_INTERNAL_ERROR." BUG=b:293571109 BRANCH=skyrim TEST=build/boot google/skyrim, use rdmsr to verify MSR value identical across all cores. Change-Id: I67391b49496d767912f5d81c1758a52a70fca6f6 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76809 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01soc/intel/broadwell/include/soc/me.h: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I2d65e9dbefc8fa5d8288151995a587f76049c65a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-01soc/intel/common/mma: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Id19193b960935eeffca8e8db60073321592368fe Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76836 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01soc/amd/common: Redefine EFS_OFFSETZheng Bao
The EFS_OFFSET is the relative address to flash base. We can not assume the flash size is 16M. The change will affect only Gardenia and Pademelon whose flash size are 8M. Change-Id: Ia68032db05264c55d333deec588ad9690a4ed2c1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76764 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31soc/amd/common/cpu: Add Kconfig to program the PSP_ADDR MSRMatt DeVillier
The PSP_ADDR_MSR is programmed into the BSP by FSP, but not always propagated to the other cores/APs. Add a hook to run a function which will read the MSR value from the BSP, and program it into the APs, guarded by a Kconfig. SoCs which wish to utilize this feature can select the Kconfig. BUG=b:293571109 BRANCH=skyrim TEST=tested with rest of patch train Change-Id: I14af1a092965254979df404d8d7d9a28a15b44b8 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-31soc/intel/apl: Hide PMC/IPC ACPI device from WindowsMatt DeVillier
No drivers are needed/available, so hide the device to prevent an unknown device from showing under Device Manager. Linux does not use the ACPI _STA so no effect there. Change-Id: I02efb64a845edc6e4fc559e7e99a7825abf4c2aa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-31soc/intel/apl: program VMX per Kconfig settingMatt DeVillier
While FSP programs the VmxEnable UPD per CONFIG_ENABLE_VMX, it doesn't set the lock bit, which prevents Windows from enabling virtualization on devices which support it. Call set_vmx_and_lock() to ensure the lock bit is properly set. TEST=build/boot Win11 on google/ampton,reef; verify virtualization enabled. Change-Id: I54ea0adb0a6d10f2df18f604b1f1e5a7a145dfb3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76804 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-07-31soc/intel/alderlake: Allow channel 0 for DDR5 memory-downJeremy Soller
This matches the change done for DDR4 in commit 8509c25eece8 ("soc/intel/alderlake: Allow channel 0 for memory-down"). Fixes detection of the on-board RAM (Samsung M425R1GB4BB0-CQKOD) on the System76 Lemur Pro 12 (Clevo L140AU). The Clevo L140*U are the only boards in the tree using mixed memory topology. Change-Id: I395f898472a9a8f857fd6b0564b95c787b96080b Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-31soc/intel/common/block/pcr: Remove useless break after a returnElyes Haouas
Change-Id: Ie7f2144d0af21ba111464dfd135159704a3d82b7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76474 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31soc/intel/alderlake/hsphy.c: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Id0baf970dbe94a8ebf75f8dbabc6abe345d1c454 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-07-30soc/amd/common/data_fabric/domain: skip reserved resources for ACPIFelix Held
The non-PCI resources added to the domain device are resource consumers, so they mustn't be reported as resource producers. To make sure that this is the case, skip all resources that have the IORESOURCE_RESERVE flag set in amd_pci_domain_fill_ssdt. Commit 7a5dd781d147 ("soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt") that introduced amd_pci_domain_fill_ssdt already contained the bug, but since no MMIO range consumers were added back then, the bug only became visible when commit 32169720bb67 ("soc/amd/common/data_fabric/domain: report non-PCI MMIO resources") added the reserved non-PCI MMIO resources to the domain device's resources resulting in MMIO producer objects being generated for MMIO consumers. Those producers that should have been consumers then overlapped with the actual MMIO resource producers which caused Windows to BSOD with an ACPI_BIOS_ERROR. TEST=The non-PCI MMIO resources are no longer added as resource producers and Windows boots again on google/frostflow. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: Matt DeVillier <matt.devillier@gmail.com> Change-Id: Ib099675bc5bea93bf7c2a80f741bef067fd37a58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-30soc/amd/common/data_fabric/domain: continue after unassigned resourceFelix Held
When iterating over the resource list in amd_pci_domain_fill_ssdt, don't return when a resource is unassigned, but just continue to the next loop iteration so the resulting SSDT will be complete and not broken due to a missing resource template footer and the scope not being closed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I39fe516f27a6d971fb9c57a1e64ead79d23aff08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-30soc/intel/broadwell/pch/me.c: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Iea63e7ce165b1c8129725136e39bff45765023e6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-28soc/amd/commonn/block/include/psp_efs.h: Remove unused functionFred Reitberger
Commit 49d8aa7043ea ("soc/amd/common/block/psp: Unmap EFS region after use") removed the 'efs_is_valid' function but left the function signature in the header file. TEST=stoney/picasso/cezanne/mendocino/phoenix builds Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib596946679b50be63868af57e3428b4d65845419 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76750 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-27soc/amd/noncar/memlayout_x86.ld: Conditionally add fspm regionFelix Held
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1e75f29a52179b72b25092f0ffdfd91a182d6648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-27soc/amd/noncar/memlayout_x86.ld: Move ramstage link addressArthur Heymans
This address is more certain to not collide with other symbols. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I02eddf43a00c443a1193d6db77d6fad3715216f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-27soc/amd/noncar/memmap.c: Support non-FSP use casesFelix Held
Without FSP we assume TSEG is right above CBMEM. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8700803617c3fe4890e497c6d7b94f1d36e21cb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76472 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-27soc/amd/noncar/memmap.c: factor out FSP-specific SMM region codeFelix Held
Factor out the common FSP-specific code to get the location and size of the SMM region from the HOB that FSP has put into memory. This moves FSP-specific code out of the common AMD SoC code into the FSP-specific common AMD SoC code folder. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie137bb0f4e7438a1694810ae71592a34f9d8c86e Reviewed-on: https://review.coreboot.org/c/coreboot/+/76760 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-07-27soc/amd/common/fsp: factor out read_fsp_resources from root_complex.cFelix Held
Factor out the common FSP-specific code to report the usable and reserved memory resources read from the HOBs that FSP has put into memory. This both reduces code duplication and also moves FSP-specific code out of the SoC code into the FSP-specific common AMD SoC code folder. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib373c52030209235559c9cd383f48ee1b3f8f79b Reviewed-on: https://review.coreboot.org/c/coreboot/+/76759 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-27soc/amd/cpu.c: Conditionally define .acpi_fill_ssdtFelix Held
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I0e81c08191f3c5f768bd3cad0e4915d4476c739f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-25soc/amd/*/root_complex: introduce and use SMN_IOHC_MISC_BASE_13B1Felix Held
On the mobile SoCs, SMN_IOHC_MISC_BASE_13B1 is the only IOHC misc base address, but on for example Genoa it's the address of the IOHC misc base of the second IOHC. Due to it not being the first one on Genoa, use 13B1 as part of the name instead of using an index of 0 which would look odd in the Genoa case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1db28ec03a3ba1c2040d8a1500ae17aa9705f6e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76756 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-25soc/amd/*/root_complex: don't report root complex IOAPIC resource twiceFelix Held
Since the per PCI root IOAPIC is now reported as domain MMIO resource and the IVRS code now again probes for the IOAPIC resource on the domain device, the IOAPIC resource doesn't need to be reported as resource of the northbridge PCI device any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8604bd321ec4239076b1be99dca095e47f8b75a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76600 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-25soc/amd/common/acpi/ivrs: probe IOAPIC device on domain deviceFelix Held
This reverts commit e33d253793f6 ("soc/amd/common/block/acpi/ivrs: fix missing IOAPIC[1] error"). Now that the per PCI root domain IOAPIC MMIO resource is reported on the domain device, we can again probe the resource on the domain device instead of the northbridge PCI device in that domain. This will make the IVRS code compatible again with the work in progress Genoa SoC support. TEST=Linux doesn't complain about the IOAPIC[1] missing in the IVRS on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib861b19d798fc8ee6603e8803d8d1939be08d275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76659 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-25soc/amd/common/data_fabric/domain: report non-PCI MMIO resourcesFelix Held
Call read_non_pci_resources from amd_pci_domain_read_resources to tell the resource allocator about the non-PCI MMIO regions within the data fabric MMIO regions so that the allocator won't place any PCI MMIO in the same areas. TEST=On Mandolin 3 new non-PCI resources get reported to the allocator: avoid_fixed_resources: DOMAIN: 0000 04 base fd100000 limit fd1fffff mem (fixed) avoid_fixed_resources: DOMAIN: 0000 05 base fd000000 limit fd0fffff mem (fixed) avoid_fixed_resources: DOMAIN: 0000 20000120 base fec01000 limit fec01fff mem (fixed) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7f69b86e376e3368d4f156ccf93791cc00886489 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-25soc/amd/glinda/root_complex: add non-PCI MMIO registersFelix Held
Add the SoC-specific non-PCI MMIO register list. PPR #57254 Rev 1.52 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I29b4ef947776ab8a6c215c1a5204769a9f61e6fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/76598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-25soc/amd/phoenix/root_complex: add non-PCI MMIO registersFelix Held
Add the SoC-specific non-PCI MMIO register list. PPR #57019 Rev 3.05 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6f57df6ca09f1583409f6c4e68177b05b9f31def Reviewed-on: https://review.coreboot.org/c/coreboot/+/76597 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-25soc/amd/mendocino/root_complex: add non-PCI MMIO registersFelix Held
Add the SoC-specific non-PCI MMIO register list. PPR #57243 Rev 3.02 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2c5173e596f3f3f1c63165871178dbbd0e9641be Reviewed-on: https://review.coreboot.org/c/coreboot/+/76596 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-25soc/amd/cezanne/root_complex: add non-PCI MMIO registersFelix Held
Add the SoC-specific non-PCI MMIO register list. PPR #56569 Rev 3.04 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id99c64c172481984306814980a1ddf0b2d535413 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-25soc/amd/picasso/root_complex: add non-PCI MMIO registersFelix Held
Add the SoC-specific non-PCI MMIO register list. PPR #55570 Rev 3.18 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If7bfcdd9b70b71fe6aedcab3694698967d48e18e Reviewed-on: https://review.coreboot.org/c/coreboot/+/76554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-25soc/amd/common/root_complex: add function to report non-PCI resourcesFelix Held
Introduce the common read_non_pci_resources function to read the base address of the non-PCI resources within the MMIO regions configured in the data fabric registers and pass that info to the resource allocator. Each SoC will need to provide implementations for get_iohc_misc_smn_base and get_iohc_non_pci_mmio_regs in order for read_non_pci_resources to know the SoC-specific base addresses, register offsets and MMIO region sizes. In case of SoCs with only one PCI root domain, the domain parameter of get_iohc_misc_smn_base will be unused, but in the case of SoCs with more than one PCI root domains, this parameter will be used by the SoC-specific code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If9aca67fa0f5a0d504371367aaae5908bcb17dd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-25soc/intel/meteorlake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I0f9299d4b7417efac0d5fba39d40b97d6c3a1926 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-25soc/intel/xeon/spr: Improve RMT configurationNaresh Solanki
Set AllowedSocketsInParallel to 1 for RMT builds. This help in associating any failures encountered during RMT run with the corresponding Socket/MC/DIMM. Intel recommended setting EnforcePopulationPor to 1 for RMT runs for debugging failures if any. Change-Id: Ie2301368e9470cc23171c3c4eca9fe978e1513d4 Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76679 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 02:41:41 +0000