| Age | Commit message (Collapse) | Author |
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Xeon-SP supports MMIO high range, a.k.a. MMIO range above 4G. FSP will
assign domain MMIO high windows from this range.
However, there will be unassigned parts among these high windows for
non-domain device usage (e.g. misc devices belonging to an IIO stack
but not belonged to any PCIe domains under that stack). This will cause
segmentation in MTRR UC coverage.
For example, in SPR-XCC where only CPM0/HQM0 are supported and
instantiated to PCIe domains, MMIO ranges are still reserved for
CPM1/HQM1. See more at src/soc/intel/xeon_sp/spr/ioat.c.
Reserve MMIO high range as a whole under domain0/00:0.0. During MTRR
calculation, this reservation will connect the discontinued domain MMIO
high windows together to form one continuous range, and save MTRR
register usage from inadequacy.
This change is initially raised for SPR but could be effective for GNR
as well.
TESTED = Build and boot in intel/archercity CRB, MTRR register usage
decreases from 7 to 3 in 2S system.
TESTED = Only setting MTRR for below 4GB ranges test fails with
LinuxBoot on SPR (through x86_setup_mtrrs_with_detect_no_above_4gb)
tsc: Detected 2000.000 MHz processor
last_pfn = 0x2080000 max_arch_pfn = 0x10000000000
x86/PAT: Configuration [0-7]: WB WC UC- UC WB WP UC- WT
WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 129024MB of RAM.
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at arch/x86/kernel/cpu/mtrr/cleanup.c:978 mtrr_trim_uncached_memory+0x2b9/0x2f9
...
Call Trace:
? 0xffffffff8f600000
? setup_arch+0x4bb/0xaed
? printk+0x53/0x6a
? start_kernel+0x55/0x507
? load_ucode_intel_bsp+0x1c/0x4d
? secondary_startup_64_no_verify+0xc2/0xcb
random: get_random_bytes called from init_oops_id+0x1d/0x2c with crng_init=0
---[ end trace 0e56686fd458f0c5 ]---
update e820 for mtrr
modified physical RAM map:
modified: [mem 0x0000000000000000-0x0000000000000fff] reserved
...
modified: [mem 0x00000000ff000000-0x000000207fffffff] reserved
last_pfn = 0x6354e max_arch_pfn = 0x10000000000
Memory KASLR using RDRAND RDTSC...
x2apic: enabled by BIOS, switching to x2apic ops
Using GB pages for direct mapping
...
Initmem setup node 0 [mem 0x0000000000001000-0x000000006354dfff]
DMA zone: 28769 pages in unavailable ranges
DMA32 zone: 19122 pages in unavailable ranges
BUG: unable to handle page fault for address: ff24b56eba60cff8
BAD
Oops: 0000 [#1] SMP NOPTI
CPU: 0 PID: 0 Comm: swapper Tainted: G W 5.10.50 #2
...
Call Trace:
? set_pte_vaddr_p4d+0x24/0x35
? __native_set_fixmap+0x21/0x28
? map_vsyscall+0x35/0x56
? setup_arch+0xa00/0xaed
? printk+0x53/0x6a
? start_kernel+0x55/0x507
? load_ucode_intel_bsp+0x1c/0x4d
? secondary_startup_64_no_verify+0xc2/0xcb
CR2: ff24b56eba60cff8
---[ end trace 0e56686fd458f0c6 ]---
RIP: 0010:fill_pud+0xa/0x62
...
Kernel panic - not syncing: Attempted to kill the idle task!
---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]---
Change-Id: Ib2a0e1f1f13e797c1fab6aca589d060c4d3fa15b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83538
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add definitions for the GPIO pins on Panther Lake SoC,
as well as GPIO IRQ routing information and defines for ACPI ASL.
For now, add the following GPIO communities and GPIO groups:
Comm. 0: GPP_V, GPP_C
Comm. 1: GPP_F, GPP_E
Comm. 3: CPUJTAG, GPP_H, GPP_A, VGPIO3
Comm. 4: GPP_S
Comm. 5: GPP_B, GPP_D, VGPIO
ref doc:
- PT EDS vol2
- Panther Lake H GPIO Implementation Summary (#817954)
BUG=b:348678529
TEST=Verify on Intel Silicon platform for PTL using google/fatcat
mainboard. Note that these GPIO changes cannot be verified along as
they are merely data structure and defines for the SOC. With the
GPIO ASL, we should see the following GPIO instances under
/sys/bus/acpi/devices when booting to OS:
INTC10BC:00/ INTC10BC:01/ INTC10BC:02/ INTC10BC:03/ INTC10BC:04/
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Based on DOC #767454 (public) version 1.2. Allows to boot the
HARDKERNEL ODROID H4+ with N97 SoC. Without this patch the MCH ID
was not recognized and the SA driver did not pick up the stolen
ranges, causing the PCI MMIO allocation to be placed in the stolen
areas.
TEST=Boot HARDKERNEL ODROID H4+ with N97 SoC to Ubuntu 23.04.
Change-Id: I0fbdb12c6411e4109e68a13960b4570701629bc9
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84212
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Move the `BUILDING_WITH_DEBUG_FSP` Kconfig option from SoC-specific
files to the FSP2_0 driver Kconfig to avoid duplication. Also slightly
improves the option's prompt and help text.
TEST=Built and booted google/rex successfully.
Change-Id: I5c3dce59c396f6c1665a3ed1b8c1bb5df0f5a8d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch adds a new Kconfig option `FSP_PUBLISH_MBP_HOB` to
control the creation of the ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP.
Disabling this option can improve boot time on platforms that
do not utilize the MBP HOB, such as ChromeOS devices.
The option is disabled by default on ChromeOS and enabled
by default on other platforms.
On ADL-P based platforms, this option is forced to be enabled
as ADL-P FSP relies on MBP HOB for ChipsetInit version for
ChipsetInit sync.
Removed SoC specific implementation of `FSP_PUBLISH_MBP_HOB` config
from MTL and TGL config file.
TEST=Tested on ADL-P and ADL-N platforms. Verified that MBP HOB is
created when `FSP_PUBLISH_MBP_HOB` is enabled and not created when
it is disabled.
Also verified that the system boots successfully in both cases.
Change-Id: I21da00259c0b9bcca6f545291a6259e9cce8d900
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Signing is performed with test keys by default, set
CONFIG_SIGNING_KEYS_DIR to a non-empty value to use other keys.
Depending on the version of the Talos II firmware this alone might not
allow booting because coreboot replaces only part of the stock firmware
and its newer versions enable secure boot by default (not to be confused
with SecureBoot in EFI). The signing performed in this commit is still
a prerequisite and might as well be done on its own. Fixing operation
with newer stock firmware will be done in a follow-up change.
Change-Id: Id88baef5ecb1f8ffd74a7f464bbbaaaea0ca643d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Add specific virtual wire mapping structure for:
- First pad group does not starts with bit position 0.
- vw_index and position are not continuous in between groups within a
community.
BUG=
TEST=boot to OS and use iotools to read the registers that use 16-bit
port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group
ID field.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I986d4f4fe59b110e5075cab8742dfe8b336d034b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add support to configure GPIOs to pull for external interrupts (EINT).
BUG=b:334723688
TEST=Talk with Ti50 TPM using IRQ flow.
Change-Id: Ibeb2dafcd9909b4afbfa81728700718f01d3818f
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84026
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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$ build/cbfstool build/coreboot.rom print
FMAP REGION: COREBOOT
Name Offset Type Size Comp
cbfs_master_header 0x0 cbfs header 32 none
fallback/romstage 0x80 stage 18495 LZ4 (30096 decompressed)
fallback/ramstage 0x4940 stage 24288 LZMA (61240 decompressed)
config 0xa880 raw 1324 LZMA (3308 decompressed)
revision 0xae00 raw 726 none
build_info 0xb100 raw 122 none
(empty) 0xb1c0 null 347108 none
header_pointer 0x5fdc0 cbfs header 4 none
Change-Id: I8541aa6f1429ed6143830ed11c47c150183ddf0d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67064
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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iasl refuses to perform an arithmetic computation in a QWordMemory
parameter and fails with the following error.
dsdt.asl 2149: 0x4010800000, ((0x4010800000 + 0x10000) - 1), 0x0,
Error 6051 - ^ Address Min is greater than Address Max
This commit replaces the arithmetic with the result to define
IOM_BASE_ADDR_MAX.
BUG=b:348678529
TEST=Build for google/fatcat mainboard.
Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f16
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84216
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I62d0e324329fdde599e67efb23f813e3b3c650ef
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84199
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to enable GPE1 block.
This will include GPE1 blocks to FADT with their info.
BUG=362310295
TEST=boot to OS and check that FADT table include GPE1.
FADT should have:
GPE1 Block Address : 00001810
GPE1 Block Length : 18
GPE1 Base Offset : 80
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84103
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch refactors ITSS related SoC specific macros by consolidating
them into a common itss.h file. This improves code maintainability and
reduces redundancy as each SoC previously defined the same macros.
Specific changes include:
- Move SoC specific ITSS macros into intelblocks/itss.h.
- SoC code now includes intelblocks/itss.h instead of the SoC-local
soc/itss.h.
- Drop soc/itss.h from static ASL files.
- Delete soc/itss.h from all SoC locals except Apollo Lake and
Sky Lake.
TEST=Able to build and boot google/hatch, google/xol and google/karis.
Change-Id: I6461dc93b0d21bec5429075bc26435bae3754d74
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84183
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Details:
- Add (POWER_CTL) – Offset 0x1fc required bits.
Change-Id: Ief7f514c5837cb2f7c3158b67c4f6fed86796e71
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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This patch removes the GPIO_IRQ_START and GPIO_IRQ_END definitions
from itss.h for Alder Lake, Cannon Lake, Elkhart Lake, Jasper Lake,
Meteor Lake and Tiger Lake. These definitions are no longer needed.
TEST=Able to build and boot google/xol and google/karis.
Change-Id: I60a08ba2c894fd1c1af6c6aef3ddc4a33ec63e76
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84182
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change removes the unused pch_handle_sideband() function from the
Meteor Lake platform code.
TEST=Able to build and boot google/rex.
Change-Id: Idd14748aa1d917d6e88d738541a737c04a2c6a15
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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Change-Id: I569b9a69add341bcefe6bd5356b01a95a4e97286
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
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Change-Id: I5cd04972936c14d92295915fad65c7a45a8108d9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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De-assert PERST# at romstage to reduce the waiting time in ramstage.
Before
```
[INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done,
de-assert PERST# now
[INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries)
```
After
```
[INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done,
de-assert PERST# now
[DEBUG] wait_perst_asserted: 457568 us elapsed since assert PERST#
[DEBUG] wait_perst_done: 163413 us elapsed since de-assert PERST#
[INFO ] mtk_pcie_domain_enable: PCIe link up success (1 tries)
```
BUG=none
TEST=boot from NVMe
Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84118
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Even we assert PRSET# early to save the delay between PERST# assertion
and de-assertion. MediaTek PCIe driver still takes 47ms waiting for PCIe
link up. (1ms delay for each try)
```
[INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries)
```
Refactor common/pcie.c and add mtk_pcie_deassert_perst for early PCIe
reset. So we can de-assert PERST# at early stage to improve the boot
time.
BUG=b:361728592
TEST=emerge-cherry coreboot
Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84117
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
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Change-Id: Ida4461de6275bdd314f5cba441d3ff631d570305
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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CAPID_A, BDSM and BGSM registers may not exist on specific platform,
this patch add `HAVE_CAPID_A_REGISTER` and `HAVE_BDSM_BGSM_REGISTER`
to select them.
Change-Id: I4d1197b8b1071aefc2ea1ed2f707d769aabab5e4
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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Add EARLY_INIT_PCIE_RESET for early PERST# de-assertion.
BUG=b:361728592
TEST=emerge-cherry coreboot
Change-Id: I7ab85694e85a4c3f77fefc22efe16734c347a716
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
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mtk_pcie_reset can be shared with MT8196. So move it to common/pcie.c.
BUG=b:361728592
TEST=emerge-cherry coreboot
Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Use clr/setbits32p to make code cleaner.
BUG=none
TEST=emerge-cherry coreboot
Change-Id: Id99d5aafdf4d687dbe3a0bef29b148537cf58dd8
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
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Currently pcie.c is built into ramstage only, where DEVTREE_CONST is an
empty macro, so there's no problem with that. However, if we would like
to include that file in pre-ramstage, then DEVTREE_CONST would be
'const', leading to the following build error:
```
src/soc/mediatek/common/pcie.c:104:26: error: assignment discards
'const' qualifier from pointer target type [-Werror=discarded-qualifiers]
104 | root_dev = pcidev_path_on_root(devfn);
| ^
```
BUG=none
TEST=emerge-cherry coreboot
Change-Id: Ia7c95424019ec0dca50bbc6be7f81b6180d06d6e
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84113
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Change-Id: I46021accacbb911d7a7ecfdbb52973a7da78f36e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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- Add Kconfig: SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID.
- Change cpu_port field to 16-bit width if the Kconfig is set.
BUG=none
TEST=boot to OS and use iotools to read the registers that use 16-bit
port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group
ID field. The bit 15:8 of the returned port ID value should be 0xF2
instead of zero.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83981
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previously, `early_graphics_stop()` was skipped unconditionally if
`CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)` was enabled. This led
to overlapping screens when CSE sync was not triggered in ramstage,
as both the eSOL message and the firmware splash screen would be
displayed.
This change refactors the condition for calling `early_graphics_stop()`
to ensure it is only skipped if a CSE firmware update is actually
required *and* `CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)` is set.
This allows eSOL to display its message during CSE sync, but tears
down early graphics programming in other cases to prevent overlapping
screens.
Additionally, this change ensures that `early_graphics_stop()` is the
last function called by the romstage to guarantee proper cleanup.
BUG=b:362895813
TEST=Able to boot google/tivviks_ufs without overlapping screens.
Change-Id: Idc01bfc8963d65fcb0441300e7c9267eaaefefb9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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To support Widevine DRM, enable VBOOT_DEFINE_WIDEVINE_COUNTERS.
BUG=b:357976379
TEST=emerge-rauru coreboot
BRANCH=none
Change-Id: I3760c30b175338165f8e11b59c7cfa830070a19e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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LTO does not like that assert on a constant, so use the more appropriate
static assertion.
Change-Id: I52094ec825fcec56a9b9fb6b9abc58644c2bf9cb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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On xeon-sp this is a zero length array. With GCC LTO this triggers the
stringop-overread warning. To work around this change the signature of
the function from an array to a pointer.
Change-Id: Ieee6e9bddc4e738eb560dd0e69dc3087ac9f5da6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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A DDR5 DIMM internally has two channels each of width 32 bit.
But the total physical channel width is 64 bit.
This is the same fix as be5dc3daa "soc/intel/alderlake: Configure DDR5
Physical channel width to 64"
Building with GCC LTO cought this buffer overflow when assigning SPD
addresses to a buffer.
Change-Id: Ief6018e4dcce6b26804ff864cdfe116f0f90d545
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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There is no struct device *dev equivalent of this function. Clang LTO
warns about mismatching types.
Change-Id: I22c8c9b9f350c53469a5d386db211969c8a41cf0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The driver sets ACPI names for PCIe root ports and its subordinate
devices, and fill SSDT for them accordingly. SPR PCIe root port
devices are initially supported.
TEST=Build and boot on intel/archercity CRB
Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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This updated microcode fixes the recent voltage issues on the Raptor
Lake S platform. Intel provided this specific microcode just as an
attachment [1]. Thus, we've uploaded it to our own blobs repository,
which is why the path is changed.
Microcode signature:
sig 0x000b0671, pf_mask 0x32, 2024-07-18, rev 0x0129
[1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/81
Change-Id: I6d01e38476b0d3dc5281ea1d85bac87043d122dd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84132
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The underlying IMD function already returns an integer which indicates
success or failure.
This removes the need to have initialized variables that need to be
checked for NULL later. In some cases this actually adds the appropriate
check for returned values.
Dying is appropriate if cbmem is not found as it is essential to the
bootflow.
Change-Id: Ib3e09a75380faf9f533601368993261f042422ef
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add USB host function support.
TEST=read usb data successfully.
BUG=b:317009620
Signed-off-by: Mingjin Ge <mingjin.ge@mediatek.corp-partner.google.com>
Change-Id: Ia4efcddac9bf5e04e688648a5c22384075a0b026
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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According to RDC#646929 Power Map, there are two expected values of
VccInAuxImonIccImax and the value has to align with HW design.
But in current code, vccin_aux_imon_iccmax is hard code to 27000 (27A),
hence, provide a config for projects modification.
BUG=b:330117043
BRANCH=firmware-nissa-15217.B
TEST=Modify the register and add a printk to output a debug message
to observe whether the value is changing as expected.
Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
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This patch eliminates the LPC_IOE_COMA_EN and LPC_IOE_COMB_EN IO enables
from the io_enables variable in the pch_early_iorange_init() function
because lpc_io_setup_comm_a_b() is intended to activate legacy COM
ports like COM-A (0x3F8 - 0x3FF) and COM_B (0x2F8 - 0x2FF).
These COM ports are being activated unconditionally, which is
undesirable for the Intel Alder Lake platform and causes traffic over
the IO bus.
As a result, this code is being removed and platforms that select
DRIVERS_UART_8250IO can activate legacy COM ports.
BUG=b:354066052
TEST=Able to boot google/redrix to the operating system and confirm
that there was no traffic over legacy COMs while being monitored
using the eSPI analyzer.
Change-Id: I7a6e38bd151f823d37c07ee89a800489122cc209
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84080
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes the SOC_INTEL_GFX_MBUS_JOIN configuration option.
Support for fast modeset joining has been added to the mainline i915
kernel driver (https://patchwork.freedesktop.org/series/130480/),
making this coreboot-specific workaround unnecessary.
BUG=b:291885733
TEST=Successful build and boot of google/marasov with single and dual
displays, no redundant boot splash.
Change-Id: I53c08a0e7a40b24db7cc910c5b9adc2376a9bb17
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paz Zcharya <pazz@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
|
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Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
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Now that the PSP SMI handler for flash access is also implemented for
the PSP generation 1, the PSP SMI handler can be added to the
Stoneyridge code too. The actual PSP SMI handler code will only be added
to the build when SOC_AMD_COMMON_BLOCK_PSP_SMI is selected which isn't
the default case, so this patch doesn't change the current behavior
unless that option is also selected. This SMI handler mainly added for
completeness since the PSP firmware blobs released for Stoneyridge are
probably lacking the corresponding PSP-side code to send the PSP SMI to
the host. At least if I remember correctly the PSP bootloader release
for Stoneyridge has the ability to load the secure OS removed and since
the secure OS is the runtime component, some part of that is probably
what's sending those SMIs to the host. If there are some other PSP
bootloader builds that support loading the secure OS, this patch might
still be useful for those.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I78944e2de86bc1e8e277d22a7a8da517622f49a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84077
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that we have the local psp_smi_flash.h header, move the
psp_smi_spi_* function prototypes there.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I12cbbabf6a960836fe0c5dc1424c08550cb66a7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84068
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Use the uint[8,16,32,64]_t data types everywhere instead of a mixture of
uint[8,16,32,64]_t and u[8,16,32,64] data types for consistency.
Suggested-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I36151ecf94619afaf690dbb73834fcff3c51fdac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Add helper functions to send the PSP commands to query the fTPM and
PSP capability bits as well as the HSTI state. All SoCs using any PSP
generation support the MBOX_BIOS_CMD_PSP_FTPM_QUERY command and some
generation 1 and all generation 2 PSP SoCs support the
MBOX_BIOS_CMD_HSTI_QUERY command, so implement those two in the common
psp.c. Only PSP generation 2 supports the MBOX_BIOS_CMD_PSP_CAPS_QUERY
command, so implement that one in psp_gen2.c.
This code is ported and modified from
github.com/teslamotors/coreboot/tree/tesla-4.12-amd
Document #54267 revision 1.06 was used as reference for the 1st PSP
generation and document #55758 revision 2.04 was used for the 2nd PSP
generation.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4e17f994fb332690828c55742262da793e297d99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Rename MBOX_BIOS_CMD_PSP_QUERY to MBOX_BIOS_CMD_PSP_FTPM_QUERY to bring
it a bit more in line with document #55758 revision 2.04 and to avoid
confusion when another command is added in a follow-up patch. In
document #54267 revision 1.06 this command is called
MBOX_BIOS_CMD_PSP_QUERY and in document #55758 revision 2.04 it's called
MBOX_BIOS_CMD_FTPM_QUERY, so just name it MBOX_BIOS_CMD_PSP_FTPM_QUERY
in coreboot which should be the least confusing name for it that still
somewhat aligns with the documentation.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id085b34363d39528bd125dfb77596d3ed13b6fa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84065
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Implement the request buffer access functions for the PSP generation 1
case. In this case, only the SMI_TARGET_NVRAM is supported, so always
return this target NV ID and always return true in the validity checks
which in the PSP generation 2 case check if the target NV ID is valid.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7e141f846e930bab6972a281745c0180ac52c291
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84064
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
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The request buffer data structures differ between the PSP generation 1
and 2 in the way that the generation 2 added the 64 bit target NV ID
field right at the beginning of the request buffer data structures. In
order to make the data structure definitions common, remove the
target_nv_id struct element via the preprocessor in case the
SOC_AMD_COMMON_BLOCK_PSP_GEN2 option isn't selected. Since the request
buffer data structures are now common for both generations, also remove
the 'v2' from the struct names.
Document #54267 revision 1.06 was used as reference for the 1st PSP
generation and document #55758 revision 2.04 was used for the 2nd PSP
generation.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe0bd2d8e6a5c39cc67a49e7bb3a51ce0900a39a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Factor out the code to access the request buffer into PSP generation
specific file. This is a preparation for adding PSP SMI flash access
support for the PSP generation 1 which has a slightly different request
buffer layout.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8e18f7ea53592d9fd413ad56e8d137cfc13ad5d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The existing comment on the mbox_default_buffer struct was outdated and
didn't reflect the current state, so rework it to keep it a bit more
generic and also add the document number for the newer generations of
CPUs. To better document which commands use non-default buffers, add the
names of the commands using the non-default buffers to those buffer
struct definitions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I510d953217240243392e8a415358524257bd28b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Add I2C controller driver.
TEST=build pass
BUG=317009620
Change-Id: I617ad8a43ce8b492b1a0e5dc06c1f0ffe7d92b5e
Signed-off-by: ot_hao.han@mediatek.corp-partner.google.com
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83927
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Add watchdog support for MT8196.
TEST=build pass and WDT uart log
BUG=b:317009620
Change-Id: I9d5e71aa27d469855c2bd65abc5309d69a018750
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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- Turn off L2C SRAM and reconfigure as L2 cache:
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.
- Configure DMA buffer in DRAM:
Set DRAM DMA to be non-cacheable to load blob correctly.
TEST=build pass, register(disable_l2c) read ok
BUG=b:317009620
Change-Id: I6a3cb63d3418f085f5d8d08b282dd59ea431c294
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83925
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
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Refactor mmu operation by
- moving mtk_soc_disable_l2c_sram to l2c_ops.c
- keeping mtk_soc_after_dram in mmu_cmops.c
Change-Id: I14bd8a82e0b5f8f00ce2b52e5aee918e130912d4
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83937
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add NOR-Flash drivers for flash read/write.
TEST=read nor flash data successfully.
BUG=b:317009620
Change-Id: Id0a19f0520020f16c4cf9d62da4228a5b0371b91
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83923
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To reduce duplicate pad_func of MediaTek SoCs, move the pad_fun to a
common directory.
TEST=Build pass
BUG=b:317009620
Change-Id: I145233ef887a38251e8fc129b8357f236c5f7a2b
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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When the config of MCU firmware blob such as CONFIG_SPM_FIRMWARE is
non-empty, we should always expect the file to exist. Similarly, since
the device is unlikely to boot without the DRAM blob (assuming MRC_CACHE
doesn't contain valid memory training data), dram.elf should always
exist as well.
Therefore, remove the check for the existence of the blobs. Build would
fail if any of the blobs is missing.
Change-Id: I755e7c5a70b34b0c3d3915ab339c65263688aad7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84053
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add GPIO driver for other modules to control GPIO pins.
TEST=build pass
BUG=b:317009620
Change-Id: I6d1e6ef17660308c8de908697ffba6b5f17ff9ae
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83922
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To reduce duplicate gpio_base.h in each SoC folder, move gpio_base.h to
mediatek/common folder.
TEST=Build pass
BUG=b:317009620
Change-Id: I815df8a3083cf04b821165ec834ca98ee71a0c78
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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TEST=build pass
BUG=317009620
Change-Id: I5dffdb9f3e4e7e0d49209e6012893cd246948ee8
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83987
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
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Some targets cannot be supported by clang as clang generates slightly
larger binaries which the hardware won't accept. This is usually the
case with CONFIG_CHROMEOS.
Change-Id: I88cf8ce16fb6c61c19d615e396f5871179b06fc8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69747
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These field defines are SOC-specific. The AUX bias virtual wire field
positons are shifted in PTL.
In MTL SOC and older:
7:0 GROUP_ID Group ID in PCH GPIO
10:8 BIT_NUM Data bit Position in PCH GPIO
23:16 VW_INDEX VW Index in PCH GPIO
In PTL SOC:
15:0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID
18:16 BIT_NUM Data bit Position in PCH GPIO
31:24 VW_INDEX VW Index in PCH GPIO
BUG=361048817
TEST=boot to OS and use iotools to read AUX Bias Ctrl register to
verify the group ID, bit number, and vw index.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I0f9c895590465b2f539c91834cf331fcd7efa996
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83980
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
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Extend support for CrashLog to Intel Jasperlake based platforms.
This commit is based on 15cbc3b5996ae64aff2e4741c4c3ec3d7f5cc1a7,
originally reviewed on https://review.coreboot.org/c/coreboot/+/49943.
BUG=b:354834461
TEST=CrashLog can be enabled in Kconfig for Jasperlake based platforms
and can generate a BERT table, if enabled.
Change-Id: Ia18a79d8de849d556b4b8fd0e6b43090311eb23f
Signed-off-by: Jędrzej Ciupis <jciupis@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
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This patch extends the eSOL implementation on Alder Lake to render text
messages during late CSE sync (from ramstage).
Currently, the eSOL is limited to the early boot phase (until romstage)
and only displays FSP-M memory training warnings or messages during
early CSE sync (at romstage).
Platforms like Nissa/Nirul and Trulo, which use CSE sync from ramstage,
cannot display any eSOL messages, resulting in a brief black screen
during CSE firmware updates.
This patch implements the following logic to scale eSOL for late CSE
sync (at ramstage) without recompiling eSOL code for ramstage:
1. During boot, check if the MRC cache is available. This indicates the
need for memory/DRAM training and triggers an eSOL message.
2. For CSE lite SKUs (applicable to CrOS), leverage the
`is_cse_fw_update_required` API to check if the current CSE RW
firmware version differs from the CBFS metadata file version.
If so, trigger an eSOL message indicating a CSE sync is required.
3. If either condition #1 and/or #2 is true, the AP firmware renders
an eSOL text message using LibGfxInit for the Alder Lake platform.
BUG=b:359814797
TEST=eSOL text messages are displayed during CSE sync and FSP updates.
tirwen-rev3 ~ # elogtool list
0 | ... | Log area cleared | 4088
1 | ... | Early Sign of Life | MRC Early SOL Screen Shown
1 | ... | Early Sign of Life | CSE Sync Early SOL Screen Shown
2 | ... | System boot | 197
3 | ... | Memory Cache Update | Normal | Success
4 | ... | System boot | 198
5 | ... | Firmware Splash Screen | Enabled
Change-Id: I1c7d4475ed5cf6888df1beebab0641ee4203b497
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83975
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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This patch prevents the eSOL screen from being wiped out on Alder Lake
platforms that use late CSE sync (from ramstage). This allows the eSOL
text message to remain visible until ramstage.
Currently, the eSOL only functions during the early boot phase (until
romstage), so platforms like Nissa/Nirul and Trulo, which use CSE sync
from ramstage, cannot display any eSOL messages to the user.
A future patch will ensure the eSOL remains relevant for CSE sync in
ramstage, but this patch is necessary to avoid tearing down the IGD text
mode when exiting romstage.
BUG=b:359814797
TEST=eSOL text mode is not torn down when exiting romstage.
Change-Id: I81548b4057ab95ce3da0dbc69703977baf0581f1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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This enables SOC_QDF_DYNAMIC_READ_PMC and adds pmc_dump_soc_qdf_info
to report_cpu_info to dump QDF information from bootblock.
Change-Id: Iaf6f46cd9be831dde345c3b3728cd66145746d68
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com>
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This adds pmc_ipc to bootblock if SOC_INTEL_COMMON_BLOCK_PMC is enabled.
The good place to report SoC QDF can be report_cpu_info in bootblock.
QDF read is done by PMC IPC Command, so this adds pmc_ipc to bootblock
to enable calling pmc_dump_soc_qdf_info.
Change-Id: Id0391eae48fc53cd652acd09e6380ca6802eaf88
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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`CONFIG_DCACHE_RAM_SIZE' is not necessarily a multiple of way size. As
a result, when the `div' instruction is called to compute the needed
number of ways, there could be a remainder. When there is, one extra
way should be added to cover `CONFIG_DCACHE_RAM_SIZE'.
BUG=b:360332771
TEST=Verified on PTL Intel reference platform
Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83982
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit 16ab9bdcd578612bb3822373547f939eb90afd82 ("soc/intel/common:
Calculate and configure SF Mask 2") breaks the computation of the
number of ways and as result, all the derived masks. It results in MSR
such as `IA32_L3_MASK_1' to be improperly programmed yielding
unpredictable NEM issues such as hangs.
Indeed, this commit has introduced a backup of 0x1 into %edx before
comparing the requested cache-as-RAM size against the way size. When
the requested cache-as-RAM is larger, it reaches the second part of
the algorithm which computes the necessary number of ways to fit the
requested cache-as-RAM.
This algorithm uses the `div' instruction. Per specification, the div
instruction divides the 64 bits combination of %edx and %eax register.
Since 0x1 got backed up in %edx and assuming a
`CONFIG_DCACHE_RAM_SIZE' of 0x200000, we end up dividing 0x100200000
by the way size instead of 0x200000 which result in a necessary number
of ways of 4098 for a way size of 0x100000.
This commit clears the %edx register before calling the `div'
instruction.
BUG=b:360332771
TEST=Verified on PTL Intel reference platform
Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83948
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Intel's PMC CrashLog size in legacy mode is expressed in DWORDs and
therefore needs to be explicitly recalculated to bytes.
BUG=None
TEST=Built and checked the size in logs
Change-Id: I2678d537439c24fbd10aa3ceffee63c9a849d28b
Signed-off-by: Jędrzej Ciupis <jciupis@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
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This patch replaces the SoC-specific config option
`SOC_INTEL_PANTHERLAKE_DEBUG_CONSENT` with the generic
`SOC_INTEL_COMMON_DEBUG_CONSENT`.
TEST=Able to build and boot google/fatcat without any functional impact
while debugging.
Change-Id: I36bbe14d02654ed9dbda21df0d9a6a6769b87754
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83962
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch replaces the SoC-specific config option
`SOC_INTEL_METEORLAKE_DEBUG_CONSENT` with the generic
`SOC_INTEL_COMMON_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot google/rex0 without any functional impact
while debugging.
Change-Id: I657d20a38e15eee333a4e45c0c600736148173d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83961
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch replaces the SoC-specific config option
`SOC_INTEL_ALDERLAKE_DEBUG_CONSENT` with the generic
`SOC_INTEL_COMMON_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot google/redrix without any functional impact
while debugging.
Change-Id: I9a9c81b72d707f5ed2e1a53c139ee22be0e30068
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This patch drops the SoC-specific config option
`SOC_INTEL_TIGERLAKE_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot google/volteer without any functional
impact while debugging.
Change-Id: I3e96b20e7e8b3ce3c2e4884abd315a5cc55fe71d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This patch drops the SoC-specific config option
`SOC_INTEL_JASPERLAKE_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot google/dedede without any functional
impact while debugging.
Change-Id: I3e7abaf5fb3a0d5528041af5ce767a15fc738870
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83960
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch drops the SoC-specific config option
`SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot intel/elkhartlake_crb without any
functional impact while debugging.
Change-Id: Idb8db7230c432792e742218d41d891c529b2114f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83959
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch drops the SoC-specific config option
`SOC_INTEL_CANNONLAKE_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot google/hatch without any functional impact
while debugging.
Change-Id: Ifad11652b5fa6ff14f713f55a721cdbbfbfde471
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83958
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I15dfd5ed0541352930c3b70252b3e536ad1e6efd
Signed-off-by: Michael Strosche <michael.strosche@gmail.com>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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This patch adds a generic config option, SOC_INTEL_COMMON_DEBUG_CONSENT,
to control the debug interface on Intel SoCs. This eliminates the need
for SoC-specific config options like SOC_INTEL_<SOC_NAME>_DEBUG_CONSENT.
Default values are provided for various debug types:
- 0: Disabled
- 1: Enabled (DCI OOB + [DbC])
- 2: Enabled (DCI OOB)
- 3: Enabled (USB3 DbC)
- 4: Enabled (XDP/MIPI60)
- 5: Enabled (USB2 DbC)
- 6: Enabled (2-wire DCI OOB)
- 7: Manual
Specific SoCs can override the SOC_INTEL_COMMON_DEBUG_CONSENT value
using SoC config override methods.
TEST=Able to build google/rex.
Change-Id: I84ad03f0ffe5da4bc53c665489c430fe9b65ede7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch selects the SOC_INTEL_COMMON_BASECODE option for Elkhart
Lake so that future patches can incorporate the common code debug
feature with it.
TEST=Able to build the EHL platform.
Change-Id: I71d95352fe627a7f1912f802aa971ad1ebbbead7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
4. Ref: Processor EDS documents
Panther Lake U/H 12Xe/H 4Xe External Design
Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and
Volume 2 of 2 #813030
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Replace 'is_domain0(dev_get_domain(dev))' with 'is_dev_on_domain0(dev)'
which is a helper function that does exactly the same, but slightly
simplifies the call.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8b0c52a9176288039e6414a09c3fe0662db79e4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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The previous implementation incorrectly assumed that the presence of a
UFS device implied the availability of the ISH partition. This is not
always true, especially on Alder Lake platforms where ISH may be
enabled by default even without UFS.
This patch fixes the issue by directly checking for the presence of the
ISH device to determine if the ISH partition is available.
BUG=b:359440547
TEST=1. Able to dump the ISH version with UFS device:
```
tirwen-rev3 ~ # cbmem -c -1 | grep ISH
[DEBUG] ISH version: 5.4.2.7780
```
2. Able to dump the ISH version with eMMC device:
```
trulo-rev1 ~ # cbmem -c | grep ISH
[DEBUG] ISH version: 5.4.2.7780
```
Change-Id: I411e36606c0697f91050af40e0636f7c64810e95
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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If a root port doesn't use a clock request pin, we shouldn't check if
this pin number, which defaults to 0 when not set, is already used. This
fixes the following spurious warning that was previously printed for
each external PCIe port which has the 'PCIE_RP_CLK_REQ_UNUSED' flag set
and didn't set 'clk_req' to some unused clock request pin number:
Found overlapped clkreq assignment on clk req 0
Tested on the cw-al-4l-v2.0 mainboard that uses an Alder Lake N100 SoC
which I'm currently porting coreboot to. Also changing this for Meteor
Lake, since they have the same implementation in their romstage
fsp_params.c file
Change-Id: I3ee66ca5ed5a2d06dfb68c45a50e11eb2b93daa0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
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This patch updates the platform-specific Meteor Lake early
sign-of-life config (SOC_INTEL_METEORLAKE_SIGN_OF_LIFE) with a generic
ChromeOS eSOL config (CHROMEOS_ENABLE_ESOL) which uses the Intel FSP
uGOP driver as an underlying technology for rendering eSOL screen.
This patch does not change the binary or the system behaviour.
BUG=b:352651132
TEST=Able to build google/rex and checked the config in output.
Change-Id: Ib4589f52080229b1c83915b51272a042b7ac32cd
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83769
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch updates the early libgfx init config
(MAINBOARD_HAS_EARLY_LIBGFXINIT) used for Alder Lake SoC with a
generic CrOS/ChromeOS early sign of life config (CHROMEOS_ENABLE_ESOL)
This patch does not change the binary or the system behaviour and is
only meant to bind the early GFX initialization with a generic eSOL
config.
BUG=b:352651132
TEST=Able to build google/tivviks and checked the config in output
Change-Id: Ibc1b9190ac0e4d25f3c5517d74c9b519bc3bb349
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83841
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Remove the unused config VPD from GNR Kconfig.
Change-Id: I3fc45ba05df5fc23e326081d6ce9e53b2046464c
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82975
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Includes additional minimal code required to compile the PTL SoC
and google/fatcat mainbaord.
5. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for
PTL using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83354
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch add a new Kconfig HAVE_SPECIFIC_GPMR and use it to include
soc/gpmr.h if necessary.
Change-Id: I94797a72af75fc96ab2cacb1d46b581605a15387
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83317
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use 'enum cb_err' instead of {-1,0}.
Change-Id: Icea33ea3e6a5e3c7bbfedc29045026cd722ac23e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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We introduce two new functions to create region objects. They allow us
to check for integer overflows (region_create_untrusted()) or assert
their absence (region_create()).
This fixes potential overflows in region_overlap() checks in SMI
handlers, where we would wrongfully report MMIO as *not* overlapping
SMRAM.
Also, two cases of strtol() in parse_region() (cbfstool), where the
results were implicitly converted to `size_t`, are replaced with the
unsigned strtoul().
FIT payload support is left out, as it doesn't use the region API
(only the struct).
Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b
Ticket: https://ticket.coreboot.org/issues/522
Found-by: Vadim Zaliva <lord@digamma.ai>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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<device/mmio.h> is supposed to chain-include <arch/mmio.h>. See
`Documentation/contributing/coding_style.md` section `Headers and includes`
Change-Id: I08f7480650b42df1613994146a026bd1e12dbf66
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Change-Id: Iab7e9f3d17c87576761333c4b62c40eea5e424a5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
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Refactor EINT driver by
- Move `pos_bit_calc_for_eint` to `common/gpio_eint_v1.c` and rename to
`gpio_calc_eint_pos_bit`.
- Implement `gpio_get_eint_reg` to obtain EINT base address.
This change is prepared for the driver change in MT8196.
BUG=b:334723688
TEST=EINT works on Geralt
Change-Id: Ie53abc23971bfa39250ebd7dd48e28d6b91c5973
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83703
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. print host software ownership, SMI enable and NMI enable registers
after configuring
2. read and print GPIO configuration dword registers after writing
3. use %zu to print size_t values according to CI reporting.
Change-Id: I8820956f6db91c7bcc26b46a4361da3dfa8f77b5
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83316
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Pass the PSP NVRAM base and size to amdfwtool for all SoCs except Genoa
and Stoneyridge which don't use/support this.
If a mainboard has an section named 'PSP_RPMC_NVRAM' in its FMAP file,
the start and length of it in the flash will be passed to amdfwtool
which then adds the base and length to the corresponding type 0x54 PSP
directory table entry.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9f8a7eec68a5222be63e46173132f1c4a461b4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83815
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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This patch adds new North Peak PCI device IDs for Intel PTL-U and PTL-H.
Additionally, updates the tracehub driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Boot to OS using PTL Silicon, verify if above 4GB IMR region is
reserved.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ifa1a0a57c504e06d686e7e0826547251b456cc8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83786
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds support for specifying the CSE_RW_VERSION directly in
Kconfig.
* If `CONFIG_SOC_INTEL_CSE_RW_VERSION` is defined, its value will be
used directly as the CSE_RW version.
* Otherwise, the version will be extracted from the CSE_RW binary file
as before.
Platform prior to Intel Meteor Lake still requires to override the CSE
RW version using CONFIG_SOC_INTEL_CSE_RW_VERSION config rather reading
the CSE RW version from CSE RW partition.
BUG=b:327842062
TEST=CSE RW update successful on Karis with this patch using below
recipe:
1. Overriding the CONFIG_SOC_INTEL_CSE_RW_VERSION="18.0.5.2269"
2. Without overriding the CONFIG_SOC_INTEL_CSE_RW_VERSION=""
Platform prior to Intel Meteor Lake would be using #1 and platform
starting with Meteor Lake expected to use #2 recipe.
Change-Id: I1327c813b7aef77c65766eb9c40003bb8a71d4b6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83831
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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