summaryrefslogtreecommitdiff
path: root/src/soc
AgeCommit message (Collapse)Author
2017-04-24google/oak: Support cr50 over I2C on rowanVadim Bendebury
This patch enables TPM2 using cr50 over I2C for the Rowan board, and adds an mt8173 specific TPM IRQ polling function. The function relies on the appropriate EINT input configured to trigger the ready status on the rising edge. The cr50 TPM is on I2C address 0x50. The cr50 interrupt GPIO is also made available for use by depthcharge via the coreboot tables. BRANCH=none BUG=b:36786804 TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are configured to use IRQ flow control when talking to the Cr50 TPM. Change-Id: If6cdd0e39e4ac86538f27f322c55c329179ee084 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19364 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-24mediatek/mt8173: Add EINT supportDaniel Kurtz
Add basic support to configure GPIOs to poll for external interrupts (EINT). BRANCH=none BUG=b:36786804 TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are configured to use IRQ flow control when talking to the Cr50 TPM. Change-Id: I9d52591661a5a74ec1fd9a081f606f0a08a3a6ab Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19362 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins)
2017-04-24soc/intel/common: provide default tis_plat_irq_status() implementationAaron Durbin
On Intel platforms utilizing the CR50 TPM the interrupts are routed to GPIOs connected to the GPE blocks. Therefore, provide a common implementation for tis_plat_irq_status() to reduce code duplication. This code could be further extended to not be added based on MAINBOARD_HAS_TPM_CR50, but that's all that's using it for now. Change-Id: I955df0a536408b2ccd07146893337c53799e243f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19369 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-04-24soc/intel/skylake: Add ID's for Kabylake-RNaresh G Solanki
Add CPUID, IGD, MCH & LPC ID of Kabylake-R. Change-Id: I5ee7b3a2616f71137bba83c071288dbda2acde3d Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/19218 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-19soc/intel/quark: Move include of reg_access.hLee Leahy
Move include of reg_access.h from pci_devs.h to reg_access.c. TEST=Build and run on Galileo Gen2 Change-Id: I0d2de96f51c56001cdd06c7974cbc649fde1e89c Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19355 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-04-19soc/intel/skylake: Add ASL entries for IMGU and CIO2 devicesSowmya
Add ASL entries for IMGU and CIO2 devices * _CCA ACPI object to report that there is no Cache Coherent DMA support. * CAMD ACPI object to specify the device type. These ACPI objects are used by Intel kernel drivers. BUG=b:36580624 BRANCH=none TEST=Build and boot poppy. Dump and verify that DSDT table has the entries for IMGU and CIO2 devices. Change-Id: I13050253e18408cdb1e196f8003b3f43299aa5a5 Signed-off-by: Sowmya V <v.sowmya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18968 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-13soc/intel/apollolake: Change IOSF_BASE_ADDRESS to PCR_BASE_ADDRESSFurquan Shaikh
With recent change to use common block PCR (ccd8700c), IOSF_BASE_ADDRESS was renamed to PCR_BASE_ADDRESS. However, SD card change (99ce8a9b) was not rebased on top of it, so IOSF_BASE_ADDRESS slipped into the tree. Fix this by replacing all occurrences of IOSF_BASE_ADDRESS by PCR_BASE_ADDRESS. Change-Id: I40eb07be306035c940fc960896e0807d6c73bafa Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19277 Tested-by: build bot (Jenkins) Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-13soc/intel/apollolake: Set sdcard card detect (CD) host ownershipVenkateswarlu Vinjamuri
Currently sdcard CD host ownership is always owned by the GPIO driver. Due to this sdcard detection fails during initial boot process and OS fails to boot from sdcard. This implements change in host ownership from acpi to GPIO driver when kernel starts booting. BUG=b:35648535 TEST=Check OS boot from sdcard. Change-Id: I042a8762dc1f9cb73e6a24c1e7169c9746b2ee14 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/18947 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
2017-04-13soc/intel/skylake: Split AC/DC settings for Deep Sx configDuncan Laurie
Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled in both DC and AC states. However since using Deep S3 disables some expected features like wake-on-USB it is not always desired to enable the same state in both modes. To address this split the setting and add a separate config for Deep Sx in AC and DC states. All motherboards that set this config were updated, but there is no actual change in behavior in this commit. BUG=b:36723679 BRANCH=none TEST=This commit has no runtime visible changes, I verified on Eve that the Deep SX config registers are unchanged, and it compiles for all affected boards. Change-Id: I590f145847785b5a7687f235304e988888fcea8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19239 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-11intel/soc/apollolake: Use intel/common/uart driverAamir Bohra
Change-Id: I6829eca34d983cfcc86074ef593cd92236b25ac5 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19204 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-11soc/intel/skylake: Use intel/common/uart driverAamir Bohra
Change-Id: Id132df15ae5a6aef75d6434df18fc71d8d28c3ca Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19003 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-11soc/intel/common/block: Add Intel common UART codeAamir Bohra
Create Intel Common UART driver code. This code does below UART configuration for bootblock phase. * Program BAR * Configure reset register * Configure clock register Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/18952 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-11soc/intel/apollolake: Use LPSS common libraryAamir Bohra
Use lpss common library to program reset and clock register for lpss modules Change-Id: I75f9aebd60290fbf22684f8cc2ce8e8a4a4304b0 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19154 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-11soc/intel/skylake: Use LPSS common libraryAamir Bohra
Use lpss common library to program reset and clock register for lpss modules. Change-Id: I198feba7c6f6d033ab77ed25a5bd9ea99411a1e4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19153 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10soc/intel/common/block: Add LPSS function libraryAamir Bohra
LPSS function library implements common register programming under lpss. Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19001 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10soc/intel/apollolake: Use RTC common codeSubrata Banik
This patch uses common RTC library to enable upper 128 byte bank of RTC RAM. Change-Id: I55e196f6c5282d7c0a31b3980da8ae71764df611 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18700 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-10soc/intel/skylake: Use RTC common codeSubrata Banik
This patch uses common RTC library to enable upper 128 byte bank of RTC RAM. Change-Id: Ibcbaf5061e96a67815116a9f7a03be515997be6d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18701 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-10soc/intel/common/block: Add Intel common RTC code supportBarnali Sarkar
Create Intel Common RTC code. This code currently only contains the code for configuring RTC required in Bootblock phase which has the following programming - * Enable upper 128 bytes of CMOS. Change-Id: Id9dfcdbc300c25f43936d1efb5d6f9d81d3c8453 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18558 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins)
2017-04-10soc/intel/apollolake: Use common PCR moduleSubrata Banik
This patch use common PCR library to perform CRRd and CRWr operation using Port Ids, define inside soc/pcr_ids.h Change-Id: Iacbf58dbd55bf3915676d875fcb484362d357a44 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18673 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10soc/intel/skylake: Use common PCR moduleSubrata Banik
This patch use common PCR library to perform CRRd and CRWr operation using Port Ids, define inside soc/pcr_ids.h Change-Id: Id9336883514298e7f93fbc95aef8228202aa6fb9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18674 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10soc/intel/common/block: Add Intel common PCR supportSubrata Banik
IOSF_SB message space is used to access registers mapped on IOSF-SB. These registers include uncore CRs (configuration registers) and chipset specific registers. The Private Configuration Register (PCR) space is accessed on IOSF-SB using destination ID also known as Port ID. Access to IOSF-SB by the Host or System Agent is possible over PSF via the Primary to Sideband Bridge (P2SB). P2SB will forward properly formatted register access requests as CRRd and CRWr request via IOSF-SB. Change-Id: I78526a86b6d10f226570c08050327557e0bb2c78 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18669 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-09drivers/spi: Get rid of spi_get_configFurquan Shaikh
There is only one user for spi_get_config i.e. SPI ACPI. Also, the values provided by spi_get_config are constant for now. Thus, get rid of the spi_get_config call and fill in these constant values in SPI ACPI code itself. If there is a need in the future to change these, appropriate device-tree configs can be added. BUG=b:36873582 Change-Id: Ied38e2670784ee3317bb12e542666c224bd9e819 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19203 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-07soc/intel/skylake: Enable XHCI clock gate control in ACPINaresh G Solanki
Enable SS link trunk clock gating & D3hot when device enters D3 state. Similarly disable SS link trunk clock gating & D3hot when device enters D0 state TEST=Build & boot Poppy board. Check working for XHCI wake when DUT is in S3. Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/18879 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-06soc/intel/skylake: Add support for GSPI controllerFurquan Shaikh
Sky Lake PCH contains two GSPI controllers. Using the common GSPI controller driver implementation for Intel PCH, add support for GSPI controller buses on Sky Lake/Kaby Lake. BUG=b:35583330 Change-Id: I29b1d4d5a6ee4093f2596065ac375c06f17d33ac Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19099 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-06soc/intel/common: Add support for common GSPI controllerFurquan Shaikh
Add support for GSPI controller in Intel PCH. This controller is compliant with PXA2xx SPI controller with some additional registers to provide more fine-grained control of the SPI bus. Currently, DMA is not enabled as this driver might be used before memory is up (e.g. TPM on SPI). Also, provide common GSPI config structure that can be included by SoCs in chip config to allow mainboards to configure GSPI bus. Additionally, provide an option for SoCs to configure BAR for GSPI controllers before memory is up. BUG=b:35583330 Change-Id: I0eb91eba2c523be457fee8922c44fb500a9fa140 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19098 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-05soc/intel/lpss: Provide common LPSS clock configFurquan Shaikh
Since there are multiple controllers in the LPSS and all use the same frequency, provide a single Kconfig option for LPSS_CLOCK_MHZ. BUG=b:35583330 Change-Id: I3c0cb62d56916e6e5f671fb5f40210f4cb33316f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19115 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-05soc/intel/skylake: Add tsc_freq.c to verstageFurquan Shaikh
This is required to provide tsc freq required by timer library. BUG=b:35583330 TEST=Verified that delay(5) in verstage adds a delay of 5 seconds. Change-Id: I03edebe394522516b46125fae1a17e9a06fd5f45 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19094 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-05soc/intel/common: allow lpss i2c time-based data hold timeAaron Durbin
When using rise_time_ns and fall_time_ns there's currently not a way to specify a target data hold time. The internal 300ns value is used. However, that isn't always sufficient depending on bus topology. Therefore, provide the ability to specify data hold time in ns from devicetree, defaulting to default value if none are specified. BUG=b:36469182 Change-Id: I86de095186ee396099709cc8a97240bd2f9722c9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19064 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-03nb/intel: Deduplicate vbt headerPatrick Rudolph
Move header and delete duplicates. Change-Id: I0e1f5d9082626062f95afe718f6ec62a68f0d828 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18903 Tested-by: build bot (Jenkins) Tested-by: coreboot org <coreboot.org@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-29soc/intel/apollolake: Fix debug build booting issueSubrata Banik
This patch fix apollolake devices unable to boot with coreboot debug image issue. Change-Id: I28943100ba19dec1e540fdbba1c1e110c6af1488 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/19036 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-28Remove libverstage as separate library and source file classJulius Werner
In builds without CONFIG_VBOOT_SEPARATE_VERSTAGE, verstage files are linked directly into the bootblock or the romstage. However, they're still compiled with a separate "libverstage" source file class, linked into an intermediate library and then linked into the final destination stage. There is no obvious benefit to doing it this way and it's unclear why it was chosen in the first place... there are, however, obvious disadvantages: it can result in code that is used by both libverstage and the host stage to occur twice in the output binary. It also means that libverstage files have their separate compiler flags that are not necessarily aligned with the host stage, which can lead to weird effects like <rules.h> macros not being set the way you would expect. In fact, VBOOT_STARTS_IN_ROMSTAGE configurations are currently broken on x86 because their libverstage code that gets compiled into the romstage sets ENV_VERSTAGE, but CAR migration code expects all ENV_VERSTAGE code to run pre-migration. This patch resolves these problems by removing the separate library. There is no more difference between the 'verstage' and 'libverstage' classes, and the source files added to them are just treated the same way a bootblock or romstage source files in configurations where the verstage is linked into either of these respective stages (allowing for the normal object code deduplication and causing those files to be compiled with the same flags as the host stage's files). Tested this whole series by booting a Kevin, an Elm (both with and without SEPARATE_VERSTAGE) and a Falco in normal and recovery mode. Change-Id: I6bb84a9bf1cd54f2e02ca1f665740a9c88d88df4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18302 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28vboot: Move remaining features out of vendorcode/google/chromeosJulius Werner
This patch attempts to finish the separation between CONFIG_VBOOT and CONFIG_CHROMEOS by moving the remaining options and code (including image generation code for things like FWID and GBB flags, which are intrinsic to vboot itself) from src/vendorcode/google/chromeos to src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig options, and clean up menuconfig visibility for them (i.e. some options were visible even though they were tied to the hardware while others were invisible even though it might make sense to change them). CQ-DEPEND=CL:459088 Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18984 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28chromeos / broadwell / jecht: Make save_chromeos_gpios() jecht-specificJulius Werner
This callback was only required for a single mainboard, and it can easily be moved to mainboard-specific code. This patch removes it from the global namespace and isolates it to the Jecht board. (This makes it easier to separate vboot and chromeos code in a later patch.) Change-Id: I9cf67a75a052d1c86eda0393b6a9fbbe255fedf8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18981 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-28vboot: Assume EC_SOFTWARE_SYNC and VIRTUAL_DEV_SWITCH by defaultJulius Werner
The virtualized developer switch was invented five years ago and has been used on every vboot system ever since. We shouldn't need to specify it again and again for every new board. This patch flips the Kconfig logic around and replaces CONFIG_VIRTUAL_DEV_SWITCH with CONFIG_PHYSICAL_DEV_SWITCH, so that only a few ancient boards need to set it and it fits better with CONFIG_PHYSICAL_REC_SWITCH. (Also set the latter for Lumpy which seems to have been omitted incorrectly, and hide it from menuconfig since it's a hardware parameter that shouldn't be configurable.) Since almost all our developer switches are virtual, it doesn't make sense for every board to pass a non-existent or non-functional developer mode switch in the coreboot tables, so let's get rid of that. It's also dangerously confusing for many boards to define a get_developer_mode() function that reads an actual pin (often from a debug header) which will not be honored by coreboot because CONFIG_PHYSICAL_DEV_SWITCH isn't set. Therefore, this patch removes all those non-functional instances of that function. In the future, either the board has a physical dev switch and must define it, or it doesn't and must not. In a similar sense (and since I'm touching so many board configs anyway), it's annoying that we have to keep selecting EC_SOFTWARE_SYNC. Instead, it should just be assumed by default whenever a Chrome EC is present in the system. This way, it can also still be overridden by menuconfig. CQ-DEPEND=CL:459701 Change-Id: If9cbaa7df530580a97f00ef238e3d9a8a86a4a7f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18980 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28vboot: Remove VBOOT_DYNAMIC_WORK_BUFFER Kconfig optionJulius Werner
VBOOT_DYNAMIC_WORK_BUFFER and VBOOT_STARTS_IN_ROMSTAGE are equivalent in practice. We can't have a dynamic work buffer unless we start in/after romstage, and there'd be no reason to go with a static buffer if we do. Let's get rid of one extra option and merge the two. Change-Id: I3f953c8d2a8dcb3f65b07f548184d6dd0eb688fe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18979 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28vboot: Remove CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL Kconfig optionJulius Werner
CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL allows the SoC directory to provide its own main() symbol that can execute code before the generic verstage code runs. We have now established in other places (e.g. T210 ramstage) a sort of convention that SoCs which need to run code in any stage before main() should just override stage_entry() instead. This patch aligns the verstage with that model and gets rid of the extra Kconfig option. This also removes the need for aliasing between main() and verstage(). Like other stages the main verstage code is now just in main() and can be called from stage_entry(). Change-Id: If42c9c4fbab51fbd474e1530023a30b69495d1d6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18978 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-28vboot: Select SoC-specific configuration for all Chrome OS boardsJulius Werner
Some Chrome OS boards previously didn't have a hardcoded vboot configuration (e.g. STARTS_IN_BOOTBLOCK/_ROMSTAGE, SEPARATE_VERSTAGE, etc.) selected from their SoC and mainboard Kconfig files, and instead relied on the Chrome OS build system to pass in those options separately. Since there is usually only one "best" vboot configuration for a certain board and there is often board or SoC code specifically written with that configuration in mind (e.g. memlayout), these options should not be adjustable in menuconfig and instead always get selected by board and SoC Makefiles (as opposed to some external build system). (Removing MAINBOARD_HAS_CHROMEOS from Urara because vboot support for Pistachio/MIPS was never finished. Trying to enable even post-romstage vboot leads to weird compiler errors that I don't want to track down now. Let's stop pretending this board has working Chrome OS support because it never did.) Change-Id: Ibddf413568630f2e5d6e286b9eca6378d7170104 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19022 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28soc/intel/apollolake: Clean up code by using common System Agent moduleSubrata Banik
This patch currently contains the SA initialization required for bootblock phase - 1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code. 2. Perform PCIEXBAR programming based on soc configurable PCIEX_LENGTH_xxxMB 3. Use common systemagent header file. Change-Id: I01a24e2d4f1c8c9ca113c128bb6b3eac23dc79ad Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18567 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-28soc/intel/skylake: Clean up code by using common System Agent moduleSubrata Banik
This patch currently contains the SA initialization required for bootblock phase - 1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code. 2. Perform PCIEXBAR programming based on soc configurable PCIEX_LENGTH_xxxMB 3. Use common systemagent header file. Change-Id: I0fa0a60f680b9b00b7f26f1875c553612b123a8e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18566 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28soc/intel/common/block: Add Intel common systemagent supportSubrata Banik
Create common Intel systemagent code. This code currently contains the SA initialization required in Bootblock phase, which has the following programming- * Set PCIEXBAR * Clear TSEG register More code will get added up in the subsequent phases. Change-Id: I6f0c515278f7fd04d407463a1eeb25ba13639f5c Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18565 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28soc/pci_devs.h: Use consistent naming in soc/pci_devs.hSubrata Banik
This patch to make common PCI device name between APL and SKL. Change-Id: I5e4c7502e9678c0a367e9c7a96cf848d5b24f68e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18576 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28soc/intel/apollolake: Clean up code by using common CAR initSubrata Banik
This patch currently contains common CAR initialization required in bootblock phase along with common MSR header - 1. Use SOC_INTEL_COMMON_BLOCK_CAR to have common CAR initialization and CAR teardown. 2. Use common MSR header "intelblocks/msr.h" inside soc/cpu.h Change-Id: I67f909f50a24f009b3e35388665251be1dde40f7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18555 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28soc/intel/common/block: Add cache as ram init and teardown codeSubrata Banik
Create sample model for common car init and teardown programming. TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED and CAR_NEM configs till post code 0x2a. Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18381 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-26soc/intel/fsp_baytrail: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside soc/intel/fsp_baytrail. Change-Id: I2791346289c04049e6f032c8e120e4be9ba6657f Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17319 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-24soc/intel/apollolake: Remove unused CAR_GLOBAL variableSubrata Banik
Also move all local variable declaration at starting of function block. Change-Id: I774485a23b4b7d96a8dbd837da45553251dff3b0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18949 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-24soc/intel/skylake: Use C entry code for MTRR programmingSubrata Banik
Make skylake cache as ram SPI mapped MTRR programming align with apollolake code. Change-Id: I87a5c655da8ff5f6d8ef86907b7ae2263239b1ac Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18923 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-23soc/intel/skylake: Add SGX initializationRobbie Zhang
This patch implements SGX initialization steps in coreboot per Intel SGX BWG rev 2.0.8 for Kaby Lake SoC. If enabled on a Kabylake device, SoC capability and PRM (processor reserved memory) of desired size (needs to be configured through PrmrrSize) are provisioned for later software stack to use SGX (i.e., run SGX enclaves). One issue is still puzzling and needs to be addressed: by calling configure_sgx() in cpu_core_init() which is the per-thread function, SGX is always failing for thread 0 but is successful for other 3 threads. I had to call configure_sgx() again from soc_init_cpus() which is the BSP-only function to make it enable on the BSP. Another pending work is the implementation for the Owner Epoch update which shall be added later. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Tested on Eve, verified SGX activation is successful on all threads. Change-Id: I8b64284875eae061fa8e7a01204d48d320a285a9 Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: https://review.coreboot.org/18445 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-22soc/intel/skylake: Add option to disable host reads to PMC XRAMRizwan Qureshi
FSP disables host access to shadowed PMC XRAM registers by default, it also provides a UPD to enable/disable host reads to these regiters. Expose the same in devicetree as a config option. Change-Id: Iaa33aa3233bda4f050da37d1d8af0556311c9496 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18319 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-22soc/intel/skylake: Add configs for enabling DCI and TraceHubAamir Bohra
Add configs for enabling Intel TraceHub and DCI for aid in debugging. Change-Id: Ic40f9499c0125070049856e242e89024ca5a1c4e Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18791 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-22soc/intel/apollolake: Add CQOS config for CAR common codeSubrata Banik
Change-Id: I5947170a96e888cea2f3faac92355e72b63c1fef Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18735 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-21soc/intel/apollolake: Use common function to fill DIMM informationBarnali Sarkar
Extract SMBIOS memory information from FSP SMBIOS_MEM_INFO_HOB and use common function dimm_info_fill() to save it in CBMEM. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot Reef to verify the type 17 DIMM info coming in SMBIOS table from Kernel command "dmidecode". Change-Id: I33c3a0bebf33c53beadd745bc3d991e1e51050b7 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18451 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-03-17soc/intel/broadwell: Fix other issues detected by checkpatchLee Leahy
Fix the following error and warnings detected by checkpatch.pl: ERROR: switch and case should be at the same indent WARNING: line over 80 characters WARNING: storage class should be at the beginning of the declaration WARNING: adding a line without newline at end of file WARNING: __func__ should be used instead of gcc specific __FUNCTION__ WARNING: Comparisons should place the constant on the right side of the test TEST=None Change-Id: I85c400e4a087996fc81ab8b0e5422ba31df3c982 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18885 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17soc/intel/broadwell: Fix {}, () and conditional issuesLee Leahy
Fix the following errors and warnings detected by checkpatch: ERROR: open brace '{' following struct go on the same line ERROR: return is not a function, parentheses are not required ERROR: do not use assignment in if condition ERROR: trailing statements should be on next line WARNING: else is not generally useful after a break or return WARNING: braces {} are not necessary for single statement blocks WARNING: braces {} are not necessary for any arm of this statement TEST=None Change-Id: I9414341b0c778c252db33f0ef4847b9530681d96 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18884 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-17soc/intel/broadwell: Add int to unsignedLee Leahy
Fix the following issue detected by checkpatch: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=None Change-Id: Iae22e724b6adae16248db7dc8f822f65bfadae5f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18873 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-17soc/intel/broadwell: Fix spacing issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: code indent should use tabs where possible ERROR: space required after that ',' (ctx:VxV) ERROR: space prohibited before that ',' (ctx:WxW) ERROR: spaces required around that '=' (ctx:VxV) ERROR: spaces required around that '<=' (ctx:WxV) ERROR: spaces required around that '<=' (ctx:VxV) ERROR: spaces required around that '>' (ctx:VxV) ERROR: spaces required around that '>=' (ctx:VxV) ERROR: spaces required around that '+=' (ctx:VxV) ERROR: spaces required around that '<' (ctx:VxV) ERROR: "foo * bar" should be "foo *bar" ERROR: "foo* bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" ERROR: space required before the open parenthesis '(' WARNING: space prohibited between function name and open parenthesis '(' WARNING: please, no space before tabs WARNING: please, no spaces at the start of a line False positives are generated for the following test: WARNING: space prohibited between function name and open parenthesis '(' in both pei_data.h and pei_wrapper.h TEST=None Change-Id: Icab08e5fcb6d5089902ae5ec2aa5bbee5ac432ed Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18872 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-17soc/intel/apollolake: Reduce D3 cold delay for eMMC controllerZhuo-hao Lee
eMMC Controller is taking over 100ms to resume during runtime which results in I/O latency issues on the Apollo Lake system such as Snappy. The cause is the Linux Kernel setting the firmware reset time to 100 ms by default. This patch adds _DSM method for eMMC comtroller for specifying the device readiness durations. Function index 9 returns package of five integers to set D3 cold delay to zero and ACPI constant Ones for the elements where overriding the default values is not desired. BUG=b:35774937 BRANCH=none TEST=update snappy coreboot and test i/o latency is under 100ms Signed-off-by: Zhuo-hao Lee <zhuo-hao.lee@intel.com> Signed-off-by: Sowmya V <v.sowmya@intel.com> Change-Id: Idcfe4252b20bead15c2e5b9cb000ff797295f06a Reviewed-on: https://review.coreboot.org/18806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-17soc/intel/braswell: Fix most of the issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: that open brace { should be on the previous line ERROR: return is not a function, parentheses are not required WARNING: braces {} are not necessary for any arm of this statement WARNING: line over 80 characters WARNING: braces {} are not necessary for single statement blocks WARNING: Avoid unnecessary line continuations WARNING: break is not useful after a goto or return WARNING: else is not generally useful after a break or return False positives are generated by checkpatch for the following test: ERROR: Macros with complex values should be enclosed in parentheses TEST=Build for cyan Change-Id: I19048895145b138a63100b29f829ff446ff71b58 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18871 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-03-17soc/intel/braswell: Add int to unsignedLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=Build for cyan Change-Id: Ib5c6a1bf5308a8add42d7371854b80ea53d7ae84 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18870 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-03-17soc/intel/braswell: Fix spacing issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: space required after that ',' (ctx:VxV) ERROR: space prohibited before that ',' (ctx:WxE) ERROR: spaces required around that '=' (ctx:WxV) ERROR: code indent should use tabs where possible WARNING: space prohibited between function name and open parenthesis '(' WARNING: please, no spaces at the start of a line TEST=Build for cyan Change-Id: I84d4204585b498b695608c5008fdfb7961e2416f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18869 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-03-17soc/intel/skylake: Fix remaining issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: code indent should use tabs where possible ERROR: Macros with complex values should be enclosed in parentheses ERROR: "foo * bar" should be "foo *bar" ERROR: space required before the open parenthesis '(' ERROR: spaces required around that '=' (ctx:VxW) WARNING: space prohibited between function name and open parenthesis '(' WARNING: storage class should be at the beginning of the declaration WARNING: char * array declaration might be better as static const WARNING: please, no space before tabs WARNING: braces {} are not necessary for single statement blocks WARNING: else is not generally useful after a break or return WARNING: static const char * array should probably be static const char * const TEST=Build for glados Change-Id: Ic14ca3abd193cfe257504a55ab6b74782b26bf6d Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18868 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-17soc/intel/skylake: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch: WARNING: line over 80 characters TEST=Build for glados Change-Id: I79341f46ca06ac052f987975ccaf975470d27806 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18867 Tested-by: build bot (Jenkins) Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2017-03-17soc/intel/skylake: Add int to unsignedLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=Build for glados Change-Id: Idc2ad265e8ed8cd7fd6d228cfbe4cbbcb9d3ebfc Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18866 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-15intel/skylake: Support for setting AC/DC loadlineDuncan Laurie
Add options to set the AC and DC loadline values for each supported VR type so these can be tuned on a per-board basis in devicetree.cb. BUG=b:36228330 BRANCH=none TEST=Build and boot on Eve and check debug FSP output to ensure that it is applying the provided loadline values Change-Id: I2a5533d2c9fd86351c86584e3738e80ac4c1f915 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18819 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-15intel/skylake: Fix bug in VR configuration with FSP 2.0Duncan Laurie
With the move to FSP 2.0 the number of VR types supported was reduced to 4, and the VR_RING type is no longer present. This means all existing boards using FSP 2.0 are incorrectly passing VR configuration into FSP as the values corresponding to "GT Sliced" and "GT Unsliced" have changed. Fix this by updating the skylake SOC VR handling to account for changes in the FSP configuration and no longer provide VR_RING type when using FSP 2.0. BUG=b:36228330 BRANCH=none TEST=manual: build and boot on Eve Change-Id: I59eea9fba006a4c235d7b42d07fdc6e4f44f7351 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18818 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-03-15intel/skylake: nhlt: Add support for rt5514 NHLT blobDuncan Laurie
Add support for describing the NHLT blob for the rt5514 DSP. Currently this only supports 4 channel capture. BUG=b:35585307 BRANCH=none TEST=build and boot on Eve P1 Change-Id: Ib59b56222f9aa65370fdcf9ddf25145c571b1b2e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18816 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-15soc/intel/quark: Read the rmu.bin file from read-only regionLee Leahy
Always read the rmu.bin file from the read-only section of the SPI flash. Without this change vboot attempts to read this file from the A or B section of the flash. TEST=Build and run on Galileo Gen2 Change-Id: Ied8eaa2cd37645bf401aa957936943946bfd6182 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18803 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-15soc/intel/common: Wrap lines at 80 columnsLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: code indent should use tabs where possible TEST=Build and run on Galileo Gen2 Change-Id: Ief4b96073b3df30e45bf5d802ca3b190e7f431a7 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18753 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-15soc/intel/apollolake: Cache FPF status value in flashAndrey Petrov
Since asking CSE to read FPF status turned out to be slow in some cases, cache and save returned value on first boot only. Value is read from flash on consequent boots. BUG=b:35586975 BRANCH=reef TEST=boot twice, make sure cached FPF status is loaded from flash the second time. Change-Id: I6e56a35407c9097616ccb05a557fded7b639c88a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18774 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14soc/intel/quark: Pass S3 wake status to fsp_silicon_initLee Leahy
Fix build error with FSP 1.1. Pass the S3 wake status to fsp_silicon_init. TEST=Build and run on Galileo Gen2 Change-Id: I78150f737321db5b1b4d63b411fa6432ac30d080 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18805 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14soc/intel/quark: Add ESRAM display to FSP 1.1Lee Leahy
Add ESRAM display to FSP 1.1 TEST=Build and run on Galileo Gen2 Change-Id: Ia47b0bdba65606a7f0695332d298fc1e910b0e2f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18804 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14soc/intel/quark: Return NULL for top_of_memoryLee Leahy
Return NULL for top_of_memory when the register has not been set. TEST=Build and run on Galileo Gen2 Change-Id: If79cac68c2a64aa9bf3be72d3cfc4c73fceef12b Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18802 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14soc/intel/skylake: Extract DIMM Information from FSP MEM INFO HOBBarnali Sarkar
Extract SMBIOS memory information from FSP SMBIOS_MEM_INFO_HOB and save it in CBMEM. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in SMBIOS Table from Kernel command "dmidecode". Change-Id: I593d4ccb0d4866e99913a73c49b2f000b51827d1 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18275 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-13soc/intel/quark: Add the verstage filesLee Leahy
Add the files to support verstage for vboot. TEST=Build and run on Galileo Gen2 Change-Id: Icf87075012c08cf581c17d579e0763888c707265 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18040 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13soc/intel/apollolake: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build for reef Change-Id: I4fbe95037ca4b52e64ba37e5c739af4a03f64feb Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18728 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13soc/intel/apollolake: Fix issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: switch and case should be at the same indent ERROR: do not use assignment in if condition WARNING: Statements terminations use 1 semicolon WARNING: unnecessary whitespace before a quoted newline WARNING: else is not generally useful after a break or return TEST=Build for reef Change-Id: I5486936dbf19b066c76179d929660affa1da5f16 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18727 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13soc/intel/apollolake: Fix position of storage classLee Leahy
Fix the following error and warning detected by checkpatch.pl: ERROR: inline keyword should sit between storage class and type WARNING: storage class should be at the beginning of the declaration TEST=Build for reef Change-Id: I2ed418cc3b4a989eb1101013944169429bf147c2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18726 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13soc/intel/apollolake: Fix parenthesis issuesLee Leahy
Fix the following errors and warning detected by checkpatch.pl: ERROR: space required before the open parenthesis '(' ERROR: space prohibited before that close parenthesis ')' ERROR: return is not a function, parentheses are not required WARNING: space prohibited between function name and open parenthesis '(' TEST=Build for reef Change-Id: I31f854adf3269ba6f77c4044fb3748bb1957841c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18725 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13soc/intel/apollolake: Fix unsigned warningsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=Build for reef Change-Id: Ifc45ce90d466d087cd20af72ddfc8486d2f1492c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18724 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13soc/intel/apollolake: Remove unnecessary bracesLee Leahy
Fix the following warnings detected by checkpatch.pl: WARNING: braces {} are not necessary for any arm of this statement WARNING: braces {} are not necessary for single statement blocks TEST=Build for reef Change-Id: Ifab09c023faa7da215945f1aedd391f4b2a1a04c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18723 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13soc/intel/apollolake: Indent code using tabsLee Leahy
Fix the following error and warnings detected by checkpatch.pl: ERROR: code indent should use tabs where possible WARNING: please, no spaces at the start of a line WARNING: please, no space before tabs TEST=Build for reef Change-Id: Id7a758463b95274c5e8bbdd67da0955f1ae78aac Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18721 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13soc/intel/apollolake: Fix spacing around operators and commasLee Leahy
Fix the following errors detected by checkpatch.pl: ERROR: spaces required around that '==' (ctx:VxO) ERROR: space required before that '-' (ctx:OxV) ERROR: spaces required around that '=' (ctx:VxW) ERROR: spaces required around that '=' (ctx:WxV) ERROR: spaces required around that '=' (ctx:VxV) ERROR: need consistent spacing around '+' (ctx:VxW) ERROR: space prohibited before that '++' (ctx:WxB) ERROR: space prohibited before that ',' (ctx:WxW) ERROR: space required after that ',' (ctx:VxV) TEST=Build for reef Change-Id: I37265a69fcb14fbf7c182ef29d823f70a5748ad8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18720 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13soc/intel/apollolake: Fix space between type, * and variable nameLee Leahy
Fix the following errors detected by checkpatch.pl: ERROR: "foo * bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" TEST=Build for reef Change-Id: I4a762d8fa762057a06e601dfed10538adc5d8bc8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18719 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13soc/intel/apollolake: Move brace to beginning of lineLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: open brace '{' following function declarations go on the next line TEST=Build for reef Change-Id: Icb92dc49c6e7b8dfea60bc0395f3db7316c4e34c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18722 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13soc/intel/common: Remove parenthesisLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: return is not a function, parentheses are not required TEST=Build and run on Galileo Gen2 Change-Id: Idf7723d4fd48124a26bbb626afc310820f859f66 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18757 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-13soc/intel/common: Fix unsigned warningsLee Leahy
Fix the following warning detected by checkpatach.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=Build and run on Galileo Gen2 Change-Id: Ic266c077eb115e0c7d934c15bcc4cc9b9e530a39 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18756 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-13soc/intel/common: Fix spacing issuesLee Leahy
Fix the following errors detected by checkpatch.pl: ERROR: spaces required around that '=' (ctx:VxV) ERROR: spaces required around that ':' (ctx:VxW) ERROR: space required after that ',' (ctx:VxV) ERROR: space required before the open parenthesis '(' ERROR: switch and case should be at the same indent ERROR: "foo ** bar" should be "foo **bar" TEST=Build and run on Galileo Gen2 Change-Id: I52ba2a3c1e0fffad7145eecd878aba8dc450ac0b Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18755 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-13soc/intel/common: Indent code with tabsLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: code indent should use tabs where possible TEST=Build and run on Galileo Gen2 Change-Id: I61c4f01216cb6c788cf6da988c414bbb9648d502 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18754 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-10soc/intel/common: Pass the minimum possible string length for strncpyBarnali Sarkar
In strncpy() function of dimm_info_fill(), the minimum possible size of Module Part Number of DIMM is passed as argument. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in SMBIOS Table from Kernel command "dmidecode". Change-Id: Icc7667149eae9705b91e271628af1b443eb8556e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18617 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10soc/intel/broadwell: Rework IGD's CDClk selectionNico Huber
CDClk selection was wrong in some corner cases (e.g. ULX SKUs) and, for Broadwell, never took the devicetree config into account. Rewrite the selection with the following in mind: o cpu_is_ult() might return `true` for ULX SKUs, too, o ULX and Broadwell-ULT SKUs can be `overclocked` with additional cooling, so leave that as devicetree option. For Haswell, the following frequency selections are valid: o ULX: 337.5MHz by default, 450MHz optional o ULT: 450MHz only (maybe 337.5MHz too, documentation varies, it wasn't selectable before either) o others: 540MHz by default, 450MHz optional For Broadwell: o ULX: 450MHz by default, 337.5MHz / 540MHz optional o ULT: 540MHz by default, 337.5MHz / 450MHz / 675MHz optional o others: 667MHz by default, 337.5MHz / 450MHz / 540MHz optional Side effects: A too high setting in the devicetree results in the highest possible frequency now, Haswell non-ULT/ULX defaults to 540MHz instead of 450MHz. Change-Id: Iec12752f2a47bf4a5ae6077c75790eae9378c1b2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17768 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-10soc/intel/skylake:Add _DSM method to reduce D3 cold delay for eMMC controllersowmyav
eMMC Controller is taking over 100ms to resume during runtime which results in I/O latency issues on the Skylake systems like Cave and Caroline. This patch adds _DSM method for eMMC comtroller for specifying the device readiness durations. Function index 9 returns package of five integers to set D3 cold delay to zero and ACPI constant Ones for the elements where overriding the default values is not desired. BUG=b:35774937 BRANCH=none TEST=update caroline coreboot and test i/o latency is under 100ms Change-Id: Iacc8aa8560897da8770fe559ca8cd17aaf6ebeba Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/18532 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-10soc/intel/apollolake: Add PM methods to power gate SD cardVenkateswarlu Vinjamuri
This implements dynamic generation of sdcard GpioInt in SSDT. GpioInt in SSDT generation is based on the card detect GPIO if it is provided by the mainboard in devicetree. This implements GNVS variable to store the address of sdcard cd pin. GNVS used to store rxstate of the sdcard cd pin to get card presence. Add _PS0/_PS3 methods to power gate the sd card controller in S0ix and runtime PM. CQ-DEPEND=448173 BUG=chrome-os-partner:63070 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should enter S0ix and resume with no issue. Change-Id: Id2c42fc66062f0431385607cff1a83563eaeef87 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/18496 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
2017-03-09soc/intel/skylake: Add GPIO macros for IOxAPIC and SCILi Cheng Sooi
Add two GPIO macros: 1. PAD_CFG_GPI_APIC_EDGE allows a pin to be route to the APIC with input assuming the events are edge triggered. 2. PAD_CFG_GPI_ACPI_SCI_LEVEL to route the general purpose input to SCI assuming the events are level triggered. Change-Id: I944a9abac66b7780b2336148ae8c7fa3a8410f3f Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com> Reviewed-on: https://review.coreboot.org/18533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-09soc/intel/skylake: Add SKL SOC PCH H GPIO supportLi Cheng Sooi
Add SKL/KBL PCH-H GPIO settings referring from SKL PCH-H specifications to support sklrvp11. Split the gpio_defs.h into headers gpio_pch_h_defs.h and gpio_soc_defs.h for PCH-H specific and SOC specific GPIO defs respectively. Change-Id: I5eaf8d809a1244a56038cbfc29502910eb90f9f2 Signed-off-by: Li Cheng Sooi <li.cheng.sooi@intel.com> Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com> Reviewed-on: https://review.coreboot.org/18027 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-09soc/intel/apollolake: Add check if FPFs are blownAndrey Petrov
Apollolake platform comes with FPF (field-programmable-fuses). FPF can be blown only once, typically at the end of the manufacturing process. This patch adds code that sends a request to CSE to figure out if FPFs have already been blown. Change-Id: I9e768a8b95a3cb48adf66e1f17803c720908802d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18604 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-09soc/intel/apollolake: Start using common CSE driverAndrey Petrov
Change-Id: If866453f06220e0edcaa77af5f54b397ead3ac14 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18603 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-09soc/intel/common/block: Add HECI driverAndrey Petrov
Add common driver that can send/receive HECI messages. This driver is inspired by Linux kernel mei driver and somewhat based on Skylake's. Currently it has been only tested on Apollolake. BUG=b:35586975 BRANCH=reef TEST=tested on Apollolake to send single messages and receive both fragmented and non-fragmented versions. Change-Id: Ie3772700270f4f333292b80d59f79555851780f7 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18547 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-09soc/intel/apollolake: Prepare to use common HECI driverAndrey Petrov
Change-Id: Ib284493d886b223e8c85607de5fdb56b698fe5fa Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-08intel/skylake: Filter suspend well power failure event for Deep SxDuncan Laurie
If Deep Sx is enabled the event log will get entries added on every power sequence transition indicating that the suspend well has failed. When a board is using Deep Sx by design this is intended behavior and just fills the logs with extraneous events. To make this work the device init state has to be executed first so it actually enables the Deep Sx policies in the SOC since this code does not have any hooks back into the devicetree to read the intended setting from there. BUG=b:36042662 BRANCH=none TEST=Perform suspend/resume on Eve device with Deep S3 enabled, and then check the event log to be sure that it does not contain the "SUS Power Fail" event. Change-Id: I3c8242baa63685232025e1dfef5595ec0ec6d14a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18664 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-08intel/skylake: Add function to read state of Deep S5Duncan Laurie
Add a function to read the current state of Deep S5 configuration and indicate if it is enabled (for AC and/or DC) or disabled. This is similar to the existing function that checks Deep S3 enable state. BUG=b:36042662 BRANCH=none TEST=tested with subsequent commits to check Deep S5 state at boot and filter event log messages if it is enabled. Change-Id: I4b60fb99a99952cb3ca6be29f257bb5894ff5a52 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18663 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-08intel/skylake: Add devicetree settings for acoustic noise mitigationDuncan Laurie
Add options to the skylake chip config that will allow tuning the various settings that can affect acoustics with the CPU and its VRs. These settings are applied inside FSP, and they can adjust the slew slew rate when changing voltages or disable fast C-state ramping on the various CPU VR rails. BUG=b:35581264 BRANCH=none TEST=these are currently unused, but I verified that enabling the options can affect the acoustics of a system at runtime. Change-Id: I6a8ec0b8d3bd38b330cb4836bfa5bbbfc87dc3fb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18662 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 09:44:09 +0000