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2018-08-08cpu/amd: Correct number of MCA banks clearedMarshall Dawson
Use the value discovered in the MCG_CAP[Count] for the number of MCA status registers to clear. The generations should have the following number of banks: * Family 10h: 6 banks * Family 12h: 6 * Family 14h: 6 * Family 15h: 7 * Family 16h: 6 Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08cpu/amd: Rename MCA status registerMarshall Dawson
Change the defined name of MCI_STATUS (i.e. MCi_STATUS) to reflect its MC0_STATUS address. Change-Id: I97d2631a186965bb8b18f544ed9648b3a71f5fb0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-08soc/intel/apollolake: add new dimm info saving APIAaron Durbin
The current call for saving dimm info passed the lpddr4_cfg and memory sku id. In order to prepare decoupling the part number from lpddr4_cfg provide a new API, save_lpddr4_dimm_info_part_num(), which explicitly takes the part number. The previous API now uses the new one internally. BUG=b:112203105 Change-Id: Ieadf452b6daa3231a0c5e3be61b0603b40d0fff2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-08soc/intel/apollolake: Add support for LPDDR4 nWR settingRavi Sarawadi
nWR (Write-Recovery for AutoPre-charge commands), the programmed value of nWR is the number of clock cycles the LPDDR4-SDRAM device uses to determine the starting point of an internal Pre-charge operation after a Write burst with AP (auto-pre-charge) enabled. For >2133MHz speed parts the nWR needs to be set to 24 clock cycles. The nWR field, though, is only in the GLK FSP, so just update that field conditionally based on the GLK Kconfig option. BUG=b:112062440 TEST= build test Change-Id: I1147538f72f4e2f14e32f3657c05f1f505a56fbf Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-08soc/amd/stoneyridge/acpi.c: Remove fixed value variablesRichard Spiegel
In procedure generate_cpu_entries(), the code was copied from code that could change variables "plen" and "pcontrol_blk" based on number of cores. This is not the case with stoneyridge (2 cores only), and there's no need to use the variables. Remove them and replace with fixed values. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I0258b19960b050e8da9d218ded3f1f3bfccad163 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27877 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-08src/soc/intel/common: Configure the gspi chip select state correctlyAamir Bohra
This implementation updates the chip select control register programming in gspi controller setup call to program the correct bit fields for chip select state. Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920a53 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/27889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-07sdm845: Implement bitbang UART for bootblockJulius Werner
This patch replaces the UART in the bootblock of SDM845 with a bitbang implementation. Since SDM845 hardware UART needs a firmware blob loaded into it before it becomes usable, it is not really suited for use in the bootblock (since by the time we can read blobs from SPI, the bootblock is essentially over anyway). This solution allows us to still have some console output during early SoC initialization. Change-Id: I0c252ec83a7993edce5c4debc687f1fdd0d7b36d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-06soc/amd/stoneyridge: Call AMD ALIB method with AC/DC stateMarc Jones
AMD ALIB Function 1 accepts the AC/DC startup state. This is reported to be required for AMD PSPP settings. BUG=b:112020107 TEST= build test Change-Id: Ibb6c872d84745217912956c15d6ca2e8ba387561 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27785 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-06google/grunt: Move PSP_SELECTABLE_SMU_FW to socRichard Spiegel
Now that an updated bootloader with important fixes is available at coreboot repository, all stoneyridge boards should use it. Move the selection of SOC_AMD_PSP_SELECTABLE_SMU_FW from mb/google/kahlee to soc/amd/stoneyridge. BUG=b:111428800 TEST=Build and boot grunt. Change-Id: Idf8e348efbc85569aa1163125f412c5242c46eb4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27844 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-06src/soc/intel: Add AML IGD in platform reportingGaggery Tsai
This patch revises IGD naming and adds AML IGD in platform reporting. BUG=None BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage & Ensure AML IGD is shown in platform reporting. Change-Id: Id8f8379703abdaa5b14a4337a4fca04b370f3a2a Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06soc/intel/skl: Add AML IccMax and remove unused infoGaggery Tsai
This patch adds AML IccMax for VR configuration. From doc #594883, the IccMax for Core was changed to 28A, we need this patch to accommodate the changes. Besides, removes unused sku information from sku_icc_max_mapping structure. BUG=b:110890675 BRANCH=None TEST=Remove icc_max from DT & emerge-atlas coreboot chromeos-bootimage & Tested with AML-Y and KBL-Y SKUs. Change-Id: Ic22bae162b58b06b9519f1b708be55bde5e4641e Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27610 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-06soc/amd/stoneyridge: Enable spread spectrum in bootblockRaul E Rangel
setup_spread_spectrum is called in early_init, meaning the console is not initialized yet. So you won't see boot block booting twice. BUG=b:111610455 TEST=booted grunt and verified that AmdInitReset does not reboot. I had AGESA patched to skip the JTAG check. Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06soc/amd/stoneyridge: Disable SATA based on devicetree settingRichard Spiegel
Grunt boards don't use SATA, so it should be disabled to save power. Check if SATA is enabled in devicetree, and enable/disable the device based on that setting. BUG=b:112139043 TEST=Buil and boot grunt, checked the absence of SATA PCI. Change-Id: I4a3b5f65e612e8da5bedff0c557a0850f350dfa8 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-03soc/amd/common: Remove PSPP override settingMarc Jones
For some reason the PSPP setting was being overwritten in the common code. Remove the setting and allow the oem customize function to make the setting. BUG=b:112020107 TEST= build test Change-Id: If7f4511a71f725fedd60d33552656850e50d955d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-03soc/intel/cannonlake: Report Whiskey Lake infoLijian Zhao
According to #574725, report Whiskey Lake CPUID, MCH device ID and graphics device ID in bootblock stage. BUG=N/A TEST=Build and boot up whiskey lake rvp platform and check serial log to see proper CPU/MCH/GFX/PCH got recognized. Change-Id: I3fbc190e0520989d2fd4a9b3294e84d67e49b2cf Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2018-08-03soc/intel/coffeelake: Add initial coffeelake supportLijian Zhao
Add coffeelake config and include path to coffeelake fsp header files. BUG=N/A TEST=Using private mainboard file can boot up on coffeelake rvp platform. Change-Id: Ide180de32a9d1896bed85b9e093963721c3d6041 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27468 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02google/cyan: Switch Touchpad and Touchscreen interrupts to be level-triggeredMatt DeVillier
Adapted from chromium commit 126d352 [Strago: switch Touchpad and Touchscreen interrupts to be level-triggered] The Elan and other touch controllers found in this device work much more reliably if used with level-triggered interrupts rather than edge-triggered. TEST=Boot several cyan boards, verify that touchpad and touchscreen work. Original-Change-Id: I59d05d9dfa9c41e5472d756ef51f0817a503c889 Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/894689 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia4f8cf83351dae0d78995ce0b0ed902d1e4ac3e8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-01sdm845: Add GPIO APIDavid Dai
Introduces new and required GPIO APIs, using common pinmux definitions for GPIO configuration. TEST=build & run Change-Id: I8cef9dae2072da32cb0678efefeb8f0070cdde9c Signed-off-by: David Dai <daidavid1@codeaurora.org> Reviewed-on: https://review.coreboot.org/26233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-01soc/amd/stoneyridge/lpc.c: Fix LPC host control namingRichard Spiegel
2 bits of LPC host control were originally not public, and wrongly identified as IMC related. Now that the bits are available in public BKDG, fix the naming of the bits. BUG=b:111912080 TEST=build and boot grunt. Change-Id: I1921f46c6be54eda6329c98267cec27004caadd5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27744 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01soc/intel/common/block: Add WhiskeyLake (WHL) IDsKrzysztof Sywula
Specifically PCI device ID for graphics and PCI device ID for northbridge. Change-Id: Ide237d3274df0543409c8a23b9bb50c8e0a6b7a3 Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com> Reviewed-on: https://review.coreboot.org/27519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kin Wai Ng <kin.wai.ng@intel.com>
2018-07-31src/soc/amd/stoneyridge: Remove IMC supportRichard Spiegel
Per AMD, the Integrated Micro Controller is not a supported feature of the Stoney Ridge APU. Systems are expected to implement an external EC for desired features. Remove all stoney IMC files and functions from src/soc/amd/stoneyridge. There are 2 "IMC bits" left (and used) that are not truly IMC. New BKDG describe these bits, so a new patch will be released later to fix the names and comment. BUG=b:111780177 TEST=Build grunt and gardenia Change-Id: I6a24e4c3f03d04713a030b884c611d9c64c4cb3a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27651 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30soc/amd/stoneyridge/northbridge.c: Create a way to change eDP training valueRichard Spiegel
The careena board needs different video settings to pass eye diagram test, which does not affect negatively the grunt board. In preparation for new VBIOS, create code that allows changing eDP training parameter. BUG=b:111673328 TEST=Tested in child patch. Change-Id: Ic0452618bfc5e05b9ef8280bb8ba398ec7b4ce95 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-30soc/intel/common: Add support to configure top swap featureAamir Bohra
RTC BUC control register provides a software interface to configure the top swap feature. This patch adds implementation to enable/disable top swap feature and gets it accessible in romstage as well. The top swap control functions are exposed only if INTEL_HAS_TOP_SWAP is selected. To use the topswap feature a second bootblock has to be added to the cbfs. Below configs aid in doing that, INTEL_HAS_TOP_SWAP INTEL_ADD_TOP_SWAP_BOOTBLOCK INTEL_TOP_SWAP_BOOTBLOCK_SIZE Enabling and Disabling topswap, using the added API enables user to boot alternatively from either bootblock. Change-Id: Iea31b891f81e76d4d623fcb68183c3ad3dcadbad Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/25805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-30soc/cavium/cn81xx: Use ATF from blobs repoPatrick Rudolph
Use precompiled BL31 from blobs repo. There's no check for USE_BLOBS here as the included file is "free": The BL31 is Open-Source and licensed under BSD. Change-Id: I7e9eb429d11150d43aa070d1bd6a11ea71951ce3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-30soc/cavium/bootblock: Get rid of register X1Patrick Rudolph
The register X1 isn't used. Document it and remove it. Change-Id: I9324ea9de24ba4baaef9dde890c443dd0f921ad9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/23792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-30soc/intel/fsp_baytrail: Add VBOOT supportPhilipp Deppenwiese
* Add vbnv_cmos_failed function to SoC. * Add VBOOT starts in romstage select. Change-Id: I90a051e2b8d303c918bef976d0bb07aae0b1f5b3 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29soc/intel: Remove legacy static TPM asl codePhilipp Deppenwiese
Since the TPM software stack refactoring static TPM ACPI code isn't needed anymore. Change-Id: I36a99cbc420ecfa55aa5c89787151d482225adf2 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27715 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-27soc/amd/stoneyridge: Add IGFX device ACPI ASL entryMarc Jones
Add internal graphics device 00.01.00 to the ACPI tables so that the ACPI PCI option ROM save functions have a proper scope to save the ROM to. BUG=b:111697181 TEST=Check coreboot log doesn't have "PCI: 00:01.0: Missing ACPI scope" and check _ROM method is added in the SSDT1. Change-Id: I2c9ef8d9dff76805b1fcde2ccceef958a5b53b4f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-07-27mediatek/mt8183: Add SPI supportmengqi.zhang
This patch implements SOC-specific code of mt8183 and link the common code to support SPI bus. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Signed-off-by: mengqi.zhang <mengqi.zhang@mediatek.com> Change-Id: I544e850299c74861313c2425721479fe5b91639e Reviewed-on: https://review.coreboot.org/27498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-27mediatek: Refactor SPI code among similar SOCsTristan Shieh
Refactor SPI code which will be reused amon similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: If5a6c554dc8361e729cf5c464325b97b2bfb7098 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-27mediatek/mt8183: Remove unused MMU stuff from bootblockTristan Shieh
Since we move mtk_mmu_init() from bootblock to decompressor, we don't need to build mmu_opertations.c in bootblock and we don't need to include <soc/mmu_operations.h> in bootblock.c. BUG=b:80501386 TEST=manually flashed into kukui and boots into romstage. Change-Id: I58f97ac1705e4dfde5e2d497d9bec33a1d8d17c2 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-07-26soc/intel/common/block/gpio: Add API for gpio_configure_pads_with_overrideFurquan Shaikh
This function adds support for gpio_configure_pads_with_override which: 1. Takes as input two GPIO tables -- base config table and override config table 2. Configures each pad in base config by first checking if there is a config available for the pad in override config table. If yes, then uses the one from override config table. Else, uses the base config to configure the pad. This is done to allow sharing of GPIO tables across baseboard-variants for various boards i.e. Each board can have a base config table which is provided by the baseboard and an optional override config table that can be provided by a variant to configure certain GPIOs differently. It is helpful when the variant GPIO diff list is not very huge compared to the baseboard. BUG=b:111743717 TEST=Verified that the GPIO config for phaser is same with and without this change. Change-Id: I1c5dc72c8368957201ab53d2e8398ff861341a4c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27640 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26mediatek/mt8183: Enable bootblock self-decompressionHung-Te Lin
MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. A fully functional bootblock (that can boot into verstage or romstage) is about 38000 bytes. If self decompression (CONFIG_COMPRESS_BOOTBLOCK) is enabled, only 25088 (66%) bytes are needed. Inspired from crosreview.com/1070018. BUG=b:80501386 TEST=manually flashed into kukui and boots into romstage. Change-Id: I7a739866a4ea3bcafe2ff7b9e88d5ed00f3f3e40 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/27599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-25soc/intel/apollolake: Get rid of power button device in corebootFurquan Shaikh
As per the ACPI specification, there are two types of power button devices: 1. Fixed hardware power button 2. Generic hardware power button Fixed hardware power button is added by the OSPM if POWER_BUTTON flag is not set in FADT by the BIOS. This device has its programming model in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this power button device by default if the power button FADT flag is not set. On the other hand, generic hardware power button can be used by platforms if fixed register space cannot be used for the power button device. In order to support this, power button device object with HID PNP0C0C is expected to be added to ACPI tables. Additionally, POWER_BUTTON flag should be set to indicate the presence of control method for power button. Chrome EC mainboards implemented the generic hardware power button in a broken manner i.e. power button object with HID PNP0C0C is added to ACPI however none of the boards set POWER_BUTTON flag in FADT. This results in Linux kernel adding both fixed hardware power button as well as generic hardware power button to the list of devices present on the system. Though this is mostly harmless, it is logically incorrect and can confuse any userspace utilities scanning the ACPI devices. This change gets rid of the generic hardware power button from APL and relies completely on the fixed hardware power button. BUG=b:110913245 TEST=Verified that fixed hardware power button still works as expected on octopus. Change-Id: I86259465c6cfaf579dd7dc3560b4c9e676b80b55 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27273 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-25drivers/tpm: Add TPM ramstage driver for devices without vboot.Philipp Deppenwiese
Logic: If vboot is not used and the tpm is not initialized in the romstage makes use of the ramstage driver to initialize the TPM globally without having setup calls in lower SoC level implementations. * Add TPM driver in ramstage chip init which calls the tpm_setup function. * Purge all occurrences of TPM init code and headers. * Only compile TIS drivers into ramstage except for vboot usage. * Remove Google Urara/Rotor TPM support because of missing i2c driver in ramstage. Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24905 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-24cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSxArthur Heymans
This is how these MSR's are referenced in Intel® 64 and IA-32 Architectures Software Developer’s Manual. The purpose is to differentiate with MSR_SMRR_PHYSx. Change-Id: I54875f3a6d98a28004d5bd3197923862af8f7377 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-23soc/cavium: Enable DRAM testPatrick Rudolph
Enable fast or extended DRAM test based on devicetree setting. The fast DRAM test takes less than a second, while the extended runs about 1 minute. Tested on Cavium Soc. Change-Id: I6a375f3d4c5cea7c3c0cd4592287f3f85dc7d3cf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-23soc/cavium: Apply additional devicetree fixupsPatrick Rudolph
Depends on Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d Apply additional devicetree fixes: * Update SCLK from boot fuses * Updated REFCLKUAA from UART ref clock divider settings * Remove disabled PEM entries * Remove phandle to disabled PEM entries Fixes: * Linux console wrong baud rate once the PL011 driver is started. * thunderx-pem kernel module crash on disable PCIe ports. Tested on Cavium SoC. Change-Id: I7e8eefd913915a879dad28dfb7801a2018ed2985 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-20mediatek/mt8183: Add GPIO supportPo Xu
This patch implements gpio_set_pull() and links the common MediaTek GPIO code to support IO config for other drivers (ex. SPI) and the requested functions in src/include/gpio.h. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ia2b0d88e9b70c9ad148797d77dc9e79ce1bcb64a Signed-off-by: Po Xu <jg_poxu@mediatek.com> Reviewed-on: https://review.coreboot.org/27417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-20mediatek: Share GPIO code among similar SOCsTristan Shieh
Refactor GPIO code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-19soc/cavium: Add PCI supportPatrick Rudolph
* Add support for secure/unsecure split * Use MMCONF to access devices in domain0 * Program MSIX vectors to fix a crash in GNU/Linux Tested on Cavium CN81XX_EVB. All PCI devices are visible. Change-Id: I881f38a26a165e6bd965fcd73547473b5e32d4b0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25750 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19Kconfig: Add config to insert ucode address in second FITRizwan Qureshi
This config is used to provide the name of a region where a microcode is located. The address of this will be added as the first entry in the FIT of the topswap bootblock. This adds a capability to associate two microcodes for each of the two bootblocks, this allows for the CPU to boot with different microcodes with 2 separate bootblocks. Change-Id: I4ee41d90bae34862aa68c9b8bd69288de1335585 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/27151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-19Kconfig: Add config for creating a second bootblockRizwan Qureshi
Intel PCH/Southbridges have feature that it is possible to have the southbridge/PCH look for the bootblock at a 64K or 128K/256K/512K/1MB (in case of newer SoCs) offset instead of the usual top of flash. Add configs to create a second bootblock and configure its size. Change-Id: I4bbd19c35871891b762a0673f840858d972e129e Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22533 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-18mainboard/google/Kahlee: Select low-power mode for WiFiSimon Glass
Put the PCIe clock pins in power-saving mode for the WiFi module to save power. Note: This currently does not appear to have any effect on grunt. BUG=b:110041917 BRANCH=none TEST=boot without this patch: $ iotools mem_read32 0xfed80e00 0x0046f3ff With this patch: $ iotools mem_read32 0xfed80e00 0x0046f3f1 Change-Id: I389815bc36b8610a30b0cbb9d73262ad392e0181 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-18soc/intel/common/block: Add WhiskeyLake W0 CPUIDKrzysztof Sywula
TEST=Boot up with W0 stepping processor. Change-Id: Ia7bcfd5235e57c70aa3f15d0042da8b16cf7e186 Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com> Reviewed-on: https://review.coreboot.org/27500 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-18sifive/fu540: add empty sdram init and size functionsPhilipp Hug
Change-Id: I65f900a3277bc8a4a83ebc8883d4a325bd690bf8 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-07-17riscv: add support for modifying compiler optionsXiang Wang
Each HART of a SoC like fu540 supports a different ISA. In order for the coreboot's code can run on each core, need to modify the compile options. So add this code. Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-07-17soc/amd/stoneyridge: Update ACPI external processor nameKevin Chiu
update external processor name to match declaration in SSDT. in SSDT: Processor (\_PR.P000, 0x00, 0x00000410, 0x06) {} Processor (\_PR.P001, 0x01, 0x00000000, 0x00) {} in DSDT: External (_PR_.CP00, UnknownObj) External (_PR_.CP01, UnknownObj) After fix this, ACPI _PSL (Passive List) now can return correct list of processor objects for thermal passive cooling. BUG=b:111478152 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I78c838608c78eb7b5e3f8d5c67589e082c756201 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27495 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17bdk: Use Kconfig options instead of getenv()Patrick Rudolph
* Use Kconfig options instead of unusable getenv * Select CAVIUM_BDK_DDR_TUNE_HW_OFFSETS on CN81XX * Fix Coverity CID 1393976 (DEADCODE) Tested on Cavium's cn8100_sff_evb. Change-Id: Ia16c0161b0e9cf5d06418e46556c0fb45532a5b1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-16soc/amd/stoneyridge: Add GPIO functions to SMMMarc Jones
GPIO functions are required by the Grunt SMI handler. Change-Id: Id729139b02c10bdd922b3df298f8f9feb1aff745 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16soc/amd/stoneyridge: Fix gpio_set functionMarc Jones
The gpio_set function was not writing the correct GPIO register address. Change-Id: Ib306773ac72505977b606836bbaf3e2067324894 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-16soc/cavium: Fix overflow before widenPatrick Rudolph
Fix Coverity CID1393974 Change-Id: I39caea8a248d2f1debfca307f6fb7a2fe3e431b1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-12Coverity: Fix CID1393976Patrick Rudolph
Cast to u64 to prevent possible integer overflow. Change-Id: I5c7d25278db54523242314cba6c85ac2f7a6c1f3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-12soc/intel/skylake: add a space in printing ME FPF statusPratik Prajapati
This is cosmetic change Before: ME: Power Management Event : Clean global reset ME: Progress Phase State : Unknown phase: 0x08 state: 0x10 ME: Power Down Mitigation : NO ME: FPF status : fused After: ME: Power Management Event : Clean Moff->Mx wake ME: Progress Phase State : Unknown phase: 0x08 state: 0x10 ME: Power Down Mitigation : NO ME: FPF status : fused Change-Id: I15c02045d0f94fdb3f4a028585cad488d4ac9aa6 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/27246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-12soc/intel/braswell/acpi/dptf/thermal.asl: Make Thermal event optionalFrans Hendriks
Currently thermal event support can not be disabled at board level. Define and dependent code are placed in same file. Move define of HAVE_THERM_EVENT_HANDLER to mainboard file. Change-Id: Icb532e5bc7fd171ee2921f9a4b9b2150ba9f05c5 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/27415 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11skylake: Remove "IshEnable"li feng
Remove "IshEnable" from soc_intel_skylake_config since it's not used anymore. Enable/disable ISH by checking if ISH device is turned on or not. Refer to https://review.coreboot.org/#/c/coreboot/+/26485/. BUG=b:79244403 BRANCH=none TEST=Built. Change-Id: I4d2889af118659852431c87cb516fd19b577efc5 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-11mediatek/mt8183: add PLL and clock init supportWeiyi Lu
Add PLL and clock init code. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Checked with frequency meter in SOC. Change-Id: I1f561f66bcf12de6a95c2f64eecd9508bd9bb26c Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-on: https://review.coreboot.org/27031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-11mediatek: Share PLL code among similar SOCsTristan Shieh
Refactor PLL code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: I11f044fbef93d4f5f4388368c510958d2b0ae66c Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27305 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11mediatek/mt8183: Add MMU operation supportTristan Shieh
Enable MMU in bootblock for performance, link common code to provide mtk_mmu_after_dram() to update MMU table in romstage after dram ready, implement mtk_soc_disable_l2c_sram(), and call mtk_mmu_disable_l2c_sram() to turn off L2C sram in ramstage. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I4e35f8276ca23de7fd13da3515b9f48d944ead32 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-11mediatek: Share MMU operation code among similar SOCsTristan Shieh
Refactor MMU operation code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Id8173da0a02e57e863263fcd89c91a9c089e8a0f Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-10soc/cavium: Add secondary CPU supportPatrick Rudolph
Change-Id: I07428161615bcd3d03a3eea0df2dd813e08c8f66 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10soc/cavium/cn81xx: Set cntfrq_el0Patrick Rudolph
Set cntfrq_el0 to provide correct timer frequency. Change-Id: I4b6d0b0cf646a066fc5a51552a1891eccbd91e5e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25450 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-10soc/cavium: Clean uart codePatrick Rudolph
* Only init UART_FOR_CONSOLE * Allow UART init with zero baudrate. * Init UART0..3 on Cavium's cn8100_sff_evb to fix kernel panic. Tested on CN8100_SFF_EVB. Change-Id: I1043b30318ec6210e2dd6b7ac313a41171d37f55 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10soc/cavium: Enable MMUPatrick Rudolph
* Configure and enable MMU. * Cover the whole I/O space. * A minimum of 512KB TTB space is required. * Use secure mem attribute as firmware is running in ARM TZ region. Tested on Cavium SoC. Change-Id: I969446da62b4cc7adf9393fab69ff84ebf49220d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10cavium: Add CN81xx SoC and eval board supportDavid Hendricks
This adds Cavium CN81xx SoC and SFF EVB files. Code is based off of Cavium's Octeon-TX SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK BDK coreboot differences: bootblock: - Get rid of BDK header - Add Kconfig for link address - Move CAR setup code into assembly - Move unaligned memory access enable into assembly - Implement custom bootblock entry function - Add CLIB and CSIB blobs romstage: - Use minimal DRAM init only devicetree: - Convert FTD to static C file containing key value pairs Tested on CN81xx: - Boots to payload - Tested with GNU/Linux 4.16.3 - All hardware is usable (after applying additional commits) Implemented in future commits: - Vboot integration - MMU suuport - L2 Cache handling - ATF from external repo - Devicetree patching - Extended DRAM testing - UART init Not working: - Booting a payload - Booting upstream ATF TODO: - Configuration straps Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688 Signed-off-by: David Hendricks <dhendricks@fb.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/23037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-09src/soc: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: I21680354f33916b7b4d913f51a842b5d6c2ecef3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-09soc/intel/skylake: config ISH in SOC sideli feng
Config ISH in SOC side by checking if ISH device is turned on. "IshEnable" is not needed anymore since ISH device on/off will tell if ISH should be enabled or not. "IshEnable" will be removed from chip.h in separate CL. Atlas board specific ISH setting is needed, which is committed in separate CL. BUG=b:79244403 BRANCH=none TEST=Verified on Atlas board with ISH rework. ISH log showed on console. Change-Id: I3fc8648b3e6551497617ef1ebd2889245cdd31c3 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-03soc/amd/stoneyridge: correct GPIO emission error in ACPIKevin Chiu
It can not emit byte data without BytePrefix. design to: Or (Local5, GPIO_PIN_OUT, Local5) error due to GPIO_PIN_OUT is 0x40 but 0x40 encoding means nothing in AML spec. so it will include next emitted string in Or: Or (Local5, Local5, \_SB.GPW2) fix: Store (0x40, Local0) Or (Local5, Local0, Local5) BUG=b:110962003 BRANCH=master TEST=emerge-grunt coreboot extract SSDT then check ACPI syntax is correct Change-Id: I7a0704112b77105826de87b14a38ed2f665224d5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-02stoneyridge: Enable legacy IORaul E Rangel
Legacy IO enables access to RTC IO 0x70-0x73. This is needed for CMOS to function correctly. BUG=b:110817463 TEST=ran firmware_CorruptFwSigB on grunt Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-02stoneyridge: Enable IO CF9 in bootblockRaul E Rangel
If IO CF9 is not enabled, hard_reset() won't do anything in bootblock or verstage. BUG=b:110817463 TEST=built on grunt and made sure that hard_reset() reboots. Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27267 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02mediatek/mt8183: Add mtcmos init supportTristan Shieh
Using common mtcmos code to power on audio and display modules in SOC. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Passes the status check at the end of mtcmos_power_on() Change-Id: I41f16ba36432a8bbc47793cec2979753c9f84b43 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-02mediatek: Move mtcmos code to a common directoryTristan Shieh
Move mtcmos code which can be reused into a common directory under soc/mediatek. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: I92b138890424b4f4a68cdb00bf2326eef9cd87b7 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27029 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02mediatek: Share mtcmos code among similar SOCsTristan Shieh
Refactor mtcmos code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Ibfd0a90f6eba3ed2e74a3fd54279c7645aa41774 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-02soc/amd/common: Change create_struct return valueKyösti Mälkki
Old return value was not used, and function body has die() in case of errors in allocation. Change-Id: I89b0e9c927d395ac6d27201e0b3a8658e9585187 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-02soc/amd/common: Fix agesawrapper CreateStruct callsKyösti Mälkki
When AllocationMethod == ByHost, buffer has to be provided by caller. Improve code symmetry, the named parameter is now always pointer to the struct. Change-Id: I2085f7d5d63ef96f4bd9d5194af099634c402820 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-06-30soc/intel/skylake: Generate ACPI RMRR tableMatt DeVillier
An ACPI RMRR table is requried for IOMMU to work properly with an iGPU (without using passthrough mode), so create one along with the DRHD DMAR table if the iGPU is present and enabled. Test: build/boot google/chell and purism/librem13v2 with kernel parameter 'intel_iommu=on' but without 'iommu=pt;' observe integrated graphics functional without corruption. Change-Id: I202fb3eb8618f99d41f3d1c5bbb83b2ec982aca4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2018-06-30arch/x86/acpi: Add DMAR RMRR helper functionsMatt DeVillier
Add DMAR RMRR table entry and helper functions, using the existing DRHD functions as a model. As the DRHD device scope (DS) functions aren't DRHD-specific, genericize them to be used with RMRR tables as well. Correct DRHD bar size to match table entry in creator function, as noted in comments from patchset below. Adapted from/supersedes https://review.coreboot.org/25445 Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27269 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-29soc/intel/baytrail: Fix Kconfig for mrc.bin inclusionArthur Heymans
It used the sandybridge systemagent binary and mentioned that in the help text which is simply wrong and won't work. This copies the nb/intel/haswell/Kconfig to not include an mrc.bin by default. Change-Id: I2e151a66abc6dab710abdbb92c0c28884d88912e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27140 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28amd/common/pi: Remove AGESA support files from bootblockMarshall Dawson
The stoneyridge bootblock no longer makes AGESA calls. Remove the support files from the bootblock build. TEST=boot Grunt Change-Id: I14d2336d5fb766a1acf5e812337ae0ab3ca4a6c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-28amd/common/pi: Remove obsolete heapmanager workaroundMarshall Dawson
Remove residual code that allowed successful building of the heapmanager code. Now that stoneyridge no longer makes AGESA calls in bootblock, it is safe to elimate the workaround. BUG=b:74518368 TEST=boot Grunt Change-Id: Ie169a691a177bcd8283c31c8188ce28bcbce82af Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-28fsp_broadwell_de: Add ability to set PCIe completion timeoutDavid Hendricks
This enables the user to set the completion timeout value in PCI Express Device Control 2 register via devicetree.cb. Based on corebootBDE-270-iou-complto.patch in Arista EOS 4.20 release. Change-Id: If0527899bc2047d0e57c11f7801768d07f9a5179 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/26225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-06-28soc/intel/skylake: clear MCA before booting to OSPratik Prajapati
mca_configure needs to be called for each core before booting to OS, else OS would keep dumping MCEs Change-Id: I95ca46fda7be65d74714bdb344e339922cbb6305 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/26392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-06-28intel/common: change mca_configure API's defPratik Prajapati
add an unused param so that mca_configure can be called by mp_run_on_all_cpus to run it on all cores. Change-Id: I2395ee7fbedc829f040959b0021967f800693eeb Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/26391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-06-28mediatek/mt8183: Remove the stub flash driver that planned to use eMMCTristan Shieh
The stub flash driver is a temporary hack that planned to adapt eMMC to SPI flash. Remove the hack since SPI flash is what we really expect. BUG=b:80501386 BRANCH=none TEST=Boots fine on Kukui Change-Id: If29869461fc8c2efe26bb8c901737ee85935d27f Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-06-28soc/intel/common/block: Move p2sb common functions into block/p2sbSubrata Banik
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving common soc code into common/block/p2sb. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL/CNL/APL platform. Change-Id: Ie9fd933d155b3fcd0d616b41cdf042cefe2c649a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-28soc/intel/apollolake: Remove dead filesFurquan Shaikh
Change a86d1b8 (soc/intel/common: Add SMM common code for Intel Platforms) moved APL to use common SMM code. However, smi.c and smm.h files under soc/intel/apollolake/ were not removed. This change removes the dead files since they are not used anymore. BUG=b:110836465 Change-Id: I1ff213372521fd47e2335de6a4b438d16c74ecd3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-28soc/intel/common: Disable GPEs just before enabling SMIsFurquan Shaikh
Call to pmc_disable_all_gpe is required before enabling SMIs to ensure that we do not end up in a recursive SMI handler loop as mentioned in change 74145f7 (intel/common/pmc: Disable all GPEs during pmc_init). Thus, this call was added at the end of pmc_fill_power_state as we want to ensure that all the GPE registers are backed up before being cleared for identifying the wake source in ramstage. This resulted in a side-effect on APL where pmc_fixup_power_state was called much later in the boot process. Even though we have got rid of pmc_fixup_power_state, this change moves the call to pmc_disable_all_gpe to happen just before enabling SMIs. This helps to keep the disabling of GPEs logically before the enabling of SMIs and any clean ups that happen in pmc or soc-specific code should not affect the state of GPEs. BUG=b:110836465 TEST=Verified that wake sources are correctly identified on KBL and APL. Also, no SMI handler issues observed when resuming. Change-Id: I122a8118edcec117f25beee71a23c0a44ae862ed Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-28soc/intel/common/block/pmc: Get rid of pmc_fixup_power_stateFurquan Shaikh
Now that APL does not need pmc_fixup_power_state, this function can be removed from the PMC common code as well. BUG=b:110836465 Change-Id: I94de41f3e52228bca4b7a5579afe5a23719429be Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-28soc/intel/apollolake: Remove call to pmc_fixup_power_stateFurquan Shaikh
On APL, call to pmc_fixup_power_state was added because GPE0_EN registers did not have the right bits set on resume from S3 -- this was a result of GPE_CFG registers getting reset to their default state on resume. GPE_CFG registers are programmed as part of pmc_gpe_init which was previously done only in ramstage. However, with change a673d1c (soc/intel/apollolake: Initialize GPEs in bootblock), call to pmc_gpe_init was added to bootblock which means that GPE_CFG registers will have the right state by the time control reaches romstage where pmc_fill_power_state is called. Thus, call to pmc_fixup_power_state is totally redundant and in fact leads to side-effects because of the call to pmc_disable_all_gpe at the end of pmc_fill_power_state. BUG=b:110836465 TEST=Verified on yorp that wake source is correctly identified on resume from S3. Change-Id: Ia63ddbe381ce8a59736c231d745fd71d008d5d92 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-27x86/car: Replace reference of copy_and_run locationKyösti Mälkki
For cases with POSTCAR_STAGE=y this reference pulled in the implementation of run_ramstage() which we would not call. Using _program results with the same region being marked as WRPROT-cacheble. Change-Id: Ie1eaf6f5bb8baa13e946112c4fc3d854dbf750a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Keith Hui <buurin@gmail.com>
2018-06-26soc/intel/apollolake: Enable logging for wake sources in S0ixFurquan Shaikh
This change adds GSMI callback elog_gsmi_cb_platform_log_wake_source to enable wake source logging from S0ix on APL/GLK. Additionally, elog.c is added to smm stage. BUG=b:79449585 TEST=Verified that S0ix entry/exit events are added to eventlog: =========== Power button ============ 59 | 2018-06-25 14:01:11 | S0ix Enter 60 | 2018-06-25 14:01:30 | S0ix Exit 61 | 2018-06-25 14:02:00 | Wake Source | Power Button | 0 =========== Lid open ================ 62 | 2018-06-25 14:02:36 | S0ix Enter 63 | 2018-06-25 14:02:56 | S0ix Exit 64 | 2018-06-25 14:03:26 | Wake Source | GPE # | 15 65 | 2018-06-25 14:03:32 | Wake Source | GPE # | 65 66 | 2018-06-25 14:03:37 | EC Event | Lid Open =========== Trackpad ================ 67 | 2018-06-25 14:04:20 | S0ix Enter 68 | 2018-06-25 14:04:33 | S0ix Exit 69 | 2018-06-25 14:05:03 | Wake Source | GPE # | 15 70 | 2018-06-25 14:05:08 | Wake Source | GPE # | 66 Change-Id: I005de58c73d00dc9d7e64f1459f6d786792b94db Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27234 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-26soc/amd/stoneyridge/southbridge.c: Fix get_index_bit limit checkRichard Spiegel
Limit is the maximum number of bits to be tested, however it's being checked against the number of bytes of uint32_t. when it should be number of bits. Create a macro to provide the number of bits, and use it instead of sizeof. BUG=b:75996437 TEST=Add debug messages to see code passing beyond the check, build and boot grunt, check that it passed the limit check, remove debug code. Change-Id: Id1dfda26d789183b346b20c37fec923d996b80db Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-25mb/google/kahlee/variants/grunt: Select low-power mode for BayHub720Simon Glass
Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to save power. This requires use of an additional register (Misc control register 2) and another bit in the existing 'protect' register. The naming of bit 0 of that register is incorrect, based on the latest datasheet (14 June 2018) so fix that too. BUG=b:73726008 BRANCH=none TEST=boot without this patch: iotools mem_read32 0xfed80e00 0x0046ffff With this patch: $ iotools mem_read32 0xfed80e00 0x00463fff Also see that the PCIe clock stops when eMMC is idle and can be started by starting disk activity. Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/26515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-25intel/skylake: nhlt: Add capture config for echo ref stream for Max98373 CodecSathyanarayana Nujella
During Speaker playback, quad Channel I/V feedback data is captured from SSP0 Rx. Out of these 4-channels, Stereo V-Sense data needs to be given as echo ref stream. So, adding stereo capture config to max98373_capture_formats. BUG=b:110074225 TEST='Audio playback and Capture Stereo echo ref data' Change-Id: I6fe619ece94d5011caffe37ef10b48f956938db9 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/27182 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-23soc/intel/cannonlake: Disable UART_DEBUG by defaultSubrata Banik
This patch ensures serial debug is not enabled by default on Cannonlake platform. Change-Id: Id925c8c73971a027e45ea3c61e878f134bc9feff Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/27205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-22sdm845: increase SRAM for bootblockT Michael Turney
Bootblock has grown beyond 32K, grow to 40K Change-Id: Iedc52151e223ebf4ff5b35a419b5378a6f1c661b Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/26760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-22soc/intel/cannonlake: Remove DMA support for PTTSubrata Banik
Alternative buffer communication support for PTT is no longer needed for CNL onwards and coreboot does not need to reserve additional 4KiB memory for PTT support. Change-Id: I11993cef77fd5e879eedabc1ed344f91f8257c90 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/27176 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-22soc/intel/common/block/cpu: Add option to skip coreboot AP initSubrata Banik
SoC users from IOTG team is looking forward for a solution to skip coreboot AP initialization flow and make use of FSPS-UPD to perform AP reset. TEST=Assign use_fsp_mp_init=1 to ensure coreboot is not bringing APs out of reset. Change-Id: Ibc8cd411e802fb682436a933073922b2693ba994 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21soc/intel/apollolake: unify definition for spi base addressBora Guvendik
Use SPI_BASE_ADDRESS instead of PRERAM_SPI_BASE_ADDRESS like big core in order make common code implementation straightforward. Change-Id: Ibcb013fc95de29234253e89c9ca100cc468d44f6 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/27097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21soc/intel/common: Make infrastructure ready for Intel common stage filesSubrata Banik
Select all Kconfig belongs into Intel SoC Family basecode/stage files and include required headers from include/intelbasecode/ files. BUG=None BRANCH=none TEST=Code is compiling with cannonlake configurations and also booting on cannonlake RVP. Change-Id: Iac99b4346e8bf6e260b00be9fefede5ad7b3e778 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 14:27:11 +0000