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2020-09-14soc/intel/cnl: Add ACPI support for PMC core OS driverMichael Niewöhner
PMC core OS driver (intel_pmc_core.c in linux kernel) provides debug hooks to developers and end users to quickly figure out why their platform is not entering a deeper idle state such as S0ix. Include the common pmc.asl added in commit 957481c. Test: PMC gets detected by Linux kernel module. Change-Id: Ibf7c8ba7449df15c2ca30d23791e17fc878204f2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45318 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14soc/amd/picasso: Move sd_emmc_config into emmc_config structRaul E Rangel
I plan on adding another eMMC parameter. This refactor keeps the config contained in a single struct. BUG=b:159823235 TEST=Build test Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4b57d651ab44d6c1cad661d620bffd4207dfebd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-14soc/amd/picasso: copy local info to transfer bufKangheui Won
We added transfer_info_struct to contain various information about memory region we pass from PSP to x86 in commit 0c12abe462. This should be at the start of transfer region but we only manipulated it as local variable and didn't put data into the region, resulting garbage data for transfer_info when x86 tries to read it. Copy the content of local variable to beginning of _transfer_buffer before requesting transfer to PSP so coreboot on x86 can access it. BUG=b:159220781 BRANCH=zork TEST=check transfer_info_struct is correctly populated on romstage Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I14bc34e6af501240a6f633db3999a7759e88d60b Reviewed-on: https://review.coreboot.org/c/coreboot/+/44751 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14soc/intel/xeon_sp/cpx: display FSP_PREV_BOOT_ERR_SRC_HOBJonathan Zhang
Before MRC code execution, FSP interrogates EMCA MSR registers and other registers to see if there are fatal errors happened during previous boot session. If there are, error records are saved into FSP_PREV_BOOT_ERR_SRC_HOB. When the value of Length field of FSP_PREV_BOOT_ERR_SRC_HOB is 2, that means the HOB does not contain any valid error record. TESTED=Injects MCE error through cscript, reboot into OS, check boot log: 0x75904d70, 0x00000400 bytes: HOB_TYPE_GUID_EXTENSION 5138b5c5-9369-48ec-5b9738a2f7096675: FSP_PREV_BOOT_ERR_SRC_HOB_GUID ================ PREV_BOOT_ERR_SRC HOB DATA ================ hob: 0x75904d88, Length: 0x42 MCBANK ERR INFO: Segment: 0, Socket: 0, ApicId: 0x0 McBankNum: 0x3 McBankStatus: 0xfe00000000800400 McBankAddr: 0xf0ff McBankMisc: 0xfffffff0 MCBANK ERR INFO: Segment: 0, Socket: 0, ApicId: 0x0 McBankNum: 0x4 McBankStatus: 0xfe00000000800400 McBankAddr: 0xfff0 McBankMisc: 0xfffffff0 0x75904d88: 42 00 01 00 00 00 00 00 03 00 00 04 80 00 00 00 B............... 0x75904d98: 00 fe ff f0 00 00 00 00 00 00 f0 ff ff ff 00 00 ................ 0x75904da8: 00 00 01 00 00 00 00 00 04 00 00 04 80 00 00 00 ................ 0x75904db8: 00 fe f0 ff 00 00 00 00 00 00 f0 ff ff ff 00 00 ................ 0x75904dc8: 00 00 Change-Id: Idbace4c2500440b3c1cf2628dd921ca1a989ae81 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44974 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14soc/intel/tigerlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KBAnil Kumar
This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix cbmem buffer overflow issue. Bug=None Branch=None Test=Boot TGLRVP and check cbmem -c | grep 'CBFS: Locating' lists all stages Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I2393cc83008211be8e6a2ca7a1e41a7e9d92caf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45183 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14soc/intel/tigerlake: Select USE_CAR_NEM_ENHANCED_V2 for tigerlakeShreesh Chhabbi
Selects Cache QoS mask MSR programming flow for Tigerlake SoC. BUG=b:145958015 TEST= Build and boot to Chrome OS on TGL-UP3 RVP. Recipe used: 1. Patch https://review.coreboot.org/c/coreboot/+/43494 that implements calculation of CQOS mask dynamically based on stack size usage & incorporates Tigerlake SoC specific programming flow. 2. QS Engineering Microcode based on 0x56 Official Microcode with LLC CQOS change. 3. QS SoC Part Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Change-Id: I602d93eb4f8243ec49993b00691140d9a6cf5733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-14soc/intel/common/cpu: Update COS mask calculation for NEM enhanced modeAamir Bohra
Update the COS mask calculation to accomodate the RW data as per SoC configuration. Currently only one way is allocated for RW data and configured for non-eviction. For earlier platform this served fine, and could accomodate a RW data up to 256Kb. Starting TGL and JSL, the DCACHE_RAM_SIZE is configured for 512Kb, which cannot be mapped to a single way. Hence update the number of ways to be configured for non- eviction as per total LLC size. The total LLC size/ number of ways gives the way size. DCACHE_RAM_SIZE/ way size gives the number of ways that need to be configured for non- eviction, instead of harcoding it to 1. TGL uses MSR IA32_CR_SF_QOS_MASK_1(0x1891) and IA32_CR_SF_QOS_MASK_2(0x1892) as COS mask selection register and hence needs to be progarmmed accordingly. Also JSL and TGL platforms the COS mask selection is mapped to bit 32:33 of MSR IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before MSR write instead of eax(maps 31:0). This implementation corrects that as well. BUG=b:149273819 TEST= Boot waddledoo(JSL), hatch(CML), Volteer(TGL)with NEM enhanced CAR configuration. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-13soc/amd/picasso/chip: fix typo in acp_pme_enableFelix Held
That devicetree setting is about the Audio Co-Processor and not ACPI. BRANCH=zork Change-Id: I7f376371ee094392d4434340c77f0fc8d0d8e4e1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-13soc/amd/picasso/aoac: make AOAC device number unsignedFelix Held
The AOAC device number is never negative, so make it unsigned. BRANCH=zork Change-Id: I3e0d15a646f02da5767504471961d5d9f8f28bea Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45308 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-13soc/amd/picasso/uart: make AOAC device ID in uart_enable unsignedFelix Held
This change is separate from CB:45308 to only have the directly UART- related changes in this patch train. BRANCH=zork Change-Id: Ie587fdbd1e6229c1374fce3568c6a361577dc6c4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-13soc/amd/picasso/uart: add missing types.h includeFelix Held
BRANCH=zork Change-Id: I51923d72a2ad8dceeef11e15fb6765262dd514d9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-12soc/intel/common/block/*/Kconfig: Guard options with if-blocksAngel Pons
The usual structure of these files is a global enable symbol, usually followed by an if-block which contains all other dependent symbols. Use this instead of having a `depends on` line to each symbol. Guard all symbols, even if they originally were not guarded, since they don't do anything useful unless the global enable option is selected. Change-Id: If5347187b07a46192f0063011ab197b5047f555f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45043 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-12soc/intel/denverton_ns/uart_debug: include header for uart_platform_baseFelix Held
Include console/uart.h for the declaration of uart_platform_base instead of declaring the function in the source file. Change-Id: Ib72d8884f27e93cec058dbcda404dd6908de1981 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-12include/console/uart: make index parameter unsignedFelix Held
The UART index is never negative, so make it unsigned and drop the checks for the index to be non-negative. Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-12soc/amd/picasso/uart: make index parameters unsignedFelix Held
The UART index is never negative, so make it unsigned and drop the check for the index to be non-negative. BRANCH=zork Change-Id: I38b5dad87f8af4fbe8ee1d919230efe48f68686c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-11soc/amd/picasso: Fix TSC frequency calculationNikolai Vyssotski
Fix TSC frequency calculation per Picasso PPR. This code was copied from Stoney and was incorrect for Picasso. BUG=b:163423984 TEST=verify Dalboz TSC to be 1GHz BRANCH=zork Change-Id: Ibe3f49c7d295e7336ee042da2b94823171b6eb55 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-11soc/amd/common/espi_util: clarify espi_open_io_windowFelix Held
Calling espi_open_generic_io_window in espi_open_io_window depends on the condition in the preceding if statement, so move the command into an else block to make it more obvious that this is the case. TEST=Timeless build results in identical image. Change-Id: I3039817afd79c30a2df2f2f54e7848f52dc2c487 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-11soc/intel/tigerlake: Clean up systemagent.hSubrata Banik
List of changes: 1. Convert inconsistent white space into tab. 2. Group together all MCHBAR offset macros. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I82fc362589389081b1b1856524a972b780af9a13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45256 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10soc/amd/picasso: Move APCB generation out of picassoRob Barnes
Move APCB generation out of the picasso makefile and into the mainboard makefile. APCB generation tends to be mainboard specific and does not belong in the soc makefile. BUG=b:168099242 TEST=Build mandolin and check for APCB in coreboot binary Build and boot ezkinil Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10soc/amd/picasso: Add MADT entry for GNB IOAPICJason Glenesk
Add the missing entry using new Kconfig symbol for IOAPIC ID. coreboot will always enable the GNB IOAPIC. Cq-Depend: chrome-internal:3247431, chrome-internal:3253044 BUG=b:167421913, b:166519072 TEST=Boot fully to morphius board with and without amd_iommu kernel parameter. Dump MADT and IVRS tables. Cross check ioapic entries in MADT against IVRS. BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: Ic4a2e9b71dba948e8a4907e5f97131426d8a4a3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45056 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10soc/amd/picasso: Assign IOAPIC IDs, GNB APIC base with FSPMarshall Dawson
Add Kconfig symbols for the FCH and GNB IOAPIC IDs, then pass the info to FSP to keep it in sync with coreboot. Do the same for the northbridge's IOAPIC base address. Use the new values where needed, and reserve the resources consumed by the GNB IOAPIC. BUG=b:167421913, b:166519072 TEST=Boot Morphius and verify settings BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45115 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10soc/mediatek: Drop unneeded empty linesElyes HAOUAS
Change-Id: Ia419de14614a7a1b583e0870e9ca2fcdc8cf815a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-09-10soc/intel/alderlake: Rename pch_init() codeSubrata Banik
Rename the pch_init function to bootblock_pch_init to maintain the parity with previous generation SoC code block. Refer to commit 1201696. Change-Id: Id2a89b2f64b58079062d79e07efbdcfad7ed3d2d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45189 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10soc/intel/tigerlake: Maintain consistent tab in iomap.hSubrata Banik
This patch converts inconsistent white space into tab. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: If5e191b92e3e53b43335136ef51bc62589b955a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-09-10sc7180: Add display hardware pipe line initializationVinod Polimera
Add sc7180 display hardware pipeline programming support and invoke the display initialization from soc_init. Changes in V1: - added display init required check. - added edid read function using i2c communication. - added sn65dsi86 bridge driver to init bridge. - moved display initialization to mainboard file. Changes in V2: - moved diplay init sequence to mainboard file - moved edid read function to bridge driver. - calculated timing paramters using edid parameters. - removed command mode config code. - moved bridge driver to drivers/ti. - seperated out bridge and soc code with mainboard file as interface. Changes in V3: - add GPIO selection at runtime based on boardid. - add vbif register struct overlay. Changes in V4: - update gpio config for lazor board. Change-Id: I7d5e3f1781c48759553243abeb3d694f76cd008e Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-10sc7180: Add display dsi interface programmingVinod Polimera
This change adds support for sc7180 dsi interface host programming. Changes in V1: - remove dual dsi config code. - update register access using struct overlays. - remove dsc config & command mode code. Changes in V2: - remove dsi read and write functions. - remove target and panel related code. Changes in V3: - move prototypes to headers. - define macros for constants. Changes in V4: - define register bits instead of hardcoded values. Change-Id: Ie64354ce8bc2a64b891fb9478fbca38d6ec4c321 Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-10sc7180: enable bl31T Michael Turney
Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/28014/44 Change-Id: Ia961ee0e30478e21fd786ce464655977449df510 Signed-off-by: Ashwin Kumar <ashk@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09soc/intel/common/block/imc: Drop unused codeAngel Pons
Nothing uses this code anymore. Change-Id: I5da1020597c126a40b015beb6e43fb0168aa330f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-09-09sc7180: Add display 10nm phy & pll programming supportVinod Polimera
Adds basic headers as well as source required for display dsi 10nm phy & pll programming. Changes in V1: - add struct overlays to model hardware registers. - remove typedef structures. - remove dead code such as dual dsi,split config etc. Changes in V2: - remove panel related header files. - update the bitclock calculation using edid parameters. - add phy timing calculation function. - update copyright license. Changes in V3: - update the mdss clock structure. - remove dsi_phy_configinfo_type struct. - remove unused struct fields. Changes in V4: - update clock apis. - remove unused structures. Change-Id: I8ff400922ae594f558cf73a5aaa433a3a93347c2 Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09sc7180: clock: Add display external clock in corebootTaniya Das
Add support for display external clock in coreboot for SC7180. Tested: Display clocks are configured. Change-Id: Ida222890252b80db738fa1f685b212b3f7c6e689 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09trogdor: Change Memlayout to increase QcLib region from 512 to 596kBAshwin Kumar
Change-Id: I49008ea9bc6254c745352b2e8ee965ddc2e8e5e4 Signed-off-by: Ashwin Kumar <ashk@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09trogdor: SoC makefile blob supportashk
Following blobs will includes with SoC makefile: * AOP * BOOT * QTISECLIB * QCSEC * QUPV3FW Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Signed-off-by: Ashwin Kumar <ashk@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09soc/ti/am335x: Fix MLO buildSam Lewis
Allows the AM335X to boot from the coreboot generated MLO by: - Fixing the load address in the MLO header to be the start of SRAM - Fixing the way that the bootblock size is calculated (which is embedded into the MLO so that the MLO knows how much to load into SRAM). The previous method relied on parsing cbfstool output - the output has changed format since this was originally written so this no longer works. Directly using the filesize of the built binary is probably a more stable way of doing this. As part of this, the start addresses of SRAM and DRAM were fixed to be consistent with the AM335x Technical Reference Manual (spruh73, rev Q). TEST: Booted Beaglebone Black from MLO placed at offset 0x00 on an SD card Change-Id: I514d7cda65ddcbf27e78286dc6857c9e81ce6f9e Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44381 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09soc/intel/common/block/uart/Kconfig: Drop unused symbolsAngel Pons
They are not referenced anywhere. Change-Id: Iff2d3b0063da5796e0bff1ada08b0a544c3f9a5a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-09-09soc/intel/xeon_sp: Select CPU_INTEL_COMMONAngel Pons
This is an intermediate step to have SOC_INTEL_COMMON_BLOCK_CPU select CPU_INTEL_COMMON directly, to avoid dependency problems. Tested with BUILD_TIMELESS=1: Without including the config file in the coreboot.rom, both OCP Tioga Pass and Delta Lake remain identical. Change-Id: I565e75869be730e7c2fe7114b829941bc9890e6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45041 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09soc/intel/cannonlake: Add PCIe ports on PCH-HPatrick Rudolph
Fixes complains about missing INT configuration by the pciexp kernel modules. Tested with Linux 5.5 on Prodrive Hermes. Change-Id: I277f592cd8d2c86a9c7ba4b34d3f703f7d593582 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-09apollolake: Define MAX_CPUS at SoC scopeAngel Pons
The three Intel Apollo Lake boards (apl_rvp, leafhill and minnow3) do not define MAX_CPUS, which would then default to 1. Since this is most likely an oversight, use the same value as other Apollo Lake boards. To ensure this does not happen again, factor out MAX_CPUS to SoC scope. Change-Id: I5ed98a6b592c8010b59eca7ff773ae1ccc4cd7b1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45144 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09geminilake: Factor out MAX_CPUS valueAngel Pons
Both Gemini Lake boards in the tree use the same value. Change-Id: Ib6bd05206026736fd7e3d44b49e4d8ba217c2708 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-09soc/intel/apollolake: Rename `SOC_INTEL_GLK` symbolAngel Pons
For consistency with other platforms, use `SOC_INTEL_GEMINILAKE`. Change-Id: I06310e5a9bca6c9504f19a6c2fe9b26626f290d4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-09vendorcode/intel/fsp/fsp2_0/adl: Add FSP header file version 1332Subrata Banik
List of changes: 1. Select FSP_HEADER_PATH 2. Select FSP_FD_PATH 3. Select PLATFORM_USES_FSP2_2 4. Select UDK_202005_BINDING Change-Id: Ic5b09bad3c23b84c6ff6b1ea9e1dc684d7463c27 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-09-08pci_ids: Add Alder Lake DTT PCI IDsSubrata Banik
Add PCI IDs for Intel's Dynamic Tuning Technology (DTT) for ADL. Also add NULL terminator at end of pci_device_ids. Change-Id: If25b1f562567a833683b0b8796bd1d6cac0bd490 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45140 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08pci_ids: Add Alder Lake IPU PCI IDsSubrata Banik
Add PCI IDs for Intel's Image Processing Unit (IPU) for ADL. Also add NULL terminator at end of pci_device_ids. Change-Id: I327828d676422fc6162fadffd9b39529ecb89ace Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08soc/mediatek/mt8192: Add SPI flash controller dual read functionCK Hu
Support SPI flash dual read funciton which change spi mode (1-1-1) to dual mode (1-1-2). Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: Iabd3668fc4bc42137b7743144fc1cced4fe72737 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44852 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08soc/intel/baytrail: Add missing GSM size definitionsAngel Pons
Change-Id: I456591f63f463c5cec1cbf3c1633bdb61be92d29 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44935 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08soc/intel/denverton_ns/Kconfig: Drop unused 'IQAT_MEMORY_REGION_SIZE'Elyes HAOUAS
Change-Id: I25cfc61b7a25b68dd22573a88933e03931a755ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian <d.guckian20@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08soc/intel/tigerlake: Skip GPIO configuration from FSPSrinidhi N Kaushik
FSP v3333 or later, provides a new UPD to Skip configuring GPIO settings from FSP. coreboot should provide all the required GPIO configuration for the platform when this UPD is set. BUG=b:166790597, b:146390704 BRANCH=none TEST=build and boot volteer proto2 Cq-Depend:chromium-internal:3240396,chromium-internal:2870145 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: If32f35a188d510db8e4d8973cae78297d49a9240 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44913 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08soc/intel/elkhartlake: Update SA & PM related definitionsTan, Lean Sheng
1. Update SA base address & size 2. Update GBE control bit register value Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I1f5036c9cd75682fcf239170bcb257ffaa002e7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-08soc/intel/elkhartlake: Update PMC related register definitionsTan, Lean Sheng
Update ABase, PMC GPIO value sets and PMC register base address. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Iba43b791cab0665ddebfbed68b7e2d15406ad206 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-08soc/intel/elkhartlake: Add CPU, SA, PCH & IGD DIDs TableTan, Lean Sheng
1. Add CPU, SA, PCH & IGD DIDs table into report_platform.c 2. Add additional EHL SA DID in pci_ids.h Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I5c98089873b17f82560eba13c7de3353b6d3e249 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-08soc/intel/elkhartlake/acpi: Copy acpi directory from jasperlakeTan, Lean Sheng
Clone entirely from Jasperlake List of changes on top off initial jasperlake clone 1. Rename from jasperlake to elkhartlake 2. Remove irelevant devices asls (ipu,ish,camera clock,gpio_op) Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I5e77081d1673cc0ca97edc63e9996c045ab6e9b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44812 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08soc/intel/elkhartlake: Do initial SoC commit till ramstageTan, Lean Sheng
Clone entirely from Jasperlake List of changes on top off initial jasperlake clone 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Replace "jsp" with "mcc" 4. Rename structure based on Jasperlake with Elkhartlake 5. Clean up upd override in fsp_params.c will be added later 6. Sort #include files alphabetically as per comment 7. Remove doc details from espi.c until it is ready 8. Remove pch_isclk & camera clocks related codes 9. Add new #define NMI_STS_CNT & NMI_EN as per comment Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I372b0bb5912e013445ed8df7c58d0a9ee9a7cf35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-08soc/intel/apollolake: Hook up ENABLE_VMXAngel Pons
Unlike other platforms, Apollo and Gemini Lake have VmxEnable on FSP-S. Note that this will enable VMX by default on both of these platforms. Change-Id: I6a4470e0e64b10f07edfcf270bb02c7cd6a8fa1a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-09-08soc/intel/apollolake: Select CPU_INTEL_COMMONAngel Pons
This is an intermediate step to have SOC_INTEL_COMMON_BLOCK_CPU select CPU_INTEL_COMMON directly, to avoid dependency problems. Tested with BUILD_TIMELESS=1, UP Squared does not change. Gemini Lake already selects this through SOC_INTEL_COMMON_BLOCK_SGX. Change-Id: If737fa6d8700f435c8692c80244f0e71657c2236 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-09-08soc/intel/broadwell: Drop `gpu_panel_port_select`Angel Pons
The corresponding bits in PP_ON_DELAYS are reserved MBZ. Change-Id: I9789a7d50c4bce2ccad0bf476f877db25e3ff82e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-08soc/intel/tigerlake: Add SMRR Locking supportTim Wawrzynczak
The SMRR MSRs can be locked, so that a further write to them will cause a #GP. This patch adds that functionality, but since the MSR is a core-level register, it must only be done once per core; if the SoC has hyperthreading enabled, then attempting to write the SMRR Lock bit on the primary thread will cause a #GP when the secondary (sibling) thread attempts to also write to this MSR. BUG=b:164489598 TEST=Boot into OS, verify using `iotools rdmsr` that all threads have the Lock bit set. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4ae7c7f703bdf090144637d071eb810617d9e309 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08soc/intel/common: Add SMRR Lock Supported bit definition for MTRR_CAPTim Wawrzynczak
The IA32_MTRR_CAP register has a bit which indicates that the SMRR MSRs can be "locked" and this patch adds the definition for that. BUG=b:164489598 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1254fb40c790f2a83dd11c2aabcf9bdf922b9395 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08soc/mediatek/mt8192: Add SPI flash controller DMA read functionCK Hu
To speed up SPI flash read, enable DMA read function. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: Ic1679ef7940258350feeadac50ad8ea407fd7b90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-09-06soc/intel/apl: Add panel power and backlight configurationNico Huber
Change-Id: Id8892ac7aafce1006831e2d9f2806919f5950756 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-06soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by defaultMichael Niewöhner
Fsp configures the USB over-current pin and overrides the according pad configuration to NF1, regardless of the port being configured as disabled. Thus, set the OC pin to 0xff ("disabled") in this case to prevent this. This allows us to skip setting USBx_PORT_EMPTY in the devicetree for disabled USB ports. Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45112 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-05soc/intel/alderlake/bootblock: Do initial SoC commit till bootblockSubrata Banik
List of changes: 1. Add required SoC programming till bootblock 2. Include only required headers into include/soc 3. Add CPU/PCH/SA EDS document number and chapter number 4. Include ADL-P related DID, BDF Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I204e692fabb84fce297bebee465f4ca624c6fe56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-04soc/intel/{jasperlake,tigerlake}/Kconfig: Drop redundant 'select ↵Elyes HAOUAS
CPU_INTEL_COMMON_SMM' CPU_INTEL_COMMON_SMM is set to yes if CPU_INTEL_COMMON at cpu/intel/common/Kconfig. Change-Id: I7c8e1bb6b7c3199a24711b64a6cbba4de190c6d9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-04soc/intel/cnl: Enable HECI3 depending on devicetreeFelix Singer
Currently HECI3 gets enabled by the option Heci3Enabled, but this duplicates the devicetree on/off options. Therefore depend on the devicetree for enablement of the HECI3 controller. All corresponding mainboards were checked if the devicetree configuration matches the Heci3Enabled setting, and divergent devicetrees were adjusted. Change-Id: Ic7d52096aee225c2ced1e1bc29ca850fe5073edc Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44579 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-04soc/intel/tigerlake: Remove unused PID_SDX macroSubrata Banik
Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I177a146643f2196018182502fff8d82830e139dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/45019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-03soc/amd/picasso/acpi: Remove padding in IVRS table caused by realignment.Jason Glenesk
Previous CL (1916f8969b10e27fe06b3e0eb1caae632bd947f6) misinterpreted spec as requiring size alignment on all IVHD device entries. The correct requirement specifies only for 4-byte entries. The unneeded realignments result in gaps in the table. The kernel hangs in early boot due to the malformed table. Remove 8-byte entry alignment. BUG=b:166519072 TEST=Boot fully to morphius board with and without amd_iommu kernel parameter. Confirm IVRS contains no alignment gaps/corruption. Change-Id: Iddcff98279be1d910936b13391dd2448a3bb2d74 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-03soc/amd/picasso: Set max_speed_mts and configured_speed_mtsRob Barnes
ddr_frequency is deprecated. Set max_speed_mts and configured_speed_mts instead. This will result in SMBIOS type 17 displaying more accurate speed information. BUG=b:167218112 TEST=Boot ezkinil and observe dmidecode -t17 dmidecode -t17 # dmidecode 3.2 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x000B, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR4 Type Detail: Synchronous Speed: 3200 MT/s Manufacturer: Unknown (0) Serial Number: 00000000 Asset Tag: Not Specified Part Number: MT40A512M16TB-062E:J Rank: 1 Configured Memory Speed: 2400 MT/s Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I1879676ea9436b6d19c768f1b78487a4e179f8d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44984 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-03soc/intel/cnl: Allow using the remaining Comet Lake FSPsFelix Singer
To allow using the 3 remaining Comet Lake SoCs, add a new Kconfig option for each of them and configure the paths to FSP header files and FSP binary. Change-Id: I4272a6ee08e19769a8a17c93bb3ce2421be0bbc9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Michael Niewöhner
2020-09-033rdparty/fsp: Update submodule pointer to current masterFelix Singer
Change-Id: I50bac5a70425495832649e0d6d6e91aad623f25c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-03soc/intel/cnl: Add new Kconfig option which matches its FSPs nameFelix Singer
Since there are 4 different versions of FSPs for the Comet Lake platform, add a new Kconfig option for the currently used SoC being able to differ between the various SoCs and FSPs. The new Kconfig option selects the Comet Lake SoC as base for taking over its specific configuration and is only used for configuring the path to its specific FSP header files and FSP binary. Also, adjust all related mainboards so that their Kconfig selects the new option. For details, please see https://github.com/intel/FSP/tree/master/CometLakeFspBinPkg Built System76/lemp9 with BUILD_TIMELESS=1 before and after this patch and both images are equal. Change-Id: I44b717bb942fbcd359c7a06ef1a0ef4306697f64 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-03soc/amd/picasso: Only build PSP bootloader & verstage into ROMartin Roth
The PSP bootloader and verstage are only used out of the RO region, so don't build them into the RW sections. BUG=None TEST=Build & Boot BRANCH=zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ic7bcb9a6a78926325e80755c010bb047e4a9485c Reviewed-on: https://review.coreboot.org/c/coreboot/+/44990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03soc/amd/picasso: Add config for PSP verstage signing tokenMartin Roth
This allows a platform to specify the location of the signing token for the PSP verstage, and build it into the firmware image. BUG=b:166108929 TEST=Build file into PSP firmware, verify that it's present and has the correct ID. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I182ad9b48a2776ccd29ead0f54cfe14c5bf45560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03soc/amd/picasso: Allow use of pre-built PSP verstageMartin Roth
To use a signed PSP verstage, we're going to need to build it first, then sign and store the binary. This patch allows the stored (signed) verstage binary to be used. BUG=b:166108929 TEST=Build with existing verstage binary instead of re-building it. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5cbceca3b75f05c5460190b1c829d1ffaab2c736 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03soc/amd/picasso: Move DRAM end to after transfer bufferJosie Nordrum
Move PSP_SHAREDMEM_DRAM_END after _etransfer_buffer to ensure that the transfer buffer actually lives within the 32KiB that is supported to be transferred. Resulting symbol address change in bootblock.debug file summarized below. BEFORE: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02019000 T _epsp_sharedmem_dram 02019000 T _preram_cbmem_console 0201a600 T _epreram_cbmem_console 0201a600 T _timestamp 0201a800 T _etimestamp 0201a800 T _fmap_cache 0201ac52 T _efmap_cache 0201ac52 T _etransfer_buffer AFTER: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02014040 T _preram_cbmem_console 02015640 T _epreram_cbmem_console 02015640 T _timestamp 02015840 T _etimestamp 02015840 T _fmap_cache 02015c92 T _efmap_cache 02015c92 T _etransfer_buffer 02019000 T _epsp_sharedmem_dram BUG=b:167243965 BRANCH=None TEST=checked 'cbmem -1' for FMAP error after ec reboot Signed-off-by: Josie Nordrum <josienordrum@google.com> Change-Id: I9b482aced5deb40bd87d19d9c42585d8a6db5fc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45045 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02soc/intel/tigerlake: Add mainboard hook for overriding SoC configJes Klinke
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x BUG=b:154333137 Change-Id: Iff28e4a29fab5c22c410cdc743d0402134c4ac56 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/44914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-02src: Drop redundant 'select BOOTBLOCK_CONSOLE'Elyes HAOUAS
BOOTBLOCK_CONSOLE is already set to yes in console/Kconfig file. Change-Id: I2a4ee517795bc7b378afc5eae92e2799ad36111b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-02soc/intel/xeon_sp/Kconfig: Drop redundant 'select POSTCAR_CONSOLE'Elyes HAOUAS
POSTCAR_CONSOLE is already set to yes in console/Kconfig file. Change-Id: If520c33f5e36d569511b2441bf23aa90180591c7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-02{nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)Elyes HAOUAS
Change-Id: I049441dd9074659effc1092dce08224974d60a2c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-09-01{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistentSubrata Banik
Convert 0X -> 0x Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-31soc/intel/elkhartlake/romstage: Do initial SoC commit till romstageTan, Lean Sheng
Clone entirely from Jasperlake List of changes on top off initial jasperlake clone 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Rename structure based on Jasperlake with Elkhartlake 4. Clean up upd override in fsp_params.c, will be added later 5. Temporarily remove _weak attributes in fsp_param & romstage.c 6. Add required headers into include/soc/ from jasperlake directory Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: If2bbe0b8a12bb78b3650f9d0a60f002f7eacb513 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-08-31soc/intel/elkhartlake/bootblock: Do initial SoC commit until bootblockTan, Lean Sheng
Clone entirely from Jasperlake This patch is based on TGL_upstream series patches: https://review.coreboot.org/c/coreboot/+/36550 List of changes on top off initial jasperlake clone 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Rename structure based on Jasperlake with Elkhartlake 6. Add required headers into include/soc/ from JSL directory Elkhart Lake specific changes will follow in subsequent patches. 1. soc/intel/elkhartlake: Update Kconfig Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I9f91c1efa81a358b1f59e032e209e07b62d54613 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-31soc/amd/picasso/southbridge: make GPP clock outputs configurableFelix Held
Make the general purpose PCIe clock outputs configurable to be either permanently enabled, permanently disabled or dynamically enabled via their corresponding external #CLK_REQx pins in the board's devicetree. BUG=b:149970243 BRANCH=zork Change-Id: I3f5760c0b869e8a9416ba9b57d182a88a2eb5e44 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31soc/amd/picasso/southbridge.h: rename GPP clock setting offsetsFelix Held
The _SHIFT postfix is a bit clearer than the _SHL one and more in line with the names used for this kind of defines in coreboot. The documentation on that register is currently wrong and will hopefully be fixed in the future; the defines should now match the hardware. BUG=b:149970243 BRANCH=zork Change-Id: I977f107d466521484ca13fa1f4dd86a50c8150d7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31soc/amd/picasso/southbridge.h: replace GPP_CLK_REQ_MAP_* with macrosFelix Held
Replacing the existing defines with macros makes them easier to use in a function that applies the setting for a certain GPP/GFX clock output. Also add macros for statically enabling or disabling the clock outputs and not only for configuring them as controlled by the #CLK_REQx pins. BUG=b:149970243 BRANCH=zork Change-Id: I14198f224639721fe6ca71ca3dcd9cb413a587d5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31soc/amd/picasso/southbridge.h: remove OSCOUT*_CLK_OUTPUT_ENB definitionsFelix Held
On Picasso MISC_CLK_CNTL1 doesn't contain OSCOUT[12]_CLK_OUTPUT_ENB and this was probably just copied over from stoneyridge. BUG=b:149970243 BRANCH=zork Change-Id: I32f459026c4e8632672123681b20736245f198b2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44886 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31{intel/gma,include/device}: Delete unused 'drm_dp_helper.h' fileElyes HAOUAS
'drm_dp_helper.h' file is duplicated and not used. Change-Id: Ibb08f7ff91c3914940dfe899be331b06e292c7c9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-08-29PCI IDs: Add PCI ID for CML DPTF/DTT PCI deviceEdward O'Callaghan
This PCI ID is required in order for the CML devices to perform SSDT generation for DPTF. CML Processor, EDS, Vol 1, Table 9-5, Section 9.2. BUG=b:158986928 BRANCH=puff TEST=builds Signed-off-by: Edward O'Callaghan <quasisec@google.com> Change-Id: I94aea6b9e0f60656827daada7b2cc2741604b8b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Andrew McRae <amcrae@google.com>
2020-08-28amd/picasso/psp_verstage: add vboot rsa functionKangheui Won
Add vb2ex_hwcrypto_rsa_verify_digest function for verifying rsa signature against digest using PSP svc. This function will be later used by vboot to accelerate rsa verification. BUG=b:163710320, b:161205813 TEST=build zork firmware with vboot modification, confirm it's booting and boot time is reduced by ~230ms. Change-Id: Ic5c1d13092db5a84191642444f3df9c26925e475 Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44456 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28soc/amd/picasso/romstage: Set SATA enable UPD if controller is enabledMatt Papageorge
FSP has recently added support for a UPD switch to power gate SATA. This change adds the coreboot side of the feature. To avoid having two SATA enable options, the value of the sata_enable UPD is determined by the enable state of the AHCI controller in the platform devicetree. BUG=b:162302027 BRANCH=zork TEST=Verify AHCI controller can be hidden/disabled. Change-Id: I48bf94a7e6249db6079a6e3de7456a536d54a242 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44067 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww34 release and adapt socJonathan Zhang
Intel CPX-SP FSP ww34 release added some features: a. change DDR frequency limit. b. define MRC debug message verbosity level. c. enable/disablee of PCH DCI. In addition, there are some changes to HOB data structures. Update UPD and HOB header files and adapt soc accordingly. TESTED=booted on YV3 DVT to target OS command line. Also rebooted okay. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iadbf5dc850c445f988bc7f07a24165abed2298c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44685 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28soc/intel/tigerlake: add ddr4-spd-empty.hexAaron Durbin
In generating the potential spds the ddr4-spd-empty.hex was accidentally omitted. Generated from: go run util/spd_tools/ddr4/gen_spd.go src/soc/intel/tigerlake/spd/ \ util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt TGL Change-Id: Ic8b9449830fb5405ebf138ebd54f41b0f76ba584 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44908 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28mb/google/zork: Switch zork to use spd_toolsRob Barnes
Switch all zork boards to use generated generic SPDs from spd_tools. HMAA1GS6CMR6N-VK is unused by Ezkinil, and all other boards, so it was removed. picasso/Makefile.inc was updated to populate the 2nd APCB channel based on APCB_POPULATE_2ND_CHANNEL. This removes the need to suffix spd entires with _x1/_x2. Command to generate files: $ find src/mainboard/google/zork/variants/ -maxdepth 1 -type d | grep -v '/$' | while read b; do n=$(basename ${b}); if [ "${n}" = "baseboard" ]; then continue fi go run util/spd_tools/ddr4/gen_part_id.go src/mainboard/google/zork/spd \ src/mainboard/google/zork/variants/${n}/spd \ src/mainboard/google/zork/variants/${n}/spd/mem_parts_used.txt done BUG=b:162939176 TEST=Boot ezkinil and dalboz check dmidecod -t17 Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I0553858f83d3d1e90cf35bece108768f004a29a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44480 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28util: Add memory parts needed by zork boardsRob Barnes
Add memory parts needed by zork boards. Attributes are derived from data sheets. BUG=b:162939176 TEST=Compared generated SPDs with data sheets and checked in SPDs Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I67f205f9af24bbc5c12656be1f363a15fe975955 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44447 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28util/gen_spd: translate DeviceBusWidth to die bus widthNick Vaccaro
If a memory part is a x16 part that has two dies and only a single rank, then the x16 describes the part width (since this solution will need to be a stacked solution) and as such, we must translate the DeviceBusWidth to the "die bus width" instead. Change DeviceBusWidth variable name to PackageBusWidth to be more descriptive BUG=b:166645306, b:160157545 TEST=run gen_spd and verify that spds for parts matching description above changed appropriately. Change-Id: Ia6f3ca109d344b7a015da28125a94ce10d2bdfb8 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-28soc/mediatek/mt8192: Use SPI-NOR as flash controllerCK Hu
Add a SPI-NOR flash controller which supports pio mode. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: I1e38672a532dd8234b3ef24c84113888c8795810 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-28util: rename lp4x spds to include "lp4x-" in nameNick Vaccaro
Change lp4x spd names to include lp4x memory type (eg. lp4x-spd-1.hex). BUG=b:160157545 TEST=run gen_part_id for volteer variants and verify that it changed spd names to prepend the "lp4x-" to the filename.. Change-Id: I0c59da7eb78f34640aad2e852ca725d3e8571a8e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44784 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28util: volteer/dedede: move generic SPDs to common locationNick Vaccaro
Now that generic SPD files have the memory type prepended to the filename, they can be stored in the same location. This CL moves the generic SPDs to the new location. Change the ddr4 gen_part_id.go and gen_spd.go tools to use "ddr4_spd_manifest.generated" instead of "spd_manifest.generated". Change the lpddr4x gen_part_id.go and gen_spd.go tools to use "lp4x_spd_manifest.generated" instead of "spd_manifest.generated". Move TGL DDR4 and LPDDR4x generic SPDs into a common location. Move JSL DDR4 and LPDDR4x generic SPDs into a common location. Change the volteer/spd/Makefile.inc to use the new path for the spds. Change the dedede/spd/Makefile.inc to use the new path for the spds. BUG=b:165854055 TEST="emerge-volteer coreboot" and verify all variants build correctly. Change-Id: I83b088cb718d15ffd3012c84a12b5231ae84a3e4 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44648 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27symbols: Change implementation details of DECLARE_OPTIONAL_REGION()Julius Werner
It seems that GCC's LTO doesn't like the way we implement DECLARE_OPTIONAL_REGION(). This patch changes it so that rather than having a normal DECLARE_REGION() in <symbols.h> and then an extra DECLARE_OPTIONAL_REGION() in the C file using it, you just say DECLARE_OPTIONAL_REGION() directly in <symbols.h> (in place and instead of the usual DECLARE_REGION()). This basically looks the same way in the resulting object file but somehow LTO seems to like it better. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I6096207b311d70c8e9956cd9406bec45be04a4a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-08-27soc/intel/common: Include Elkhart Lake SA IDsTan, Lean Sheng
Add additional Elkhart Lake specific SA IDs. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I41af9b17b8121f3b47f2242d9beeec297893b378 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40854 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27soc/intel/common: Add Elkhart Lake B0 CPU IDTan, Lean Sheng
Add Elkhart Lake B0 CPU ID. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I90fab9a6392443005ee7224049931c687cb77c0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/44798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-08-26soc/mediatek: Include addressmap.h in gpio_common.hCK Hu
The gpio_common.h needs EINT_BASE from addressmap.h. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: I20834e38343410526da0a489fed907acbf479d02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-26soc/intel/tigerlake: Rename pch_init() codeAlexey Buyanov
Rename the pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=successfully built and booted TGLRVP Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com> Change-Id: Ib7450fcdc3024dfb5e375a54f9bdcdca9bc373d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-17 18:24:19 +0000