Age | Commit message (Expand) | Author |
2020-08-07 | src/soc/intel/icelake: Allow option to use USE_INTEL_FSP_MP_INIT | Subrata Banik |
2020-08-06 | soc/intel/tigerlake: add common routine for DDR init | Nick Vaccaro |
2020-08-06 | soc/intel/common/block/cpu: Refactor init_cpus function | Subrata Banik |
2020-08-06 | soc/mediatek/mt8183: Set MMU default map length to 8GB befor mem init | Huayang Duan |
2020-08-06 | soc/mediatek/mt8183: Add ddr geometry to support 6GB, 8GB DDR bootup | Huayang Duan |
2020-08-06 | soc/mediatek/mt8183: Adjust tRFCab and tRFCpb by the density value | Huayang Duan |
2020-08-06 | soc/mediatek/mt8183: Add missing register settings for channels | Huayang Duan |
2020-08-05 | {sb,soc}/intel/*/acpi/lpc.asl: Drop commented-out code | Angel Pons |
2020-08-05 | {nb,soc}/intel: Use get_current_microcode_rev() for ucode version | Subrata Banik |
2020-08-05 | mb/google/zork: keep the c-state IO base address alignment | Chris Wang |
2020-08-05 | src: Use space after 'if', 'for' | Elyes HAOUAS |
2020-08-05 | src/soc/intel/common: Make top_of_ram till TOLUD region mmio_resource | Subrata Banik |
2020-08-05 | soc/intel/common: Include Alder Lake device IDs | Subrata Banik |
2020-08-04 | soc/intel/skylake: Add RMRRs after all DRHDs | Angel Pons |
2020-08-04 | soc/intel/broadwell: Add RMRRs after all DRHDs | Angel Pons |
2020-08-04 | soc/intel/apollolake/acpi.c: Add RMRRs after all DRHDs | Angel Pons |
2020-08-04 | soc/amd/picasso/acpi: clean up global NVS | Felix Held |
2020-08-04 | soc/intel/baytrail: Factor out `acpi_fill_madt()` | Angel Pons |
2020-08-03 | soc/amd/picasso: set is_rv to 1 for RV family | Akshu Agrawal |
2020-08-03 | soc/intel/baytrail: Add MRC SMBus workaround | Mate Kukri |
2020-08-03 | soc/intel/xeon_sp/cpx: configure STACK_SIZE | Jonathan Zhang |
2020-08-03 | soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2 | Jonathan Zhang |
2020-08-03 | src/soc/intel/jasperlake: Update SD card ACPI device | Aamir Bohra |
2020-08-03 | Change all assert(0) to BUG() | Julius Werner |
2020-08-03 | qualcomm/sc7180: Fix TLMM assignments for GPIOs 29, 31 and 32 | Julius Werner |
2020-08-03 | soc/intel/tigerlake: Invoke PCIe root port swapping | Caveh Jalali |
2020-08-02 | soc/intel/baytrail/northcluster.c: Clean up comments | Angel Pons |
2020-08-02 | soc/intel/baytrail/sata.c: Fix SATA init sequence | Angel Pons |
2020-08-02 | soc/intel/baytrail: Add native refcode replacement | Mate Kukri |
2020-08-02 | soc/intel/baytrail/northcluster.c: Rename variable | Angel Pons |
2020-08-02 | soc/intel/baytrail/northcluster.c: Tidy up long lines | Angel Pons |
2020-08-02 | soc/intel/braswell/northcluster.c: Tidy up long lines | Angel Pons |
2020-08-02 | soc/intel/braswell/northcluster.c: Rename macro | Angel Pons |
2020-08-01 | soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecated | Subrata Banik |
2020-07-31 | soc/intel/cannonlake: Fix DMAR when no iGPU is present | Patrick Rudolph |
2020-07-31 | soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE | Jonathan Zhang |
2020-07-30 | smbios: Fix type 17 for Windows 10 | Patrick Rudolph |
2020-07-30 | mb/amd,google/mandolin,zork: Set EFS SPI platform config | Matt Papageorge |
2020-07-30 | amd/common/block/spi: Add EFS SPI configurations to Kconfig | Matt Papageorge |
2020-07-30 | soc/amd/picasso: Split ops for internal and external PCIe GPP bridges | Furquan Shaikh |
2020-07-29 | soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold | John Zhao |
2020-07-29 | soc/intel/skylake: Enable HDA depending on devicetree configuration | Felix Singer |
2020-07-29 | soc/intel/skylake: Enable HECI3 depending on devicetree configuration | Felix Singer |
2020-07-29 | soc/intel/skylake: Enable eMMC depending on devicetree configuration | Felix Singer |
2020-07-29 | soc/intel/skylake: Enable TraceHub depending on devicetree configuration | Felix Singer |
2020-07-29 | soc/intel/skylake: Enable SMBus depending on devicetree configuration | Felix Singer |
2020-07-29 | soc/intel/skylake: Enable LAN depending on devicetree configuration | Felix Singer |
2020-07-29 | soc/intel/skylake: Enable SATA depending on devicetree configuration | Felix Singer |
2020-07-29 | src/soc/rockchip: Add missing <{stddef,stdint}.h> | Elyes HAOUAS |
2020-07-29 | soc/intel/tigerlake: Set default USB3 de-emphasis to -3.5dB | Duncan Laurie |
2020-07-29 | soc/intel/jasperlake: Clean up report_cpu_info() function | Usha P |
2020-07-29 | util/apcb: Strip SPD manufacturer information | Rob Barnes |
2020-07-29 | src/soc/samsung/exynos{5250,s5420}: Add missing <{stddef,stdint}.h> | Elyes HAOUAS |
2020-07-28 | soc/amd/picasso: Add controls for SMT and downcoring | Marshall Dawson |
2020-07-28 | src/soc/amd: Add include <types.h> | Elyes HAOUAS |
2020-07-28 | soc/amd/picasso: Enable VBNV_BACKUP_TO_FLASH for psp_verstage | Martin Roth |
2020-07-28 | soc/amd/picasso: Init SPI in psp_verstage | Martin Roth |
2020-07-28 | soc/amd/picasso/Makefile.inc: force an error if PSPBTLDR_FILE is not set | Ronald G Minnich |
2020-07-28 | src: Never set ISA Enable on PCI bridges | Angel Pons |
2020-07-28 | soc/intel/braswell/fadt.c: Use `ACPI_ADDRESS_SPACE_IO` macro | Angel Pons |
2020-07-28 | broadwell: Factor out PIRQ routing from devicetree | Angel Pons |
2020-07-28 | soc/intel/cannonlake: Configure SataPwrOptEnable only if SATA is enabled | Felix Singer |
2020-07-28 | soc/intel/apollolake: Simplify is-device-enabled checks | Felix Singer |
2020-07-28 | soc/intel/jasperlake: Simplify is-device-enabled checks | Felix Singer |
2020-07-28 | soc/intel/tigerlake: Simplify is-device-enabled checks | Felix Singer |
2020-07-28 | Revert "src: Remove unused include <cpu/x86/smm.h>" | Patrick Rudolph |
2020-07-27 | soc/amd: Use spi_writeX & spi_readX for all spi accesses | Martin Roth |
2020-07-27 | soc/amd/common: Move spi access functions into their own file | Martin Roth |
2020-07-27 | soc/amd/picasso: Set __USER_SPACE__ for psp_verstage | Martin Roth |
2020-07-27 | soc/amd/picasso: make USB over-current pin mapping configurable | Felix Held |
2020-07-27 | soc/intel/jasperlake: Invoke PCIe root port swapping | Karthikeyan Ramasubramanian |
2020-07-26 | soc/intel/tigerlake: Disable CPU PCIe in FSP | Shaunak Saha |
2020-07-26 | soc/intel/tigerlake: Disable VT-d and no DMAR table for pre-QS platform | John Zhao |
2020-07-26 | soc/intel/common/basecode: Implement CSE update flow | Rizwan Qureshi |
2020-07-26 | soc/amd/common/block/psp/psp_smm.c: Add missing <string.h> | Elyes HAOUAS |
2020-07-26 | src/soc/qualcomm: Add include <types.h> | Elyes HAOUAS |
2020-07-26 | src/soc/mediatek: Add include <types.h> | Elyes HAOUAS |
2020-07-26 | src/soc/intel: Add include <types.h> | Elyes HAOUAS |
2020-07-26 | soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG | Maxim Polyakov |
2020-07-26 | soc/intel/common/hda: Add HDA ID for Jasper Lake | yan.liu |
2020-07-26 | soc/intel/jasperlakelake: Rename pch_init() code | Usha P |
2020-07-26 | src: Update bare access to BOOL CONFIG_ vals to CONFIG() | Martin Roth |
2020-07-26 | src: Change BOOL CONFIG_ to CONFIG() in comments & strings | Martin Roth |
2020-07-26 | src: Remove whitespace between 'sizeof' and '(' | Elyes HAOUAS |
2020-07-26 | {sb,soc}/intel/**/*.c: Use macros for PCI COMMAND bits | Angel Pons |
2020-07-26 | soc/amd/common: Refactor and consolidate code for spi base | Martin Roth |
2020-07-26 | soc/amd/picasso: Update postcode value | Martin Roth |
2020-07-26 | Kconfig: Remove unnecessary choice names | Martin Roth |
2020-07-26 | smp/spinlock: Do not define barrier() globally | Kyösti Mälkki |
2020-07-26 | arch/x86: Move cpu_relax() | Kyösti Mälkki |
2020-07-26 | cpu,soc/intel: Drop select SMP | Kyösti Mälkki |
2020-07-26 | src: Remove unused 'include <cbmem.h>' | Elyes HAOUAS |
2020-07-26 | src: Remove extra lines in license header | Elyes HAOUAS |
2020-07-26 | skylake boards: Factor out copy-pasted PIRQ routes | Angel Pons |
2020-07-26 | src: Remove unused include <cpu/x86/smm.h> | Elyes HAOUAS |
2020-07-26 | amd/picasso: rework USB2 PHY tune parameter handling | Felix Held |
2020-07-26 | soc/skylake: Configure SATA options only if SATA is enabled | Felix Singer |
2020-07-25 | soc/amd/picasso: don't apply unconfigured USB2 PHY tune parameters | Felix Held |
2020-07-25 | soc/intel/baytrail/southcluster.c: Align with Braswell | Angel Pons |
2020-07-25 | soc/intel/baytrail/include/soc/irq.h: Add braces | Angel Pons |