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2020-08-17soc/intel/common: Move common HDA registers to <device/azalia_device.h>Elyes HAOUAS
Change-Id: I9ea191e5076e2f055405dc34d46dbbb8cfb0015e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44106 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17soc/intel/skylake: Call mainboard ACPI sleep methodsBenjamin Doron
Skylake mainboards also can implement ACPI functionality surrounding sleep. Tested on an Acer Aspire VN7-572G (Skylake-U). Change-Id: I969d92c7445b01964d92d28b21f6667614ea82e7 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17soc/intel/jasperlake: Add IGD Device IDKrishna Prasad Bhat
Add IGD Device ID for Jasperlake. Reference is taken from Jasperlake EDS volume 1(Document Number: 613601). TEST=Build and boot Jasperlake platform. Change-Id: Iab3ba286f36afbf9533ac3cc62891fa390ca2441 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44000 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17soc/intel/jasperlake: Add FSP UPDs for minimum assertion widthsV Sowmya
Add the FSP UPDs for the chipset minimum assertion widths and Power cycle duration to the chip options which can be configured per mainboard. * PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy * PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy * PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy * PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy * PchPmPwrCycDur: PCH PM Reset Power Cycle Duration * Check to avoid violating the PCH EDS recommendation for the PchPmPwrCycDur setting. BUG=b:159104150 Change-Id: I042e8e34b7dfda3bc21e5f2e6727cb7692ffc7f7 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-08-17soc/mediatek/mt8192: Initialize watch dog in bootblockCK Hu
Initialize watch dog so the system won't reboot on timeout. In addition, print the reason of reboot triggered by watch dog. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: I7e849659700218f1c50365c2d68a32be2f703d94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-17soc/mediatek/mt8192: Initialize mmu in bootblockCK Hu
Initialize CPU mmu and config range. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: I5ba405dab87d51d373704657ccb44c07c7249041 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-15soc/amd/picasso: use FADT devicetree configuration optionsMartin Roth
Two of the items in the FADT ACPI table frequently are partially board- specific, so let's make it easy to update them via devicetree settings. - fadt_boot_arch 0="legacy free" which while reasonable, probably isn't what will be wanted by most mainboards, so this should generally get updated in the specific devicetree. - In fadt_flags all chipset-specific flags get set while the mainboard has to set all other flags that it needs to have set. This patch changes the default for fadt_boot_arch. Change-Id: I6e8d0c60cadfdd24b6926703b252abbc56d436de Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-14soc/intel/tigerlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 5KBRavi Sarawadi
This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 3KB to 5KB to fix *** Pre-CBMEM romstage console overflowed, log truncated! *** issue. Bug=None Branch=None Test=Boot Delbin and check 'cbmem -c | more' for full log message. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Id2ea64feb92ec29df5402b2fb1bac3ff73cc5bb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-14soc/intel/skylake: Refactor PEG configurationFelix Singer
Simplify some if-blocks which are used for the configuration, enablement and disablement of the PEG devices. This changes the logic of the code, since it configures PegxEnable before the if-blocks, where x is the number of the PEG device, and the further configuration of the PEG devices depends on the enablement of PegxEnable. Change-Id: I6dd88ce752ce8f0255c424d0e5b2d8ef918885a1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner
2020-08-14soc/intel/skylake: Factor out unnecessary if-else-blockFelix Singer
Move InternalGfx config option out of the if-else-block and replace the left over config option IgdDvmt50PreAlloc by a ternary expression. Also, adjust related code comments to fit the new logic of this code. This changes the logic of the code, since InternalGfx is configured first and IgdDvmt50PreAlloc depends on its value. The negation in the ternary expression is removed to improve the readability. Change-Id: I89ff17f4574a7ade228c1791f17ea072fb731775 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-14soc/intel/skylake: Use PEG definitions from pci_devs.hFelix Singer
Change-Id: I7114deed35f25e74ac508f08e9c85653a7fe39ed Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-14soc/intel/skylake: Add PEG device definitions to pci_devs.hFelix Singer
Change-Id: Ib2453425f44e2b4abd5566f454ae68b704dbc33e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-14soc/amd/picasso/acpi: Set missing RTC offsetsRaul E Rangel
The RTC Date Alarm and RTC AltCentury fields are supported on picasso. These get consumed by the linux kernel: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/third_party/kernel/v5.4/drivers/rtc/rtc-cmos.c;l=1243 BUG=b:160277722 TEST=Boot kernel and make sure suspend stress test works. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie83d7e0a06107a6de095f3e4c521d91e90920c0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/44448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-14soc/intel/xeon_sp/cpx: add VT-d supportJonathan Zhang
Intel CPX-SP FSP added support for VT-d through adding UPD parameter X2apic. Based on devicetree.cb setting, enable VT-d programming through FSP-M. When VT-d is enabled, add DMAR ACPI table. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ic66374af6e53fb847c1bdc324eb3f4e01c334a94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-08-14soc/intel/xeon_sp/cpx: remove unsupported configsJonathan Zhang
coherency_support and ats_support are not supported by CPX-SP FSP. Remove them from soc_intel_xeon_sp_cpx_config struct. Remove corresponding settings from DeltaLake devicetree.cb. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ibe1c4e88817fc4be7915e95fa829f0a4c0d947f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-08-14soc/intel/common/cse_lite: Perform a board specific resetKarthikeyan Ramasubramanian
When CSE Lite jumps from RO to RW, global reset is initiated. When AP is reset as part of global reset, in some boards TPM initialization fails. This is because AP reset is not detected by TPM hosting an older firmware version. To signal TPMs running older firmware version about AP reset, a modified reset sequence needs to be performed. Hence add support to perform board-specific reset sequence. BUG=b:162290856, b:162386991 TEST=Ensure that the device boots to OS with the board-specific reset sequence when CSE Lite jumps from RO to RW with an older and newer Cr50 firmware. Change-Id: I8663e7f25461e58e45766e2ac00d752bfa191d8b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44187 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13soc/intel/skylake: Refactor ternary expressionsFelix Singer
To be consistent with the rest of the tree, replace all left ternary expressions, which are used for device enablement / disablement, with `dev && dev->enabled`. Change-Id: Ie7afa48bf2c8bdad5a043f7cb6953d05b7b6597d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-13drivers/intel/fsp2_0: don't select FSP_USES_CB_STACK on FSP 2.0 platformFelix Held
soc/amd/picasso selected FSP_USES_CB_STACK even though it is FSP 2.0 based, so it doesn't reuse coreboot's stack, but sets up its own stack. In contrast to all other FSP 2.0 based platforms, this stack isn't in the CAR region, since AMD Picasso doesn't support CAR and the DRAM is already available when the x86 cores are released from reset. Selecting FSP_USES_CB_STACK ended up doing the right thing, but is semantically wrong. Instead of wrongly selecting FSP_USES_CB_STACK in soc/amd/picasso we take the corresponding code path if ENV_CACHE_AS_RAM is false which is only the case for non-CAR platforms. BUG=b:155501050 TEST=Timeless build results in an identical binary for amd/mandolin, asrock/h110m-dvs and intel/coffeelake_rvp11 which cover all 3 cases here. Change-Id: Icd0ff8e17a535e2c247793b64f4b0565887183d8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-08-13soc/intel/xeon_sp/cpx: add CPUID for CPX-SP A1 processorJonathan Zhang
Add CPUID for CPX-SP A1 (also called QS) processor. DeltaLake DVT server uses CPX-SP A1 processor. TESTED=booted DeltaLake DVT server to target OS. [root@localhost ~]# dmidecode -t 1 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0001, DMI type 1, 27 bytes System Information Manufacturer: Wiwynn Product Name: Delta Lake DVT Version: YoDL03 Serial Number: BZA02200122N01A UUID: 000A0A22-2C29-1ED6-8259-000055DA2BFF Wake-up Type: Reserved SKU Number: Not Specified Family: DeltaLake Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ic8975f6bf752fd685b38b2d1f0a4da41983b57f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-08-13soc/mediatek/mt8192: Add spi driverQii Wang
Add driver for MT8192 SPI controller TEST=Boots correctly on MT8192EVB Signed-off-by: Qii Wang <qii.wang@mediatek.com> Change-Id: I2094dd2f14ad19b7dbd66a8e694cc71d654a2b4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-13soc/intel/common/block: Stitch CSE blobs into FW_MAIN_X partitionsSridhar Siricilla
Add Kconfig option for CSE me_rw blob path and stitch the me_rw blob into FW_MAIN_X partitions. BUG=b:145796136 Change-Id: I1d2908e9e16858c5f333e1b10b19d18b7ca27765 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35406 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13soc/mediatek/mt8192: Add DRAM resource in ramstageCK Hu
Add DRAM resource in ramstage to load payload. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: Iac02f81fc7d47851b3bba442eb7043169fbdbcfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/44410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-13soc/mediatek/mt8192: Initialize build rulesCK Hu
The first Makefile to support building minimal stage files for MT8192 SOC. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: I2cf68805532f70f072b4e9a21ee61e2ebe4ebd9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43962 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13soc/mediatek/mt8192: Add a placeholder for the EMI driverCK Hu
Add minimal function to report SDRAM size. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: If74b6b52dd6e91d1ff40cf8460b6a03b2f3bb6f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43961 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12soc/intel/cannonlake: Set FSP-M UPD Heci1BarAddressSridhar Siricilla
The patch sets FSP-M UPD Heci1BarAddress to avoid disconnect between coreboot and FSP-M. Currently coreboot uses 0xfeda2000 as a PCI BAR address for CSE device while FSP-M uses 0xfed1a000. So, after FSP-M call, CSE's BAR address is overridden with 0xfed1a000. This causes HECI transactions to fail between FSP-M call and postcar. BRANCH=puff TEST=Verified sending HECI commands before and after FSP-M call on hatch. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I371cb658a96f5d580faff32ffab013cb6e6c492c Reviewed-on: https://review.coreboot.org/c/coreboot/+/44211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-12soc/amd/common/espi_util: rename espi_check_statusFelix Held
espi_poll_status describes better what the function actually does, since it polls the status register instead of just doing a single read to check. Change-Id: I0feeef5504bd911e1fb0a00d4f4c546df3548db2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-12soc/intel/common/block/sata: Add common SATA driverSubrata Banik
Enable PCI_COMMAND_MASTER for SATA controller to ensure device can behave as a bus master. Otherwise, the device can not generate PCI accesses. BUG=b:154900210 TEST=Able to build and boot CML and TGL platform. Change-Id: Icc6653c26900354df4ee6e5882c60cbe23a5685c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44299 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12soc/intel/tigerlake: Add IRQs for LPSS uartPatrick Rudolph
Values are taken from pci_irqs.asl. The common code will make use of those defines to generate ACPI SSDT code for LPSS uarts operating in "ACPI mode". Change-Id: I5ef93493965834cda30d70918e65de3129e547b7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44260 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12soc/mediatek/mt8192: Add PLL and clock init supportWeiyi Lu
Add PLL and clock init code. TEST=Boots correctly on MT8192EVB. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: Ia49342c058577e8e107b7e56c867bf21532e40d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-12soc/mediatek/mt8192: Add gpio driverCK Hu
Add MT8192 GPIO driver. Signed-off-by: Po Xu <jg_poxu@mediatek.com> Change-Id: I4b230aebc9eb4ca1bbf444c3a2f30159d707f37b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43959 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12soc/mediatek/mt8183: Transfer ddr geometry type to dram blobHuayang Duan
BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I3a677195f5036321939c60c8f9f1bace7c4a2e3f Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-11amd/picasso/acpi: Add power resources for UART0Kangheui Won
Follow-up for a31a769 - "amd/picasso/acpi: Add power resources for I2C and UART". Now PSP properly handles UART0 D3, we can shutdown UART0. BUG=b:158772504 TEST=suspend_stress_test for 50 cycles, * echo 1 > /sys/module/acpi/parameters/aml_debug_output * dmesg | grep FUR to check on&off for FUR0 [ 2413.647500] ACPI Debug: "AOAC.FUR0._OFF" [ 2413.736265] ACPI Debug: "AOAC.FUR0._ON" Change-Id: I25457e18b69d28a83e42c2fe02b45a3979ad58cd Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-11soc/intel/common/block/gspi: Recalculate BAR after resource allocationJes Klinke
The base address of the memory mapped I/O registers should not be cached across resource allocation. This CL will evict the cached value upon exiting the BS_DEV_RESOURCES stage. Change-Id: I81f2b5bfadbf1aaa3b38cca2bcc44ce521666821 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/44084 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11xeon_sp/cpx: Enable PCH thermal device via FSPJohnny Lin
Tested=On OCP Delta Lake, OpenBMC sensor-util can see PCH Temp readings. Change-Id: I39d0d0a982476f9fece51cfa19dcbd0da5dea690 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44075 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11soc/amd/picasso: Correct processor ACPI scopeJason Glenesk
Change namespace from _PR to _SB. Cq-Depend: chrome-internal:3208104 BUG=b:153242529 TEST=Boot a trembyle with change applied and dump SSDTs to ensure processors are in _SB scope. Change-Id: I534f02dc50756759da945cf64d5b3623b0ec9db1 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44325 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11soc/amd/common/espi_util: espi_send_command: improve error messageFelix Held
It's only an error if bits other than ESPI_STATUS_DNCMD_COMPLETE are set in the status register. If ESPI_STATUS_DNCMD_COMPLETE isn't set, the command failed, so we expect that one to be set. Change-Id: I6f1fb5a59b1ecadd6724a07212626f21fb90e7e7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-11soc/amd/common/espi_util: espi_std_io_decode: fix edge case bugFelix Held
When address and data register for the SIO control register access is passed as one I/O region with a size of 2, the corresponding special decode enable register should be used instead of a generic one to save the rather limited generic ones for other decode ranges. Change-Id: Ie54ff6afa2bd2156f7b3a3cf83091f1f932b6993 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-11soc/amd/common/espi_util: simplify espi_std_io_decode functionFelix Held
We can just return at all places where the ret variable was written before its value gets returned at the end of the function. Change-Id: Id87f41c0d9e3397879ac3d15b13179cca1a1263f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-11soc/amd/common/espi_util: make decode enable parameter uint32_tFelix Held
Since this is a bit mask applied to the raw value of a 32 bit register, this should be a 32 bit unsigned type. Change-Id: I9d9930963d8c827a84dc1f67e2f2fa8f95ab40f2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-11soc/amd/common/espi_util: make reg parameter unsignedFelix Held
Th register number passed to the low level read/write functions should never be negative. Change-Id: I5d7e117b3badab900d030be8e69ded026d659f8a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-11soc/amd/stoneyridge/acpi: clean up global NVSFelix Held
Some fields in GNVS seem to be copied over from Apollolake to Stoneyridge. This patch removes the unused fields. Change-Id: I135c4a4547668fe67e74d0ea9ae3a03c3687375f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-08-10soc/intel/apollolake: Rename UART irqsPatrick Rudolph
Use the same names as on other intel socs. Will be used in intel common uart driver. Change-Id: Ia418fefb3f925fe4d000683b5028682cf0b68a9b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-10soc/intel/apollolake: Add irq.hPatrick Rudolph
Move defines from soc_int.asl to soc/irq.h. The common code uart driver expect it to exist. Change-Id: I000a041120daa8cbe1ca4e4aab48a206bb3e9245 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-10soc/intel/cannonlake/acpi/serialio.asl: Don't advertise unavailable devicesPatrick Rudolph
On PCH-H the I2C4 0:19.0 device isn't usable and thus 0:19.1 and 0:19.2 can't be detected using standard PCI probing. Remove I2C4, I2C5 and UART2 from generic ASL code on PCH-H platforms that advertise its PCI conformance by the _ADR attribute. Change-Id: I89f9ab7d4afb2e7d1b1e24d072adf99e0da6fecf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-09soc/intel/{icl.tgl,jsl}: Remove SMRAM register programmingAamir Bohra
SA SMRAMC register PCI offset 0x88 is deprecated for ICL, JSL and TGL. Removing the register programming for these platforms. The write to this register does not take effect and remains configured to 0, even when programmed. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-08vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt socJonathan Zhang
Intel CPX-SP ww32 release has a number of bug fixes: a. It fixed the issue related to some PCIe ports being hidden. This affected DeltaLake config A, made the onboard PCIe NIC device not working. ww32 release added two UPD parameters: PEXPHIDE, HidePEXPMenu. b. It fixed the regression related to MRC cache. c. It fixed the issue related to VT-d support, and added X2apic UPD paramter. A separate PR will be submitted to enable VT-d in coreboot. d. It fixed the issue related to enabling thermal device with PCI or ACPI mode. [CB:44075] was submitted to enable it in coreboot. e. It fixed the issue of FSP log level change UPD parameter DebugPrintLevel not working. There is a change in IIO UDS Hob. TESTED=booted YV3 config A, and rebooted it. Access the target OS remotely. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iaffcb9d635f185f9dd6d6fbe4457549984a993a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-08soc/intel/skylake: Enable CIO depending on devicetree configurationFelix Singer
Currently, CIO gets enabled by the option Cio2Enable, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the CIO controller. All corresponding mainboards were checked if the devicetree configuration matches the Cio2Enable setting, and missing entries were added. Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44032 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-08soc/intel/skylake: Enable SA IMGU depending on devicetree configurationFelix Singer
Currently, SA IMGU gets enabled by the option SaImguEnable, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the SA IMGU controller. All corresponding mainboards were checked if the devicetree configuration matches the SaImguEnable setting, and missing entries were added. Change-Id: I293a20a321c75f82a57cbd5339656d93509b7aa6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-08soc/intel/skylake: Add IMGU definitions to pci_devs.hFelix Singer
Change-Id: Iee7393ae7e2aca94151c242894c64ac902f4d437 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-08soc/intel/skylake: Enable SDXC depending on devicetree configurationFelix Singer
Currently, SDXC gets enabled by the option ScsSdCardEnabled, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the SDXC controller. All corresponding mainboards were checked if the devicetree configuration matches the ScsSdCardEnabled setting, and missing entries were added. Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-08soc/mediatek/mt8192: Add initial config for new ARMv8 device MT8192CK Hu
Add MT8192 address map, memlayout and first Kconfig. MT8192 is similar to MT8183. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: I4e34c03a11a77ed98674ffd8eeddb20ef5fea89d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43957 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-07soc/intel/skylake: Enable thermal subsystem depending on devicetreeFelix Singer
Currently SA thermal subsystem gets enabled by the option Device4Enable, but this duplicates the devicetree on/off options. Therefore depend on the devicetree for enablement of the SA thermal subsystem controller. All corresponding mainboards were checked if the devicetree configuration matches the Device4Enable setting, and missing entries were added. Change-Id: I7553716d52743c3e8d82891b2de14c52c6d8ef16 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44026 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-07soc/intel/skylake: Add SA thermal subsystem definitions to pci_devs.hFelix Singer
Change-Id: Ic83cfbe2a715db317d94c2b9c6cdd8c58a43612f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-07soc/intel/cnl: Set Heci1Disable depending on devicetree configFelix Singer
Currently HECI1 gets enabled by the option HeciEnabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement/disablement of the HECI1 device. All corresponding mainboards were checked if the devicetree matches the HeciEnabled setting, and adjusted where necessary. Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-07soc/amd/picasso/acpi: remove AOAC device enables from global NVSFelix Held
These values in GNVS are written, but never read/used. aoac.asl contains proper ACPI power management functions for the AOAC devices that directly access the state from the device's registers instead of relying on cached values in GNVS, so the corresponding GNVS entries can be dropped. BUG=b:161165393 TEST=Mandolin still boots and dmesg shows no new ACPI errors. Change-Id: Iee78df215308bd9b656228be787fac121d10ca99 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44245 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-07xeon_sp/cpx: Enable HWP Intel Speed ShiftJohnny Lin
Set HWP base feature, enable EPP, lock thermal interrupt and lock MSR Tested=On OCP Delta Lake, rdmsr 0x1aa shows 403040 Change-Id: I6d23de4032562095db1aaf96ddfd2b70a4517faa Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44171 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-07soc/intel/broadwell/iobp: Log success in `pch_iobp_write()`Angel Pons
This reduces the differences between Lynxpoint and Broadwell. Change-Id: I759aa98b80c70c5024213bd8795375061bdbbf10 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42622 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-07soc/intel/common: Log CSE FW Status Registers before triggering recoverySridhar Siricilla
The patch logs CSE Firmware Status Registers(FWSTS1, FWSTS2 & FWSTS3) before triggering recovery to help debugging. BUG=b:159962240 Test=Verified on hatch Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I90e9f5897408bfc37a69cf0bb23bff18a146b9e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43537 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-07soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASESubrata Banik
In 'bootblock/pch.c', clear PCI_COMMAND_MASTER (BIT 2) prior to programming PWRMBASE and enable BIT 2 after programming PWRMBASE along with PCI_COMMAND_MEMORY (BIT 1). Also perform below operations 1. Use pci_and_config16 instead of pci read and write 2. Use setbits32 instead of mmio read and write Change-Id: I7a148c718d7d2b618ad6e33d6cec11bd0bce0937 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-07src/soc/intel/icelake: Allow option to use USE_INTEL_FSP_MP_INITSubrata Banik
This patch removes the unnecessary enforcement of MP PPI in ICL in order to have parity with other IA-SoC. Now it allows user to select USE_INTEL_FSP_MP_INIT if required. TEST=Able to build and boot ICL platform with either USE_INTEL_FSP_MP_INIT or USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI selected. Change-Id: I25288a24cdf9dceec45a90e4e7233225a6cab508 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-06soc/intel/tigerlake: add common routine for DDR initNick Vaccaro
Add a common routine meminit_ddr() that calls the appropriate meminit routine based on whether the memory type requested is LPDDR4x or DDR4. BUG=b:161772961 TEST='emerge-volteer coreboot chromeos-bootimage' and verify that volteer still boots. NOTE that this only tests the lpddr4 side of the implementation. I do not have a DDR4 board to test this on. Change-Id: Ib2039eb89211efc48d10897eb679d05f567ae5a1 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-08-06soc/intel/common/block/cpu: Refactor init_cpus functionSubrata Banik
This patch makes init_cpus function external so that it can be used in below scenarios: 1. When coreboot is doing MP initialization as part of BS_DEV_INIT_CHIPS (exclude this call if user has selected USE_INTEL_FSP_MP_INIT) 2. coreboot would like to take APs control back after FSP-S has done with MP initialization based on user select USE_INTEL_FSP_MP_INIT Also make sure post_cpus_init function is getting executed unconditionally to update MTRR snapshot on all cores. Change-Id: Idc03090360f34df074b33ba0fced2d192edf068a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-06soc/mediatek/mt8183: Set MMU default map length to 8GB befor mem initHuayang Duan
BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I072745933fe141cac26afd044836a564e345d036 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43795 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-06soc/mediatek/mt8183: Add ddr geometry to support 6GB, 8GB DDR bootupHuayang Duan
Currently the DRAM initialization code can only work on 4GB size and want to support larger memory sizes in future, so add geometry information to the DRAM calibration parameters. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I1fdf50b75c6a552c0a889f21e1a81ab4b9a305fa Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-06soc/mediatek/mt8183: Adjust tRFCab and tRFCpb by the density valueHuayang Duan
Different density should correspond to different tRFCab and tRFCpb timing. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I2599fcd620cdefe2e12480932ffd75e0416b9545 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-06soc/mediatek/mt8183: Add missing register settings for channelsHuayang Duan
Some DRAM control settings need to apply to all channels, so add those missing settings. Also fix a typo (0x1 < 0) to (0x1 << 0). BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I35e25c922ed45216d5f04835abcd10809a8d559a Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-05{sb,soc}/intel/*/acpi/lpc.asl: Drop commented-out codeAngel Pons
This code has been commented out for a long time. Drop it. Change-Id: Iddc635dc5bbc7a8b42e97f4e2f6d579a839d874b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43264 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-05{nb,soc}/intel: Use get_current_microcode_rev() for ucode versionSubrata Banik
This patch removes all redundant read microcode version implementation from SoC directory and refer from cpu/intel/microcode/microcode.c file. TEST=Able to get correct microcode version. Change-Id: Icb905b18d85f1c5b68fac6905f3c65e95bffa2da Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44175 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-05mb/google/zork: keep the c-state IO base address alignmentChris Wang
Align the C-state MSR value of BSP with AGESA. BUG=b:162705221 BRANCH=none TEST=Check the MSR value is correct and BSP can enter CC6 with AVT tool Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ib98d34af518439d338326446c20601867ad31690 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-05src: Use space after 'if', 'for'Elyes HAOUAS
Change-Id: I5d3a5ede47aefc7cc2ee330f8a0bcded16138764 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44173 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-05src/soc/intel/common: Make top_of_ram till TOLUD region mmio_resourceSubrata Banik
Ideally don't need to mark the entire top_of_ram till TOLUD range (used for stolen memory like GFX and ME, PTT, DPR, PRMRR, TSEG etc) as cacheable for OS usage as coreboot already done with mpinit w/ smm relocation early. TEST=Able to build and boot ICL, TGL RVP. Without this CL : PCI: 00:00.0 resource base 77000000 size 4800000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index a With this CL : PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index 9 No changes observed with MTRRs snapshot. Change-Id: I64c14b14caf0a53219fdc02ec6bbd375955a0c8e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-05soc/intel/common: Include Alder Lake device IDsSubrata Banik
Add Alder Lake specific CPU, System Agent, PCH (Alder Point aka ADP), IGD device IDs. Document Number: 619501, 619362 Change-Id: I17ce56a220e4dce2db2e0e69561b3d6dac9e65a2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-04soc/intel/skylake: Add RMRRs after all DRHDsAngel Pons
The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says: BIOS implementations must report these remapping structure types in numerical order. i.e., All remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. So, update the corresponding code to adhere to the specification. Change-Id: I2446d536603559f637f3f8b1b44e9d712aa35492 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-04soc/intel/broadwell: Add RMRRs after all DRHDsAngel Pons
The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says: BIOS implementations must report these remapping structure types in numerical order. i.e., All remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. So, update the corresponding code to adhere to the specification. Change-Id: Ib5ef5e006e590d72bec52e057e9b72150e0e636f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-04soc/intel/apollolake/acpi.c: Add RMRRs after all DRHDsAngel Pons
The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says: BIOS implementations must report these remapping structure types in numerical order. i.e., All remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. So, update the corresponding code to adhere to the specification. Change-Id: I4ee3ae6c45e2a2c921fbccbb62b853e4a141a58d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-04soc/amd/picasso/acpi: clean up global NVSFelix Held
Some fields in GNVS seem to be copied over from Apollolake to Stoneyridge to Picasso. This patch removes the unused fields. BUG=b:161165393 TEST=Mandolin still boots and dmesg shows no new ACPI errors. Change-Id: I8c6b580543089bf0180a7caeb9e6a47dc4ed4a1d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-08-04soc/intel/baytrail: Factor out `acpi_fill_madt()`Angel Pons
It is the same for the two Bay Trail boards in the tree. Change-Id: I5110cfa8807406232e4f7f1fe79dfe9c3ae4dac4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
2020-08-03soc/amd/picasso: set is_rv to 1 for RV familyAkshu Agrawal
RV has difference in clk framework. In RV we get a 48Mhz fixed clk, while in ST we had 25Mhz, 48mhz clocks and a Mux to select between them. To differentiate set the fmw property to 1 for boards using RV family of SoC. Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> BUG=b:158906189 TEST=rt5682 driver get the correct clk and tested audio playback Change-Id: I685ded1607c2c7edc5e48f0bada258ebde192bb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-03soc/intel/baytrail: Add MRC SMBus workaroundMate Kukri
- The Bay Trail MRC fails to read the SPDs from SMBus. - Instead the SPDs are read into a buffer and the buffer is passed to the MRC. Change-Id: I7f560d950cb4e4d118f3ee17e6e19e14cd0cc193 Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44092 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03soc/intel/xeon_sp/cpx: configure STACK_SIZEJonathan Zhang
Before this change, we have this problem (boot log from DeltaLake config A server): Jumping to boot code at 0x00040000(0x755f6000) Stack overrun on CPU0 (address 0x7574a000 overwritten). Increase stack from current 4096 bytes ERROR: BUG ENCOUNTERED at file 'src/lib/stack.c', line 43 Linux version 4.16.18 Configure STACK_SIZE to make it larger to fix above problem. Now, we have this boot log: BS: BS_PAYLOAD_LOAD exit times (exec / console): 326 / 21727 ms Jumping to boot code at 0x00040000(0x752f2000) CPU0: stack: 0x75746000 - 0x7574a000, lowest used address 0x7574681c, stack used: 14308 bytes Linux version 4.16.18 TESTED=booted YV3 config A to target OS. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ia04a3ee0cd37177ecab65469855a1cf920742458 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2Jonathan Zhang
CPX-SP FSP is FSP 2.2, so select PLATFORM_USES_FSP2_2. SKX-SP continues to select PLATFORM_USES_FSP2_0, as SKX-SP FSP is FSP 2.0. Correct DCACHE_RAM_BASE. Increase FSP_TEMP_RAM_SIZE, DCACHE_BSP_STACK_SIZE, and adjust DCACHE_RAM_SIZE accordingly. Thus the workaround of hardcoding StackBase and StackSize FSP-M UPD parameters is removed. Add CPX-SP soc implementation of soc_fsp_multi_phase_init_is_enable() to indicate that FSP-S multi phase init is not enabled, since it is not supported by CPX-SP FSP. TESTED=booted YV3 config A to target OS. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I25e39083df1ebfe78871561b0a0e230b66524ea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44049 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03src/soc/intel/jasperlake: Update SD card ACPI deviceAamir Bohra
1. Add _DSM method 2. Add support to turn on/off the power enable signal in _PS0/_PS3 methods. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I4f944caa535bdc946eef1e0f518fe3ee344187b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-08-03Change all assert(0) to BUG()Julius Werner
I would like to make assertions evaluate at compile time where possible, but sometimes people used a literal assert(0) to force an assertion in a certain code path. We already have BUG() for that so let's just replace those instances with that. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I674e5f8ec7f5fe8b92b1c7c95d9f9202d422ce32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03qualcomm/sc7180: Fix TLMM assignments for GPIOs 29, 31 and 32Julius Werner
According to my SC7180 reference manual, these three GPIOs are in the NORTH TLMM, but our pin table lists them as SOUTH. That means all accesses our code has been doing to them have just been hitting empty address space. BUG=b:160115694 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If9c03ac890a7975855394c2e08b8433472df204d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-08-03soc/intel/tigerlake: Invoke PCIe root port swappingCaveh Jalali
PCIe bus:function specifiers need to be coalesced the same way functions are coalesced during bus enumeration. Invoke PCIe root port devicetree update to swap the enabled root port devices with the disabled devices. At this point, the TGL pci_devs.h only describes the PCH-LP, so only the PCH-LP root ports are listed in this patch. We'll need to add additional PCIe root ports when PCH-H support is added. BUG=b:162106164 TEST=Ensure that the PCIe device 1c.7 corresponding to Root port 8 is swapped with the PCIe device 1c.0 corresponding to Root port 1. Change-Id: I9230de8b1818f3f2115dab923841fd0e7778be62 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-02soc/intel/baytrail/northcluster.c: Clean up commentsAngel Pons
Giant commit aee7ab2 (soc/intel/braswell: Clean up) reformatted comments to follow the coding style, among many other things. This commit updates some comments on Bay Trail with two objectives: follow the coding style, and reduce the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Ibe942a20c624e2c74801c8816616ec83851949af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-08-02soc/intel/baytrail/sata.c: Fix SATA init sequenceAngel Pons
SeaBIOS on Bay Trail would time out when trying to access a SATA drive. Turns out that there's two mistakes in the SATA initialization sequence: - PCI register 0x94 is wrongly cleared with a bitwise-and operation. - PCI register 0x9c is instead written to 0x98, clobbering the latter. After correcting them, SeaBIOS can boot from SATA on Asrock Q1900M. Change-Id: I5cc4b9b1695653066f47de67afc79f08f0341cc5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44088 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Máté Kukri <kukri.mate@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-02soc/intel/baytrail: Add native refcode replacementMate Kukri
- This is a reverse engineered re-implementation of refcode.elf on Bay Trail - Tested on GBYT4, should work everywhere as it's meant to behave exactly the same as the binary refcode Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Change-Id: I91977c509022b0078804dc151d27296260e24bc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43133 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-02soc/intel/baytrail/northcluster.c: Rename variableAngel Pons
Tested with BUILD_TIMELESS=1, Google Ninja does not change. Change-Id: I7e74f342c0545f8d2a2128de4162581e5dc01e17 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-02soc/intel/baytrail/northcluster.c: Tidy up long linesAngel Pons
These now fit in 96 characters. Tested with BUILD_TIMELESS=1, Google Ninja does not change. Change-Id: I7e1dc0126fa4d64f75e686d68c4f70f7109c6da0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-02soc/intel/braswell/northcluster.c: Tidy up long linesAngel Pons
These now fit in 96 characters. Tested with BUILD_TIMELESS=1, Facebook fbg1701 remains identical. Change-Id: I4275c81d22c03c461c184f26367db80b828033a9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-02soc/intel/braswell/northcluster.c: Rename macroAngel Pons
Spell `KiB` with lowercase `i`. Tested with BUILD_TIMELESS=1, Facebook fbg1701 remains identical. Change-Id: Ief606686ee3866a7ede75d097feb510418621fe8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-01soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecatedSubrata Banik
FSP default UPD for SkipMpInit is set to 0 which refers to run CPU feature programming on all cores (BSP + APs). Setting SkipMpInit=1 is not recommended as it will only limit CPU feature programming on BSP. TEST=Able to perform CPU feature programming by FSP on all cores using external MP PPI services. Change-Id: I22e70f5f15e53c5fabd78cc3698c4d718b607af6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-07-31soc/intel/cannonlake: Fix DMAR when no iGPU is presentPatrick Rudolph
Don't emit RMRR for the iGPU if it's not present. This is done on other platforms as well. Fixes an DMAR error seen in dmesg on platforms without iGPU. Change-Id: Iafe86e6938a120b707aaae935cb8168f790bb22f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43994 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZEJonathan Zhang
CPX-SP processor has 2 IMC, there are 3 channels per IMC, 2 DIMMs per channel. It supports DDR4. Configure default values for DIMM_MAX and DIMM_SPD_SIZE accordingly. Change-Id: I66cc512465362d5ba04dc36534360c94ca23e77a Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43982 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30smbios: Fix type 17 for Windows 10Patrick Rudolph
The `GetPhysicallyInstalledSystemMemory` API call, at least on Windows 10, returns an error if SMBIOS tables are invalid. Various tools use this API call and don't operate correctly if this fails. For example, the "Intel Processor Diagnostic Tool" program is affected. Windows then guesses the physical memory size by accumulating entries from the firmware-provided memory map, which results in a total memory size that is slightly lower than the actual installed memory capacity. To fix this issue, add the handle to a type 16 entry to all type 17 entries. Add new fields to struct memory_info and fill them in Intel common code. Use the introduced variables to fill type 16 in smbios.c and provide a handle to type 17 entries. Besides keeping the current behaviour on intel/soc/common platforms, the type 16 table is also emitted on platforms that don't explicitly fill it, by using the existing fields of struct memory_info. Tested on Windows 10: The GetPhysicallyInstalledSystemMemory API call doesn't return an error anymore and the installed memory is now being reported as 8192 MiB. Change-Id: Idc3a363cbc3d0654dafd4176c4f4af9005210f42 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-30mb/amd,google/mandolin,zork: Set EFS SPI platform configMatt Papageorge
Set platform defaults for SPI settings in Kconfig for EFS. BUG=b:158755102 TEST=Build and boot test on Tremblye and Morphius. Verify values in output image in a hex editor. Measure 1st x86 timestamp, perf improves by over a second. Change-Id: I765dada14700f4800263d2d3844af07fad0e5b71 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43303 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30amd/common/block/spi: Add EFS SPI configurations to KconfigMatt Papageorge
The Embedded Firmware Structure should contain SPI speed, mode and Micron support for the PSP to program. Add Kconfig options to specify these values to use for future platform changes. BUG=b:158755102 TEST=Test menuconfig and platform build for Trembyle and Mandolin. Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Change-Id: I78558fa3fa27c70820f0f3d636544127adab6f8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42567 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30soc/amd/picasso: Split ops for internal and external PCIe GPP bridgesFurquan Shaikh
This change splits the device operations for internal and external PCIe GPP bridges so that the external bridges use `pciexp_scan_bridge()` instead of `pci_scan_bridge()`. `pciexp_scan_bridge()` is required for external GPP bridges to enable ASPM on downstream devices if supported. BUG=b:162352484 TEST=Verified on Trembyle: $ lspci -s 1:00.0 -vvv | grep ASPM LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <4us, L1 <64u ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ice2aa3e4758adccf7b0b89d4222fc65a40761153 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-29soc/intel/tigerlake: Configure TCSS D3Hot and D3ColdJohn Zhao
Update configuration for both of TCSS D3Hot and D3Cold. It is expected D3Hot is enabled for all platforms. Because there are known limitations for D3Cold enabling on pre-QS platform, this change reads cpu id and disables D3Cold for pre-QS platform. For QS platform, D3Cold is configured to be enabled. BUG=None TEST=Verified D3Hot is enabled, D3Cold is disabled for pre-QS (cpu:806c0) and enabled for QS (cpu:0x806c1). Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I534ddfefcd182f5b35aa5e8b461f0920d375a66d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43980 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 04:45:01 +0000