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2017-07-13soc/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: I3c5f9e0d3d1efdd83442ce724043729c8648ea64 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-13soc/intel/cannonlake: Add reset.cAndrey Petrov
Add reset functionality. This implementation relies on CSE to trigger global reset. Change-Id: I7e6ae07a48f1cdc3d2f4cdb74246627d27253adf Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13soc/intel/cannonlake: Add MakefileAndrey Petrov
This enables building working bootblock and non-functional romstage and ramstage. Change-Id: I580cd2c3279d742f202b2adfbe55c814cfb48f99 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13soc/intel/cannonlake: Add bootblock PCHAndrey Petrov
Add essential initialization needed for PCH in bootblock. Change-Id: I3694e099e78c2989f7192c550cbba098e5df2032 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13soc/intel/cannonlake: Add early CPU initializationAndrey Petrov
Add basic CPU initialization for bootblock, as well as relevant headers. Change-Id: I318b7ea0f3aa5b5d28bf70784ccd20f2fe28cd86 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13soc/intel/skylake: reduce postcar stack usage for fsp 2.0Aaron Durbin
The FSP 2.0 path uses postcar to decompress ramstage. Since postcar is entirely RAM based there's no need to have an excessively large stack for the lzma decompression buffer. Therefore, reduce the stack required to 1 KiB like apollolake. Change-Id: I45e5c283f8ae87e701c94d6a123463dddde3f221 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-12soc/intel/cannonlake: Add PCI dev macros and IDsAndrey Petrov
Change-Id: I287404f1615c6c0b441dd1b98a40e79919920a02 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-12soc/intel/cannonlake: Add report_platform.cAndrey Petrov
Dump basic platform information early in bootblock. Change-Id: I12d1c9dd9f0518c133de465a4db72a0664a94eef Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20068 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-12soc/amd/stoneyridge: Update header guards and includesMarshall Dawson
Rename the guard to better match the new directory structure. Add include files containing typedefs used in the file. Change-Id: I5fe23ce6994603b0ace99fd6ffc5f3eded2880af Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20525 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-12soc/intel/skylake: Remove “disable SaGv” in recovery mode flowSubrata Banik
This reverts commit 5535cead (intel/skylake: Disable SaGv in recovery mode). Commit 5535cead disables SaGv in recovery mode to save few seconds booting time as we were doing memory training on every recovery flow. Now we don't need to perform MRC training on every recovery boot due to RECOVERY_MRC_CACHE implementation in place. Hence we don't need to define different SaGv policy between Normal (developer) mode and recovery mode to save few seconds. Using different SaGv parameters between recovery and all other mode has some significent drawbacks over warm reboot cycle. We are seeing a MRC traning hang in eve/soraka/poppy devices with below use case. Step 1: Boot system in developer mode (first time RW_MRC training) Step 2: Set recovery_request=1 (using crossystem) and issue “reboot” from OS Step 3: System will perform recovery mode MRC training and boot to OS (first time RECOVERY_MRC training) Step 4: Issue “reboot” from OS console. Step 5: System wil boot in developer mode (using RW_MRC cache) Step 6: Set recovery_request=1 (using crossystem) and issue “reboot” from OS Step 7: System will pick RECOVERY_MRC_CACHE and will hang during MRC training. This patch fixes issue mentioned above and ensures system boot to OS without any hang if we change mode (dev<->recovery) over warm reset. BUG=b:63515071 BRANCH=none TEST=manual stress testing of dev<->recovery mode over warm boot. No MRC hang with this fix on eve/soraka/poppy devices. Change-Id: I8d094a8b6d78ea3bf8f929870a4a179495c29c78 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-12Revert "soc/intel/skylake: storage: Add 2ms delay before exiting D3"Subrata Banik
Don't need this additional 2ms delay as PCR read after sideband write help to fix original hard hang issue. This reverts commit d4b6ac19b0a6619ebe645875282643cc50cf7a3e. Change-Id: I4232cba5b92e17f728795f7c282af6161e385e9b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-12soc/intel/skylake: Perform PCR read after all PCR writeSubrata Banik
BIOS must ensure to read same PCR offset after PCR write operation is done. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<->D3 transition on eve failing unit. No hard hang with this fix. Change-Id: Id3d567aab517b16ff99a526fc29c2d71bf4042d0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-11soc/intel/skylake: Fix PMC address range setup for PCH-HNico Huber
The PMC of PCH-H requires a different destination id. TEST=Run on kontron/bsl6 and observed that PM registers are correctly dumped at start of romstage. Change-Id: I862e4df986f1cdea34f8fa45d016fb6b51f29122 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-11soc/intel/skylake: Set generic I/O decode ranges earlyNico Huber
Move the generic I/O decode range setup before the console init. TEST=Run on kontron/bsl6 which requires 0xa80/0xa81 decoded to initialize serial ports. Serial console works from boot- block on. Change-Id: I9829f188c80eb73f6cd91b0c22e1c07da5745ad6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-11binaryPI: Define AGESA blob in CBFS as Kconfig stringKyösti Mälkki
Change-Id: I0f78cb275ecad732f81c609564a0640f03d2559e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-07-10sgx: Move SGX code to intel/common/blockPratik Prajapati
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX controls building. The SGX feature is still enabled from devicetree.cb. As of now this SGX init supports only KBL (SKL not tested). Support of SGX for new SOCs would be added incrementally in this common code base. Change-Id: I0fbba364b7342e686a2287ea1a910ef9a4eed595 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/20173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-08soc/amd/stoneyridge/northbridge.c: remove unnecessary null checkMartin Kepplinger
Checking for NULL here doesn't help here. We *rely* on cdb_dev to exist directly before this check. Coverity had found this: *** CID 1376664: Null pointer dereferences (REVERSE_INULL) /src/soc/amd/stoneyridge/northbridge.c: 666 in cpu_bus_scan() 660 * this silicon. It is an SOC and can't have >= 16 APICs, but 661 * we will start numbering at 0x10. We also know there is only 662 * on physical node (module in AMD speak). 663 */ 664 665 lapicid_start = 0x10; /* Get this from devicetree? see comment above. */ CID 1376664: Null pointer dereferences (REVERSE_INULL) Null-checking "cdb_dev" suggests that it may be null, but it has already been dereferenced on all paths leading to the check. 666 enable_node = cdb_dev && cdb_dev->enabled; 667 cpu_bus = dev->link_list; 668 669 for (j = 0; j <= siblings; j++ ) { 670 apic_id = lapicid_start + j; 671 printk(BIOS_SPEW, "lapicid_start 0x%x, node 0x%x, core 0x%x, apicid=0x%x\n", Change-Id: Ic6a53df8b8d1596ad0eb1d8f0fa200cccf9509cf Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/20415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-03soc/intel/quark: Add I2C debuggingLee Leahy
Add I2C debugging support: * Add I2C_DEBUG Kconfig value to enable debugging * Display I2C segments before the transfer * Display errors that occur during the transfer * Display the number of bytes transferred for successful transfers TEST=Build and run on Galileo Gen2 Change-Id: Ia17be8b4213b13fd6c6a367d081414d0f21fbb0f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-07-03soc/intel/apollolake: Use common gpio for apollolakeHannah Williams
No regression observed on a APL platform Change-Id: I0fcc22df5eaec014f3b89755415f051b05aa554a Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/19949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-02soc/intel/quark/spi.c: Explain a read in order to flush buffersMartin Kepplinger
In order for this (seemingly unnecessary) status assignment to stay, let's explain it in a comment. Change-Id: I0a364539c37005cfd637b75c8cc23b84e274294d Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/20411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-02soc/intel/cannonlake: Add bootblock.cAndrey Petrov
Change-Id: Ia951a466479b1e98e49895705162a66aece7609b Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-02intel/block/cse: Add Cannon Lake SoC PCI device IDAndrey Petrov
Change-Id: Ida822d704b04cc4d1dfffb58003fc308bcb502d0 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-07-02soc/amd/common: Add initial support for AMD PSPMarshall Dawson
Add files for supporting the BIOS->PSP communication not covered by AGESA. The first command implemented notifies the PSP that DRAM is ready. This patch also introduces the amd/common/block directory structure similar to intel/common/block. Change-Id: I34b2744b071aa3dfb1071b2aabde32ddb662ab87 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-01soc/intel/skylake: Remove unnecessary P-State and Flex Ratio assignmentBarnali Sarkar
This patch basically does two things - 1) Remove unnecessary setting of flex_ratio to TDP nominal: Factory configured (default) Max Non-TURBO ratio(P1) is already cofigured in MSR_PLATFORM_INFO(0xCE). If this Maximum Non-TURBO Ratio(P1) needs to be modified, it should be done using MSR_FLEX_RATIO (0x194). Here, in this code, the FLEX_RATIO is being modified by the TDP Nominal Ratio, reading the MSR_CONFIG_TDP_NOMINAL(0x648). But this value is actually less than the factory configured Maximum Non TURBO Ratio (P1). So, this code is actually not required. Also, the Bit 12 in PCH Soft Strap Register is already set in descriptor. This Bit implies Processor Boot Max Frequency - 0 = Disable Boot Max Frequency 1 = Enable Boot Max Frequency (Default) This setting determines if the processor will operate at maximum frequency at power-on and boot. Thus this patch will avoid one extra platform warm reset now onwards. 2) Remove wrongly setting Max Frequency in Bootblock phase: In the function set_max_frequency(), the P-State max ratio was set to TDP Nominal ratio if C-TDP was enabled, else it was set to Max Non Trbo ratio. But, when the cpu gets reset, it will operate with the Max-Non Turbo ratio only, which is greater than the TDP Nominal ratio. So, no need to set back the ratio to TDP Nominal which is lower than the currently operating frequency. BUG=none BRANCH=none TEST=Build and boot poppy Change-Id: I24bfc86ddf0f038d85da938e41e950382fe2a6c3 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-29soc/intel/skylake/Kconfig: Drop useless FSP1.1/2.0 promptsNico Huber
There is no choice, if not leaving it with the default the build will fail. Change-Id: Id91e3ce87f8ced3001fcd2125f8f6781b270f5bc Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-29soc/intel/cannonlake: Add UART initializationAndrey Petrov
Cannonlake has built-in UART driver as part of LPSS block. However port mapped decoders are in use as well. Change-Id: I9f209bf29c1748c5beea31bc6b31cb07a1e14195 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-29arch/x86: update assembly to ensure 16-byte alignment into CAaron Durbin
When the C compiler expects 16-byte alignment of the stack it is at the call instruction. Correct existing call points from assembly to ensure the stacks are aligned to 16 bytes at the call instruction. Change-Id: Icadd7a1f9284e92aecd99c30cb2acb307823682c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-29soc/intel/common/block/gpio: Port gpio code from Apollolake to commonHannah Williams
Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/19759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-29soc/intel/cannonlake: Add initial dummy directoryLijian Zhao
Add Cannon Lake SoC boilerplate directory with: * SoC directory * Base Kconfig * Dummy cbmem.c Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-29soc/amd/stoneyridge: Convert monotonic timerMarshall Dawson
Use the TSC for the Stoney Ridge monotonic timer. Modern AMD CPUs have invariant timestamp counters. This patch brings the feature more in line with other devices and allows the use of typical monotonic timer functions. BUG=chrome-os-partner:62578062 Change-Id: I07b05fbc7cdea54a45daac01954284a9fd67e42f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-28soc/amd/stoneyridge: Revise pci_devs.h fileMarshall Dawson
Now that pci_devs.h is part of soc/ and not used for multiple southbridges: * Remove devices not present in the Stoney Ridge APU * Complete the list to include additional devices besides those in the FCH. BUG=chrome-os-partner:62578372 Change-Id: I1cd2d5e41473f362bbfd28ee93788a292bc33991 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20370 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28soc/amd/stoneyridge: Fix device IDsMarshall Dawson
Update pci_devs.h to the correct IDs for Stoney Ridge. BUG=chrome-os-partner:62578372 Change-Id: Ic1a7fe8d95c34b80e21cc089168732372d9690a3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20200 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-28soc/amd/stoneyridge: Enable early cbmemMarshall Dawson
Add a memmap file with a cbmem_top() function. Remove the LATE_CBMEM_INIT, allowing the default of EARLY. Remove calls to the late-only set_top_of_ram() function. Change-Id: I11ad7190031c912642a7312f2fc6f792866288b7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27soc/amd/stoneyridge: Add tseg size to KconfigMarshall Dawson
Add a SMM_TSEG_SIZE symbol that can be used in top of memory calculations. Change-Id: I26f3b06f85f0cf5613656c1d5df55bd9ea4bbbbc Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19750 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-27soc/stoneyridge: Remove IDE controllerMarshall Dawson
Remove IDE from the Stoney Ridge source. This APU doesn't have an IDE controller. The support was left over from pi/hudson. BUG=chrome-os-partner:62580062 Change-Id: I7316c113a7464089ccfbea6b6cf69787940b9e97 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27soc/stoneyridge: Remove FCH PCIe supportMarshall Dawson
Remove the pcie.c file. Historically PCIe lanes have been available from the Gfx and/or the FCH. The integrated FCH in this APU has no PCIe available. BUG=chrome-os-partner:62580062 Change-Id: Ie89383dadfaa57c5a6d185e74551ae50ac8d9778 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-27soc/amd/stoneyridge: Remove PCIe-PCI bridgeMarshall Dawson
The Stoney Ridge does not contain this bridge like some of the older Hudson FCHs. Remove this support from the source. This moves the Stoney Ridge IRQ setup to the southbridge file, hudson.c. BUG=chrome-os-partner:62580062 Change-Id: I8f974ba76b8c20f4335dd8872eaf4b8172188ee2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27soc/amd/common: Fix most checkpatch errorsMarshall Dawson
Correct the majority of reported errors and mark most of the remaining ones as todo. Some of the lines requiring a >80 break are indented too much currently. Changes to agesawrapper.c cause the build to change, so this file is also left as-is. Make hex values consistently lower-case. BUG=chrome-os-partner:622407746 Change-Id: I0464f0cafac4ee67edc95d377dcf7aab9a90c66b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27soc/amd/stoneyridge: Fix most checkpatch errorsMarshall Dawson
Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27soc/amd/stoneyridge/acpi: Fix checkpatch errorsMarshall Dawson
Correct the checkpatch errors reported in the asl files and make other stylistic modifications. These changes were confirmed to cause no changes in a Gardenia build. BUG=chrome-os-partner:622407746 Change-Id: Id8b2620d161062c444e493325d83bb158705b76b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-27vendorcode/amd: Unify Porting.h across all targetsStefan Reinauer
This requires to also unify the calling convention for AGESA functions from AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr) to AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr) On systems running 32bit x86 code this will not make a difference as UINTN is uintptr_t which is 32bit on these machines. Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-27soc/intel/common/opregion: Use enum cb_err as return valuePatrick Rudolph
Return CB_SUCCESS and CB_ERR instead of some integer. Preparation to merge intel/soc and intel/nb opregion implementations. Change-Id: Ib99fcfe347b98736979fc82ab3de48bfc6fc7dcd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27soc/intel/quark: We're not Broadwell anymoreStefan Reinauer
... even though the author of the code probably wished he was working on a (much faster) broadwell system instead. Let's fix the header guard to reflect the right SOC. Noteworthy: clang detected that this was wrong. Change-Id: I74c217c0471800f40c31a9ac38ba5396f82cd724 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27soc/intel/skylake: storage: Use word access for power state registersDuncan Laurie
In the D0 and D3 ACPI methods use word access to the PME status and control register. This brings the code inline with the Intel reference code and matches how the kernel handles access to this register. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<>D3 transition across multiple devices Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-27soc/intel/skylake: storage: Add 2ms delay before exiting D3Duncan Laurie
For the skylake/kabylake generation of PCH there is an ACPI workaround for emmc/sd power state that involves disabling and re-enabling dynamic clock gating after enabling power to the controller, before setting the power state to D0. Under certain conditions we have observed that the controller is not powered and ready by the time the kernel attempts to read the PME control and status register and so the system will hang while attempting to read PCI config register 0x84. To ensure that the controller is ready add a 2ms delay after re-enabling dynamic clock gating and before setting the power state to D0. This issue has been observed on eMMC, but the same workaround exists for the SD card interface so the same delay is added there. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<>D3 transition across many devices shows no hard hang after 2 days. Change-Id: If0f0323cf5437c54c907c332937b5de9dda2d8f6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-26soc/intel/fsp_baytrail/include/soc/pci_devs.h: Add brackets around macroElyes HAOUAS
Code checked manually Change-Id: I91ababb3bf7aa1ab0f71bb005c4685e81bb4d92f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc/amd/stoneyridge: Add northbridge supportMarc Jones
Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc/amd/stoneyridge: Add CPU filesMarc Jones
Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. This is the second patch in the process of converting Stoney Ridge to soc/. Changes: - update Kconfig and Makefiles - update vendorcode/amd for new soc/ path Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc: Add AMD Stoney Ridge southbridge codeMarc Jones
Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26rockchip/rk3399: update the ddr 200MHz frequency configurationCaesar Wang
This patch updates the coreboot DDR Settings to match the configuration used by ARM-Trusted-Firmware. Change-Id: I34bc2950a9708ac89a5637bf682551e03d993fcc Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://review.coreboot.org/20304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-06-23soc/intel/skylake: Remove post SMM Relocation uCode loadingBarnali Sarkar
As per latest BWG, ucode reloading should be done at the end of Mp Init, i.e., after PRMRR and other features are enabled. No reloading specifically after SMM Relocation is required. As, in the Common CPU MP Init code, we are already doing a uCode load at the end of MP Init Feature Programming, hence, the uCode loading after SMM relocation can be removed. Change-Id: Ib1957c5fe5a8c83bb20b978a9841670b0c3e8846 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-23soc/intel/skylake: Use CPU MP Init Common codeBarnali Sarkar
This patch uses the common CPU Mp Init code. BUG=none BRANCH=none TEST=Build and boot poppy Change-Id: Ieb2f8ae25a31e86e9251fe97859678745fe610f5 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-23soc/intel/common/block: Add common MP Init codeBarnali Sarkar
This patch contains State Machine callbacks init_cpus() and post_cpu_init(). Also, it has the SOC call for CPU feature programming. Change-Id: I5b20d413c85bf7ec6ed89b4cdf1770c33507236b Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-22soc/rdc: Remove r8610 SoCMartin Roth
Bifferboard was the only board that used this chip, and it has now been removed. Removing the chip as well. If there is desire to continue work on the board, it can be found in the 4.6 branch. Change-Id: I33a1e713cdfea47abce71b79f0a9c93562c96d12 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-20soc/intel/common: Add SMM common code for Intel PlatformsBrandon Breitenstein
SMI code is very similar across Intel platforms. Move this code to common/block/smi to allow it to be shared between platforms instead of duplicating the code for each platform. smihandler.h has already been made common so all it will contain is name changes and a move to the common block location. Due to moving smihandler code, APL changes are bundled here to show this change. Change-Id: I599358f23d5de7564ef1ca414bccd54cebab5a4c Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/19392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-20soc/intel/quark: Add legacy SPI flash controller driverLee Leahy
Add SPI driver code for the legacy SPI flash controller. Enable erase and write support allowing coreboot to save non-volatile data into the SPI flash. TEST=Build and run on Galileo Gen2. Change-Id: I8f38c955d7c42a1e58728c728d0cecc36556de5c Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-19rockchip/rk3399: fix DRAM gate training issueLin Huang
The differential signal of DQS needs to keep low level before gate training. RPULL will connect 4Kn from PADP to VSS and a 4Kn from PADN to VDDQ to ensure it. But if it has PHY side ODT connected at this time, it will change the DQS signal level. So it needs to disable PHY side ODT when doing gate training. BRANCH=None BUG=None TEST=boot from bob Change-Id: I56ace8375067aa0bb54d558bc28172b431b92ca5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: cb024042c7297a6b17c41cf650990cd342b1376f Original-Change-Id: I33cf743c3793a2765a21e5121ce7351410b9e19d Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/448278 Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/18582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-16soc/intel/skylake: Use SCS common codeBora Guvendik
This patch uses common SCS library to setup sd card. Change-Id: I06898e30a9b39f169b35f581a3ee09238f0f40c4 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/20217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-16soc/intel/apollolake: Use SCS common codeBora Guvendik
This patch uses common SCS library to setup sd card. Change-Id: Iafbba04d7a498b9a321e8efee4abf07820d17330 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/19632 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-16soc/intel/common/block: Add Intel common SCS code supportBora Guvendik
Create Intel Common SCS code. This code currently only contains the code for SD card SSDT generation. More code will get added up in the subsequent phases. Change-Id: I82f034ced64e1eaef41a7806133361d73b5009d3 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/19631 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-16soc/intel/common/block/cse: Add GLK PCI IDHannah Williams
Change-Id: I88e376d61c4aba5030a0be7c8bdfe7b57881a197 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/20169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-16soc/intel/braswell: Hide some Kconfig options in menuconfigArthur Heymans
Don't allow the user to set PCIe configspace base address. Don't allow the user to set the DCACHE size and base. Change-Id: I7a42cc5f6098214364624bcfa3cbd93b4903ee84 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-16soc/intel/skylake: Don't allow user to change DCACHE base and sizeArthur Heymans
Change-Id: Ic1656311ecc670dc0436995f0ec8199d270da4d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-16src/soc/intel: Don't allow user to select PCIe config mmio sizeArthur Heymans
Change-Id: I8b2794f56f39492589a08e5676cb33eec89a976e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20179 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-16src/soc/intel/common: Don't allow user to change PCIe BARArthur Heymans
Change-Id: I254549057552be93611afa8ca52d22be220fe3dc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-16soc/intel/apollolake: Removing some menuconfig optionsArthur Heymans
Does not need to changeable in menuconfig. Change-Id: Id488f7333952d10d10a62ac75298ec8008e6f9b4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-15soc/intel/apollolake: revert CPU MP init prior to FSP-SAaron Durbin
A major regression was introduced with commit 6520e01a (soc/intel/apollolake: Perform CPU MP Init before FSP-S Init) where the APs execution context is taken away by FSP-S. It appears that FSP-S is not honoring the SkipMpInit UPD because it's been shown with some debug code that FSP-S is compeltely hijacking the APs: Chrome EC: Set WAKE mask to 0x00000000 Chrome EC: Set WAKE mask to 0x00000000 CBFS: 'VBOOT' located CBFS at [440000:524140) CBFS: Locating 'vbt.bin' CBFS: Found @ offset 2e700 size 1a00 Running FSPS in 4 secs.. 315875 4315875 cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work Running FSPS.. 4315875 4315875 ITSS IRQ Polarities Before: ITSS IRQ Polarities Before: IPC0: 0xffffeef8 IPC1: 0xffffffff IPC2: 0xffffffff IPC3: 0x00ffffff ITSS IRQ Polarities After: IPC0: 0xffffeef8 IPC1: 0x4a07ffff IPC2: 0x08000000 IPC3: 0x00a11000 This is essentially a revert of 6520e01a to fix the previous behavior. Change-Id: I2e136ea1757870fe69df532ba615b9bfc6dfc651 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20215 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2017-06-14soc/intel/skylake: Add missing PCH_DEV_* definitionsFurquan Shaikh
Change-Id: Ib7aa495ccfd405d6ffc968388c28dc540da2f525 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20203 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-14soc/intel/common/block/i2c: Ignore disabled I2C devicesFurquan Shaikh
If I2C device is disabled: 1. BAR for the device will be 0 2. There is no need to generate ACPI tables for the device TEST=Verified that if an i2c device is disabled statically in devicetree or dynamically in mainboard, then coreboot does not die looking for missing resources. Change-Id: Id9a790e338a0e6f32c199f5f437203e1525df208 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-14soc/intel/skylake: Add USB port number information to wake sourceFurquan Shaikh
USB port status register can be used to decide if a particular port was responsible for generating PME# resulting in device wake: 1. CSC bit is set and port is capable of waking on connect/disconnect 2. PLC bit is set and port is in resume state BUG=b:37088992 TEST=Verified with wake on USB2.0 port 3, mosys shows: 19 | 2017-06-08 15:43:30 | Wake Source | PME - XHCI (USB 2.0 port) | 3 Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-13Consolidate reset API, add generic reset_prepare mechanismJulius Werner
There are many good reasons why we may want to run some sort of generic callback before we're executing a reset. Unfortunateley, that is really hard right now: code that wants to reset simply calls the hard_reset() function (or one of its ill-differentiated cousins) which is directly implemented by a myriad of different mainboards, northbridges, SoCs, etc. More recent x86 SoCs have tried to solve the problem in their own little corner of soc/intel/common, but it's really something that would benefit all of coreboot. This patch expands the concept onto all boards: hard_reset() and friends get implemented in a generic location where they can run hooks before calling the platform-specific implementation that is now called do_hard_reset(). The existing Intel reset_prepare() gets generalized as soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now easily be added later if necessary). We will also use this central point to ensure all platforms flush their cache before reset, which is generally useful for all cases where we're trying to persist information in RAM across reboots (like the new persistent CBMEM console does). Also remove cpu_reset() completely since it's not used anywhere and doesn't seem very useful compared to the others. Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19789 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-12soc/baytrail: fix scope for I2C ACPI devicesMatt DeVillier
For an unknown reason, the I2C ACPI devices were placed under \SB intead of \SB.PCI0, as with all other non-Atom based Intel platforms. While Linux is tolerant of this, Windows is not. Correct by moving I2C ACPI devices where they belong. Also, adjust I2C devices at board level for google/rambi as to not break compilation. Change-Id: I4ef978214aa36078dc04ee1c73b3e2b4bb22f692 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20056 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-09soc/intel/apollolake: Use CPU common library codeBarnali Sarkar
This patch makes SOC files to use common/block/cpu/cpulib.c file's helper functions. Change-Id: I529c67cf20253cf819d1c13849300788104b083c Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19827 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09soc/intel/apollolake: Rename ACPI Base Address and Size MacroBarnali Sarkar
Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09soc/intel/skylake: Enable ACPI PM timer emulation on all CPUsSubrata Banik
This patch enables ACPI timer emulation on all the logical cpus. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Verify MSR 0x121 gets programmed on all logical cpus during coreboot MP Init. Change-Id: I2246cdfe1f60fd359b0a0eda89b4a45b5554dc4a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18288 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09soc/intel/skylake: Use CPU common library codeBarnali Sarkar
This patch makes SOC files to use common/block/cpu/cpulib.c file's helper functions. Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19566 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09soc/intel/common/block: Add Intel common CPU library codeBarnali Sarkar
Create Intel Common CPU library code which provides various CPU related APIs. This patch adds cpulib.c file which contains various helper functions to address different CPU functionalities like - cpu_set_max_ratio(), cpu_get_flex_ratio(), cpu_set_flex_ratio(), cpu_get_tdp_nominal_ratio(), cpu_config_tdp_levels(), cpu_set_p_state_to_turbo_ratio(), cpu_set_p_state_to_nominal_tdp_ratio(), cpu_set_p_state_to_max_non_turbo_ratio(), cpu_get_burst_mode_state(), cpu_enable_burst_mode(), cpu_disable_burst_mode(), cpu_enable_eist(), cpu_disable_eist(), cpu_enable_untrusted_mode() Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-06-09soc/intel/apollolake: Perform CPU MP Init before FSP-S InitBarnali Sarkar
As per BWG, CPU MP Init (loading ucode) should be done prior to BIOS_RESET_CPL. Hence, pull MP Init to BS_DEV_INIT_CHIPS Entry (before FSP-S call). BUG=none BRANCH=none TEST=Build and boot Reef Change-Id: I49f336c10d6afb71f3a3b0cb8423c7fa94b6d595 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20037 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09soc/intel/apollolake: Remove duplication of find_microcode_patch() codeBarnali Sarkar
Since get_microcode_info() is aleady searching for the microcode in cbfs, we can just add a intel_microcode_load_unlocked() call here to update the microcode. No need to duplicate finding microcode step during pre_mp_init() function. Change-Id: I525cab0ecc7826554f0a1209862e6357d1c7a9a6 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-06-09soc/intel/skylake: Move update microcode from cbfs to mp_ops callbacksBarnali Sarkar
FIT is already loading microcode before CPU Reset. So, we need not update the microcode again in RO FW in bootblock. But we need to update in RW FW if there is any new ucode version. So, added the update microcode function in get_microcode_info callback before MP Init to make sure BSP is using the microcode from cbfs. BUG=none BRANCH=none TEST=Build and Boot poppy Change-Id: I5606563726c00974f00285acfa435cadc90a085e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20051 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-06-09soc/intel/skylake: Cache the MMIO BIOS regionAaron Durbin
If the boot media is memory mapped temporarily mark it as write protect MTRR type so that memory-mapped accesses are faster. Depthcharge payload loading was sped up by 75ms using this. Change-Id: Ice217561bb01a43ba520ce51e03d81979f317343 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-09soc/intel/apollolake: use fast_spi_cache_bios_region()Aaron Durbin
The fast_spi_cache_bios_region() does the necessary lookup of BIOS region size, etc. Don't inline the calculation and just defer to the common piece of code for memory-mapped spi flash boot. Change-Id: I6c390aa5a57244308016cd59679d8c3ab02031b8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-09soc/intel/common/fast_spi: support caching bios in ramstageAaron Durbin
After the MTRR solution has been calculated provide a way for code to call the same function, fast_spi_cache_bios_region(), in all stages. This is accomplished by using the ramstage temporary MTRR support. Change-Id: I84ec90be3a1b0d6ce84d9d8e12adc18148f8fcfb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20115 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-09soc/intel/apollolake: Use common systemagent codeSubrata Banik
This patch perform resource mapping for PCI, fixed MMIO, DRAM and IMR's based on inputs given by SoC. TEST=Ensure PCI root bridge 0:0:0 memory resource allocation remains same between previous implementation and current implementation. Change-Id: I15a3b2fc46ec9063b54379d41996b9a1d612cfd2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/19795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09soc/intel/skylake: Use common systemagent codeSubrata Banik
This patch perform resource mapping for PCI, fixed MMIO, DRAM and IMR's based on inputs given by SoC. TEST=Ensure PCI root bridge 0:0:0 memory resource allocation remains same between previous implementation and current implementation. Change-Id: I93567a79b2d12dd5d6363957e55ce2cb86ff83a7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/19796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09soc/intel/common/block: Add Intel common systemagent supportSubrata Banik
Add Intel common systemagent support for romstage and ramstage. Include soc specific macros need to compile systemagent common code. Change-Id: I969ff187e3d4199864cb2e9c9a13f4d04158e27c Signed-off-by: V Sowmya <v.sowmya@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/19668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09soc/braswell: fix ACPI table by recollecting TOLMHarry Pan
cherry-pick from Chromium, commit 8fbe1e7 On Braswell and Baytrail devices, by userland 'perf top', observed demanding clocks on __vdso_clock_gettime() since chromeos_3.18 kernel; besides, evaluated massive calling of clock_gettime() cost, up to 700 ns in average. It turns out that Linux kernel of map_vdso() first call of remap_pfn_range() does not fall into reserve_pfn_range() due to size parameter, instead it relies on lookup_memtype() and potentially be failed to be identified as eligible RAM resource because the function of pat_pagerange_is_ram() actually walks through root's sibling. Meanwhile, on current BSW (and BYT) firmware implementation makes System RAM resources located on child leaf, combining all of these factors makes the kernel treat the vvar page of vdso as a uncached-minus one leading slow access in result. This patch recollects TOLM accessing; as Aaron recalled some core_msr_script turns off access to TOLM register, he suggests to store tolm to avoid getting back a zero while setting acpi nvs space. Original-Change-Id: Iad4ffa542b22073cb087100a95169e2d2a52efcd Original-Signed-off-by: Harry Pan <harry.pan@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/368585 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Idc9765ec5c0920dc98baeb9267a89bec5cadd5a0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09soc/broadwell: Allow disabling of PCIe ASPM optionsYouness Alaoui
The ASPM options (L1 substates, CLKREQ support, Common Clock and ASPM) are hardcoded for broadwell chips, but some boards may not support these ASPM options even if the SoC does support it (non-wired CLKREQ pin for example). This is required to disable L1 substates on the Purism/Librem 13 which seems to have issues with NVMe drives falling into L1.2 state and not being able to exit that state. Change-Id: I2c7173af1d482cccdc784e3fa44ecbb5d38ddc34 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09soc/baytrail: fix ACPI table by recollecting TOLMMatt DeVillier
Adapted from Chromium commit 8fbe1e7 for soc/braswell (also review.coreboot.org/#/c/20060/); same issue affects baytrail as well. This patch recollects TOLM accessing; as Aaron recalled some core_msr_script turns off access to TOLM register, he suggests to store tolm to avoid getting back a zero while setting acpi nvs space. Change-Id: Ib26d4fe229b3f7d8ee664f5d89774d1f4a997f51 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09soc/baytrail: assign unique DMA request lines to I2C controllersMatt DeVillier
Each I2C controller should have a unique pair of DMA request lines, and DMA channels should be assigned incrementally, rolling over as necessary. Source: Intel Baytrail/ValleyView UEFI reference code Change-Id: Icc9b27aaa14583d11d325e43d9165ddda72ca865 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09soc/braswell: assign unique DMA request lines to I2C controllersMatt DeVillier
Each I2C controller should have a unique pair of DMA request lines, and DMA channels should be assigned incrementally, rolling over as necessary. Source: Intel Braswell UEFI reference code Change-Id: I1d97b5a07bf732c27caf57904c138b120b93ca81 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09soc/braswell: fix scope for I2C ACPI devicesMatt DeVillier
For an unknown reason, the I2C ACPI devices were placed under \SB intead of \SB.PCI0, as with all other non-Atom based Intel platforms. While Linux is tolerant of this, Windows is not. Correct by moving I2C ACPI devices where they belong. Also, adjust I2C devices at board level for intel/strago and google/cyan as to not break compilation. Change-Id: Iaf8211bd86d6261ee8c4d9c4262338f7fe19ef43 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20055 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09soc/skylake: add ACPI method to generate USB port infoMatt DeVillier
Add ACPI method GPLD to generate port location data when passed visiblity info. Will be used by _PLD method in board-specific USB .asl files. Change-Id: I14ba3cea821e103208426e9fcaa0833d84157ff8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-08fsp/gop: Add running the GOP to the choice of gfx initNico Huber
The new config choice is called RUN_FSP_GOP. Some things had to happen on the road: * Drop confusing config GOP_SUPPORT, * Add HAVE_FSP_GOP to chipsets that support it, * Make running the GOP an option for FSP2.0 by returning 0 in random VBT getters. Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-08device/Kconfig: Introduce MAINBOARD_FORCE_NATIVE_VGA_INITNico Huber
MAINBOARD_FORCE_NATIVE_VGA_INIT is to be selected instead of the user option MAINBOARD_DO_NATIVE_VGA_INIT. The distinction is necessary to use the latter in a choice. Change-Id: I689aa5cadea9e1091180fd38b1dc093c6938d69c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-07spi: Remove unused/unnecessary spi_init function definitionsFurquan Shaikh
Remove spi_init definitions which: 1. Do nothing 2. Set static global variables to 0 Change-Id: If4c0cdbe2271fc7561becd87ad3b96bd45e77430 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20039 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-07intel/common/acpi: Fix ACPI debug log issue with LPSS UARTSubrata Banik
This patch fixes ACPI debug print issue reported internally while using APRT asl method. Potentially some junk characters gets added into final print buffer due to LPSS MMIO register space is 32 bit width and ADBG is one byte at a time. TEST=Built and boo eve to ensure to be able to get ASL console log without any corruption. Change-Id: I0b6af789c0ffc79f7fee4652b4aa6a125b182296 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-07src: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-07Use more secure HTTPS URLs for coreboot sitesPaul Menzel
The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 12:08:31 +0000