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2018-05-09drivers/intel/gma, soc/intel/common: improve cooperationPatrick Georgi
Instead of both featuring their own VBT loaders, use a single one. It's the compression-enabled one from soc/intel/common, but moved to drivers/intel/gma. The rationale (besides making all the Kconfig fluff easier) is that drivers/intel/gma is used in some capacity on all platforms that load a VBT, while soc/intel/common's VBT code is for use with FSP. BUG=b:79365806 TEST=GOOGLE_FALCO and GOOGLE_CHELL both build, exercising both affected code paths. Change-Id: I8d149c8b480e457a4f3e947f46d49ab45c65ccdc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/26039 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09sdm845: Add DRAM resourcesT Michael Turney
TEST=build Change-Id: Icf934caf8b4584ef2633054a5cc7f5be7cc734ee Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-09vendorcode/amd/pi/00670F00: Control which procedure buildsRichard Spiegel
Vendor code is compiled as a library, thus the whole library is included into the final image. However, not all procedures are required, they are there because original AGESA code had them. We cannot remove them, in order to facilitate porting of fixed AGESA code. Therefor add #if throughout the code to allow the control if unneeded procedures will be build. BUG=b:78610011 TEST=Build and boot grunt; build kahlee and gardenia. Change-Id: I68f9e359b2331f715a3b85486c4181866985afdf Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26135 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08amd/common/pi: Insert missing newline in printkMarshall Dawson
Add a newline to the unsupported callout message. Change-Id: I9bfff0ed920843f6c0818b51ee0046366f2a5c8d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08soc/intel/skylake: Support PCH UART 0 and 1 for consoleDuncan Laurie
The current PCH UART support for console is limited to UART2. This change adds support for specifying UART0 or UART1 to be used instead by changing CONFIG_UART_FOR_CONSOLE in the board level Kconfig. The default is still 2. This is tested with a board that uses UART0 for debug output. Change-Id: I91323ed3298f9b2558764aa4b54173833c021a7b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/26140 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08soc/intel/fsp_broadwell_de: Spell verb *set up* with spacePaul Menzel
Change-Id: If2e66f3531696d430b3ae133c4b7ec0d929713b7 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/26129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-08soc/intel/denverton_ns: Fill dimm info for SMBIOS table 17Julien Viard de Galbert
Rework display_fsp_smbios_memory_info_hob (shared code). Import code to convert memory HOB to dimm info for SMBIOS table 17 mostly copied from fsp1_1 mainboard_save_dimm_info. Change-Id: Id5c4ceaf4e65359f72ec764f0914b5daa82f257e Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23851 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
pci_bus_default_ops() is the default anyway. Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08intel/broadwell: Add option to enable/disable the PCIe AER capabilityYouness Alaoui
The Advanced Error Reporting capability was hardcoded in the PCIe extended capability list, but it might not always be possible. The Librem 13v1 does not seem to have working AER and this option was needed and tested on the Librem 13v1. Without it, the linux console gets spammed with AER errrors. Change-Id: If2e0ec42c93f1fee927eacdf0099004cf9302fbe Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/25326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08intel/broadwell: If L1 Sub state is disabled, do not set capabilityYouness Alaoui
I finally found out why disabling the L1 sub state option did not prevent some NVMe drives from locking up in L1 substate. I expect that the disabled L1 substate initialization that coreboot does is negated because Linux might itself configure it if it finds the capability enabled on the PCIe root port. Removing the capability from the PCIe root port when L1 sub states are disabled in the configuration should fix the problem. This was not tested because it's a difficult issue to reproduce and I do not have the problematic hardware that caused it anymore. Change-Id: I293a650db307e77cee024a43fbfc81e1d8c86265 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/25325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-05intel/acpi: Fix ACPI compile errorLijian Zhao
According to ACPI 6.1 spec 19.6.44, External informs compiler that object is external to this TABLE, no necessary for object in same DSDT tables. BUG=None TEST=Build pass Intel mainboard with 20180427 iasl. Change-Id: I153e7d0e97f9a29919676fbb73a7c26fd22f252c Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/26045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-05soc/intel/cannonlake: Include stage cache support for CNLSubrata Banik
TEST=Build and boot cannonlake rvp. cpu_index() returns correct cpu index based on caller. Change-Id: I23f80ef455d075a14121577f401cfc7c44ba0cfa Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-05soc/intel: Add KBL-R pci id supportLijian Zhao
Add KBL-R internal graphics device pci ids into coreboot. BUG=N/A TEST=Boot up fine on kabylake-r platform with display on. Change-Id: I0813247624770b70fe8b3ec3825fd17a9878cd0e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/26018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@chromium.org>
2018-05-05fsp_broadwell_de: Add option to enable EHCI controllersDavid Hendricks
Change-Id: I74ee9448923015ac5ec3eec770669f3491a375ba Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/26042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-04soc/intel/common: Allow exporting the size of the VBTPatrick Georgi
Change-Id: Ib340aad846ea7cb61d650928b495efaa1fc2d641 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/26038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-04soc/intel: unify VBT fetching APIPatrick Georgi
Skylake used the inner function, wrapping it in the same set of tests as the common code does, but expressed differently. Change-Id: Ifa6912255e7874a6e80301d49128adda6f624209 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/26037 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04soc/amd/stonyridge: Add misc deviceAkshu Agrawal
oscout system clock is present in FCH misc device. The kernel acpi misc driver will use the resource to register oscout system clock. BUG=b:74570989 TEST=Tested clock enable/disable in kernel driver Change-Id: Ia90d3abab447fb5d27f454d9d6c33d0b5c3a0f16 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/25918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04ifdtool: Add a list of known platforms that support IFD_VERSION_2Furquan Shaikh
ifdtool has relied on one of the fields within FCBA(read_freq) to determine whether a platform supports IFD_VERSION_1 or IFD_VERSION_2. However, newer platforms like GLK and CNL do not have read_freq field in FCBA and so the value of these bits cannot be used as an indicator to distinguish IFD versions. In the long run, we need to re-write ifdtool to have a better mapping of SoC to IFD fields. But until that is done, this change adds a list of platforms that we know do not support read_freq field but still use IFD_VERSION_2. This change also updates GLK and CNL to pass in platform parameter to ifdtool. BUG=b:79109029, b:69270831 Change-Id: I36c49f4dcb480ad53b0538ad12292fb94b0e3934 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04soc/amd/stoneyridge: Remove USB30PortInit settingMartin Roth
This bitmask sets the USB PORTSC.DR bit for each XHCI port. This is mainboard specific, and only for non-removable devices attached to the XHCI port. BUG=b:72859972 TEST=Boot grunt Change-Id: I0488b80da1fe4e57b06d3bc7a93ad9ebbfc97749 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/26015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-05-02soc/amd/stoneyridge: remove sb_set_readspeed functionMarc Jones
The sb_set_readspeed() was touching the wrong register and the read speed settings are handled by sb_set_spi100(). Nothing was using the function, so remove it. Change-Id: I23b20cf559ee759ba94d49ff6810a9baa64e86fb Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-02intel/common: compress VBTPatrick Georgi
It's pretty well compressible which helps when space is tight. The code encodes the assumption that the VBT is 8kb or less. Haven't seen a larger one yet. BUG=b:77971803,b:78541692 TEST=build, see that vbt.bin is compressed, boot, check log that the reported VBT size is correct. Change-Id: Ie25bca21d9edc408f441a292bbe2ab0459948ec4 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/25927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-01sdm845: Add Timer supportT Michael Turney
Frequency set to 19.2 MHz TEST=build Change-Id: I56e57156df8a74cf629f7ada86cf5a5fcd5ad3c4 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-01chromeec platforms: Update ACPI thermal event handler callMartin Roth
Currently the thermal event handler method TEVT is defined as an extern, then defined again in platforms with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. Change-Id: I64dcd2918d14f75ad3c356b321250bfa9d92c8a5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-30soc/intel/braswell: remove stale spi_loading.cAaron Durbin
CONFIG_ALT_CBFS_LOAD_PAYLOAD has long since been removed. Clean up the remnants in braswell. Change-Id: I88483a4c3a74ed0c7defacf872b1564c3ce7f909 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-30soc/amd/stoneyridge/gpio.c: Fix gpio_output()Richard Spiegel
Function gpio_output() is only setting the pin as an output, when in fact it should also set the state (high/low) of the pin. Fix the procedure to set the state of the pin. BUG=b:78328773 TEST=None Change-Id: I516192a0782a9bbb40124029f264a2711114c800 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-30mb/google/octopus: Fix crossystem wpsw_cur errorHannah Williams
With only one entry for Write Protect gpio in the OIPG package, the sysfs entry /sys/devices/platform/chromeos_acpi/GPIO.x is created as "GPIO" instead of "GPIO.x". This was causing crossytem to return error for wpsw_cur. BUG=b:78009842 Change-Id: Ica60f342420d95d09a45580f2f940443c03601de Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-27soc/intel/apollolake: enable cache-as-ram paging for glkAaron Durbin
Add support and enalbe cache-as-ram paging for glk to work around a cache-as-ram corruption issue. glk executes verstage, romstage, and FSP-M directly out of cache-as-ram (just like apl). However, the front end on glk is very agressive about pulling cache lines into L1I for potential execution. When the snoops hit in the L1D and the cache lines are dirty the processor writes the line back. However, there is no backing store for the dirty lines to go. As such when the line is pulled back in the value is all 0xff's, corrupting cache-as-ram. To fix the issue one needs to enable paging with NX (no execute) permissions which prevents the above actions from happening because the TLB will indicate that shouldn't be fetched into the instruction cache since data will be marked no execute. The generated page tables are added to cbfs and only added to the COREBOOT cbfs as they are only consumed in the early cache-as-ram stages. The page tables generated with: $ go run util/x86/x86_page_tables.go \ --iomap_file=src/soc/intel/apollolake/glk_page_map.txt \ --metadata_base_address=0xfef00000 \ --pdpt_output_c_file=src/soc/intel/apollolake/pdpt.c \ --pt_output_c_file=src/soc/intel/apollolake/pt.c Merged address space: 00000000d0000000 -- 00000000fef00000 UC NX : 375 big 256 small 00000000fef00000 -- 00000000fef20000 WB NX : 0 big 32 small 00000000fef20000 -- 00000000fefc0000 WB : 0 big 160 small 00000000fefc0000 -- 00000000ff000000 WB NX : 0 big 64 small 00000000ff000000 -- 0000000100000000 WP : 8 big 0 small Total Pages of page tables: 5 Pages linked using base address of 0xfef00000. BUG=b:72728953 Change-Id: Icde9cc0bf5079bb5821f4e59eb61e939c13d7062 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-27soc/amd/stoneyridge/include/soc/smi.h: Fix name collisionRichard Spiegel
When smi.h is included to southbridge.h (to use SCI/SMI definitions within southbridge.h definitions), this causes a collision of the definition of NONE (ioapic.h also has a NONE definition). As NONE is an enumeration of interrupt types (SCI/SMI), add INTERRUPT_ at the start of each definition. This is preparation to have GPIO table/code also declare/program SCI/SMI. BUG=b:72875858 TEST=Build grunt. Change-Id: I5c7b798f9f4d7c2a9f9c606c7ebffb7004a37b99 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25845 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27soc/amd/stoneyridge: Enable CMOS VBNV backup to flashMarc Jones
Now that we have SPI flash writes working, we can support VBOOT_VBNV_CMOS_BACKUP_TO_FLASH. This requires the mainboard to reserve the area in FMAP. BUG=b:77347873 TEST=Manually clear CMOS and check coreboot restores VBNV from flash. Change-Id: I488dbfc4c200f5100374d47feb0a0522e6a60e88 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25842 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27soc/intel/common/block/xdci: Use vboot_can_enable_udc in xdci_can_enableFurquan Shaikh
This change uses the newly added vboot_can_enable_udc to decide if it is okay to enable xDCI in vboot developer mode. BUG=b:78577893 BRANCH=poppy Change-Id: Ia83b91ce17eec782faf5bb318ad8c00c09e2db05 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-26soc/amd/common/block/include/amdblocks/psp.h: Replace todo messageRichard Spiegel
It was decided to not add the buffers definitions, so the todo message is obsolete. Replace it with minimum instructions about when a new buffer will be needed. It was also noticed a typo in one command. MBOX_BIOS_CMD_C3_DATA_INFO is about S3 transition, so it should be called MBOX_BIOS_CMD_S3_DATA_INFO. BUG=b:77940747 TEST=None. Change-Id: I6143d7e85476061395962b95ad8864ac32a1d4a3 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25740 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26src: Fix a typo on "mtrr"Elyes HAOUAS
Change "mttrs" to mtrrs. Change-Id: I4e5930cdcba5e8f5366bb2d4ebbcb659c0c2eb27 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-26soc/intel/apollolake: enable exception handling in every stage for glkAaron Durbin
Now that an idt is available in every stage utilize it for exception processing to help catch and debug issues. BUG=b:72728953 Change-Id: I69e7f938f36f2e522b787e311fd148bb8fd41247 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25764 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26src/sifive: Add the SiFive Freedom Unleashed 540 SoCJonathan Neuschäfer
The FU540 is the first RISC-V SoC with the necessary resources to run Linux (an external memory interface, MMU, etc). More information is available on SiFive's website: https://www.sifive.com/products/hifive-unleashed/ Change-Id: Ic2a3c7b1dfa56b67cc0571969cc9cf67a770ae43 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-26soc/amd/stoneyridge: Fix smi_write32 arg order in disable_all_smi_statusDaniel Kurtz
The argument order for smi_write32() is offset, value. Current code had it backwards. So, when disable_all_smi_status() was called by sb_slp_typ_handler(), instead of clearing pending flag SlpTypeEvent65 (0x2) in SMIx88 SmiStatus2 by writing 0x00000002 to 0xfed80288, it would instead write 0x00000088 to 0xfed80202 - clearing the lower 2 bytes of SMIx04 Event_Enable, which disabled the lower 16 GPEs from waking the system from S3. Thus, the EC events (Keyboard / lid switch) [GPE15] and touchpad [GPE7] did not work as wake up sources. BUG=b:78461678 TEST=powerd_dbus_suspend, tapping any key on keyboard wakes from S3. Change-Id: Ie4fbe6db1bb73f603dcf409117fcce93479a1f46 Fixes:081851a9e4 ("amd/stoneyridge: Add SlpTyp SMI handler") Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-26soc/amd/stoneyridge: Static constify smi_sourcesDaniel Kurtz
smi_sources is a file local array of constants. Change-Id: I431f181449a591ccaf8395f01a84c8e006a29b52 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-25soc/intel/apollake: add support for tracking memory detailsAaron Durbin
It's going to be necessary to know the i/o hole size as well the amount of memory configured in the sytsem. Therefore, add two helper functions: memory_in_system_in_mib() iohole_in_mib() Both return values in units of MiB. BUG=b:72728953 Change-Id: I481ba517c37f769e76d9e12b3631f5f99b5427a9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25738 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-25soc/intel/common: disable paging if PAGING_IN_CACHE_AS_RAM enabledAaron Durbin
When tearing down cache-as-ram disable paging if PAGING_IN_CACHE_AS_RAM is enabled. BUG=b:72728953 Change-Id: I86e8a57a1187876dcbedce9f4f6b05be30aea7c6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-25soc/amd/stoneyridge: Add additional early LPC and SPI initMarc Jones
Additional LPC and SPI setup needed to move AGESA out of the bootblock. Setup the prefetch, sio decode, and a bugfix for SPI. BUG=b:70558952 TEST=Boots with AGESA moved out of bootblock. Change-Id: I2c0d8632b25c036ff977c21477feb4778575189c Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/25755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-25soc/intel/apollolake: Sync FSP PCIE NPK device as per devicetreeShaunak Saha
This patch makes our devicetree in sync with the FSP configuration. Without this we see in boot logs "PCI: 00:00.2 not found, disabling it". The reason being in FSP NPK device is disabled by default. We can enable it by enabling the UPD parameter TraceHubEn. If we enable it in FSP then the logs complain the NPK pcie device is not seen. BUG=b:76115112 TEST=Build for Octopus and check that the logs do not report "PCI: 00:00.2 not found, disabling it". Change-Id: I8fe3a36dac2eff2225dacb0e6e16500a5750261e Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-24soc/amd/common/block/pi/amd_late_init.c: Fix illegal memory accessRichard Spiegel
Found-by: Coverity (CID 1387031: Memory - illegal accesses (BUFFER_SIZE_WARNING)). Calling strncpy with a maximum size argument of 19 bytes on destination array "dimm->module_part_number" of size 19 bytes might leave the destination string unterminated. Fix the size parameter. BUG=b:76202696 TEST=Build and boot kahlee, using special debug code to see the output strings, which was later removed. Change-Id: I18fa5e9c73401575441b6810f1db80d11666368c Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-23drivers/spi: reduce confusion in the APIAaron Durbin
Julius brought up confusion about the current spi api in [1]. In order alleviate the confusion stemming from supporting x86 spi flash controllers: - Remove spi_xfer_two_vectors() which was fusing transactions to accomodate the limitations of the spi controllers themselves. - Add spi_flash_vector_helper() for the x86 spi flash controllers to utilize in validating driver/controller current assumptions. - Remove the xfer() callback in the x86 spi flash drivers which will trigger an error as these controllers can't support the api. [1] https://mail.coreboot.org/pipermail/coreboot/2018-April/086561.html Change-Id: Id88adc6ad5234c29a739d43521c5f344bb7d3217 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-23cpu/x86: move NXE and PAT accesses to paging moduleAaron Durbin
The EFER and PAT MSRs are x86 architecturally defined. Therefore, move the macro defintions to msr.h. Add 'paging' prefix to the PAT and NXE pae/paging functions to namespace things a little better. BUG=b:72728953 Change-Id: I1ab2c4ff827e19d5ba4e3b6eaedb3fee6aaef14d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-23soc{broadcom,imgtec,mediatek,qualcomm}: stop using spi_xfer_two_vectorsAaron Durbin
On a second look broadcom/cygnus and imgtec/pistachio appear to support full duplex. Therefore, remove the use of spi_xfer_two_vectors(). For mediatek/mt8173 and qualcomm/ipq40xx, the driver is written in such a way that it does not support full duplex. Remove the use of spi_xfer_two_vectors() and explicitly error out when a full duplex transaction is requested. Change-Id: I8689bc9bb2b27563d25e9f165487d38881c0b059 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25742 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-20pci: Move inline PCI functions to pci_ops.hPatrick Rudolph
Move inline function where they belong to. Fixes compilation on non x86 platforms. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-20soc/amd/stoneyridge/include/soc/southbridge.c: Rename gpio structureRichard Spiegel
The GPIO definition structure has evolved to a point where it's no longer specific to stoneyridge, though probably still specific to AMD. Therefore, rename the GPIO declaration structure removing stoneyridge from it. BUG=b:72875858 TEST=Build kahlee, grunt, gardenia. Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25726 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-20soc/intel/common: Adjust LPC Generic IO setupLijian Zhao
Check same IO ranges get programmed first, if so just skip it to avoid double programming. BUG=b:77944335 TEST=Boot up with mewoth board, and check serial log, there's no error message about "LPC: Cannot Open IO Window: ". Change-Id: I89f9bb70320f91b16c6084384c4a0a53ede3760c Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25667 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-19soc/amd/common/block/pi/heapmanager.c: Simplify codeRichard Spiegel
There are sections of code that are almost identical and they can be converted to auxiliary procedures. For allocating heap, 3 sizes (the buffer size of currently being examined node, the buffer size of the current best fit node and the minimum size for a buffer that will need to be split if selected as the best fit) are used often so they could be stored in temporary variables. These 2 changes will make code shorter, with less indentation problems and overall easier to read. The actual logic of the code is not changed. BUG=b:77940747 TEST=Build and boot grunt. Change-Id: Ib4c69981eab7452228ccae9ed9bc288c8baceffe Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25703 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-19soc/intel/cannonlake: Set DISB after Dram initLijian Zhao
DRAM Initialization Scratchpad Bit needs to be set after Dram Initialization finished, according to Cannonlake PCH-LP EDS(#565870) chapter 5.3.1. BUG=None Change-Id: I16dd3787cb743bc5b7492042f3c3757534e1a51c Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Kin Wai Ng <kin.wai.ng@intel.com>
2018-04-19soc/intel/apollolake: fix 'DENSITY' misspellingAaron Durbin
DESNITY is not DENSITY. Fix that error. BUG=b:72728953 Change-Id: I1e4ebec378a20cefc7c1e4114d39b707fc767fc1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25735 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-19soc/intel/cannonlake: Force LPC IO decode settingsLijian Zhao
Force PCH LPC generic IO ranges are identical between PCH LPC pci config space and DMI PCR registers. Reference documentation from 570374 chapter 2.4.1. Bug=77944335 TEST=Boot up in OS in meowth board, using iotools to read LPC pci config space offset 0x84~0x90 and compare with values read from DMI PCR private register offset 0x2730~0x273c are identical. Change-Id: I72a40360ba67f443f24468f10504d8cfd0b099ca Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25668 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-18soc/amd/stoneyridge/include/soc/gpio.h: Remove vendor code referenceRichard Spiegel
With the exception of code that deals directly or indirectly with AGESA, all other code should be independent of vendor code reference. Therefore, remove vendor code reference from any GPIO code. BUG=b:77999987 TEST=Build and boot grunt. Change-Id: I9ba78767a269ad6b9b06fa11993d8a12350e4bad Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25695 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-17soc/intel/apollolake: Implement _PS0/_PS3 methods for PCIe root portsVenkateswarlu Vinjamuri
Creates a common asl include file for PCIe power state methods. This allows ports to be enabled independently. BUG=None BRANCH=None TEST=None Change-Id: I7b1cf4e14ebdfe9ecc7131dfe47c70ed7e2c3dc5 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/25532 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-17soc/intel/apollolake: Configure PCIe root port #3 for GLK WiFiVenkateswarlu Vinjamuri
GLK Octopus uses PCIe root port #3 (PCIe ID 13.0) for discrete PCIe wifi card. BUG=None BRANCH=None TEST=Use Stone Peak discrete wifi card and test s0ix. Change-Id: I8a064c5d97e4765bd97ec560c89b207b574b1fa1 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/25638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-17soc/intel/apollolake: Configure PCIe root port #1 for APL WiFiVenkateswarlu Vinjamuri
APL uses PCIe root port 1 (PCIe ID 14.0) for discrete PCIe wifi card. BUG=None BRANCH=None TEST=Use Stone Peak discrete wifi card and test s0ix. Change-Id: Ia81722f4533916fe93009a73d86765e5de9dab08 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/25637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-17soc/intel/skylake: check DPTF_TSR0_ACTIVE_AC* in _ACx methodsFrank Wu
Because thermal table is not included the values of DPTF_TSR0_ACTIVE_AC5 and DPTF_TSR0_ACTIVE_AC6 from internal nami/vayne thermal team. Add conditional compilation in _ACx methods if DPTF_ENABLE_FAN_CONTROL is defined in the dptf.asl. BUG=b:72974136 BRANCH=poppy TEST=emerge-nami coreboot and booted on nami board. Change-Id: I3e36ce94f714ff13f8ccee65992d7a9c7e0bb5b2 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25614 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16soc/amd/stoneyridge/northbridge.c: Fix bit definitionsRichard Spiegel
The latest public BKDG (3.6) releases some previously undefined (reserved) bits. Fix these definitions, including the header file where they are defined. BUG=b:77940747 TEST=Build and boot grunt. Change-Id: Icb5334110248d7806421200a161fa3befefcea8a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25665 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16soc/amd/stoneyridge/lpc.c: Fix bit definitionsRichard Spiegel
The latest public BKDG (3.6) releases some previously undefined (reserved) bits, also some bits were wrongly named (possibly copied from previous chip). Fix these definitions, including the header file where they are defined. BUG=b:77940747 TEST=Build and boot grunt. Change-Id: Ie8d3fcccb8443c1a6db828bdc2624778bad6ba9f Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16soc/intel/skylake: Hook up libgfxinitNico Huber
Also base the FSP/GOP related bail-out on the correct Kconfig option to allow adding a VBT along with libgfxinit. Most things should work, what doesn't is backlight control because coreboot misses the settings (moved to FSP and need backporting). Also, Kaby Lake is still unsupported. TEST=Booted yet to be upstreamed Skylake-S port (Kontron/bSL6) both with text and linear framebuffer mode and viewed a FILO menu. Change-Id: I79fbfed7732cf02d054530ea7ec0d34de32836ba Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-04-16intel/fsp_broadwell_de: Set FSP serial speed to match coreboot'sDavid Hendricks
This makes FSP use the same baud rate as coreboot so that the user can more easily change it without having to modify the FSP binary. Change-Id: I0084aa9a0394ad7eabdd88809b66fc21a25ba316 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/25666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-16soc/intel/apollolake: Fix CPU address bitsHannah Williams
APL and GLK have 39 address bits Change-Id: I9b761492332c545c13a0594d8f5937ca84bc0699 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16soc/intel/apollolake: update cache options for glkAaron Durbin
On glk there's a 4MiB L2 cache all the time. Take advantage of that by initializing a 1MiB cache-as-ram area. BUG=b:72728953 Change-Id: Ia4e777a13607d8b70c05534b0a172f0ec6b04c51 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25645 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16intel/fsp_broadwell_de: Remove buggy code for SMBus clock gatingWerner Zeh
The pch_smbus_init() function contains code to enable clock gating for the SMBus controller. Unfortunately this code is buggy and leads to a hanging system with the latest microcode version. The hang occurs as follows: The clock gate register is mapped into RCBA space. After reading the RCBA address from the LPC device config space no mask is applied to the value (only bits 31..14 are valid while bit 0 is the enable bit). For this reason the final address is off by one. The old microcodes at least allowed this unaligned access to the RCBA space. With the latest microcode this access leads to CPU hang. Once this is fixed the next issue occurs: After setting the clock gating bit for SMBus (bit 5) the SMBus controller disappears from the PCI bus completely and hence no usage of it is possible anymore. To fix this issue the clock gating code is completely removed as it was intentionally meant to enable clock gating on the SMB_CLK line and not the clock gating on the PCIe interface of the SMBus controller. This issue is known already and was discussed on the mailinglist: [coreboot] BDX-DE PCI init fail https://mail.coreboot.org/pipermail/coreboot/2018-January/085908.html TEST=Boot mc_bdx1 with microcode version M1050663_07000012. Change-Id: Icb86f4516f8a6e72552a44618737e682b0fdef33 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/25652 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13soc/amd/stoneyridge: add a romstage hook for mainboardsMartin Roth
There wasn't previously a way for Stoney platforms to run mainboard specific code in romstage. This adds an early call for configuration and passes along whether the system is currently resuming from S3. BUG=b:77921345 TEST=Build, verify that weak function implementation gets called. Change-Id: Id94855e1084814ec37956e603cd093d70f01a559 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-12include/memory_info.h: Change serial number field from 5 bytes to 4Raul E Rangel
dimm_info.serial had a strange contract. The SPD spec defines a 4 byte serial number. dimm_info.serial required a 4 character ascii string with a null terminator. This change makes the serial field so it matches the SPD spec. smbios.c will then translate the byte array into hex and set it on the smbios table. There were only two callers that set the serial number: * haswell/raminit.c: already does a memcpy(serial, spd->serial, 4), so it already matches the new contract. * amd_late_init.c: Previously copied the last 4 characters. Requires decoding the serial number into a byte array. google/cyan/spd/spd.c: This could be updated to pass the serial number, but it uses a hard coded spd.bin. Testing this on grunt, dmidecode now shows the full serial number: Serial Number: 00000000 BUG=b:65403853 TEST=tested on grunt Change-Id: Ifc58ad9ea4cdd2abe06a170a39b1f32680e7b299 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/25343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11soc/amd: Fix generating SMBIOS Type 17Raul E Rangel
The converter was setting SMBIOS values when dimm_info expects SPD values. dmidecode now shows the following: Memory Device Array Handle: 0x0000 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 8192 MB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR4 Type Detail: Synchronous Speed: 933 MT/s Manufacturer: Hynix/Hyundai Serial Number: 00000000 Asset Tag: Not Specified Part Number: HMAA51S6AMR6N-UH Rank: 1 Configured Clock Speed: 933 MT/s Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Example debug output: AGESA TYPE 17 DMI INFO: Handle: 1 TotalWidth: 64 DataWidth: 64 MemorySize: 8192 DeviceSet: 0 Speed: 1200 ManufacturerIdCode: 44416 Attributes: 1 ExtSize: 0 ConfigSpeed: 933 MemoryType: 0x1a FormFactor: 0xd DeviceLocator: DIMM 0 BankLocator: CHANNEL A SerialNumber(8): ' 00000000' PartNumber(20): 'HMAA51S6AMR6N-UH ' CBMEM_ID_MEMINFO: dimm_size: 8192 ddr_type: 0x1a ddr_frequency: 933 rank_per_dimm: 1 channel_num: 0 dimm_num: 0 bank_locator: 0 mod_id: 44416 mod_type: 0x4 bus_width: 3 serial: 0x00000000 module_part_number(18): 'HMAA51S6AMR6N-UH ' The serial number we get from AGESA (at least on my board) is always 00000000. I'm assuming this is because the SPD info is compiled in. `mosys memory spd print all` is still failing though. I will look into that next. BUG=b:65403853 BRANCH=dimm-info TEST=Test output above Change-Id: I076bc3f965f81a9374c8976da48c7fdce014dc0c Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/25304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG)Jonathan Neuschäfer
Fixes: 2269a3c328 ("soc/amd/stoneyridge: Add functions for GPIO interrupts") Change-Id: I5730259bc6819defc482d31644e1f476679257b2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25588 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11amd/stoneyridge: Reorder temp mtrr for flashMarshall Dawson
Relocate setting the temp range MTRR, for the SPI flash device, to after completion of mp_init. The mp_init functionality mirrors the BSP's exact MTRR settings into the AP cores. The ranges need to be the correct calculated values and not some temporary setting. This solves an MTRR sync issue on APUs with more than two cores, i.e. more than a single compute-unit. MTRRs within a CU are shared so the AP always stays in sync. BUG=b:77457944 TEST=run on Kahlee Change-Id: Idc4cccdf721e252bc87d6cba62a3406a9f19b940 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11soc/intel/common/block/cpu: Fix cpu_get_power_maxMario Scheithauer
To avoid rounding errors with the current data types, the formula in this function must be converted. Change-Id: I75d05165fd9e5a0992330df00f8665a05d2daeb3 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/25584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11soc/intel/common/block/gspi: Set Clock Update Bit for clock updates.Shamile Khan
This is required for clock parameter settings to take effect. BUG=b:75306520 BRANCH=None TEST=On Octopus, used a scope to check that spi_clk fed to tpm is 1 MHz Change-Id: Icdb617aa4aa944d46b3a56dab88d2008b01dea0d Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11Correct "MTTR" to "MTRR"Jonathan Neuschäfer
The term MTRR has been misspelled in a few places. Change-Id: I3e3c11f80de331fa45ae89779f2b8a74a0097c74 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11soc/intel: Remove superfluous pointers variablesArthur Heymans
Change-Id: I639be58df358129c1f420cf8d1540edd408859a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11soc/intel/common: Configure all possible GFX DSM memory reserve rangeSubrata Banik
Intel internal graphics preallocated memory size should be selected from below lists as per Intel FSP UPD header: 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB This patch ensures that coreboot can report the same preallocated memory range for intel grapics during memory layout calculation. Note: Today all existing SoCs(except Cannonlake) are supported under intel common code block design may not need to use any other values than 0x0-0x05 for GFX DSM range. DSM memory ranges between 0xF0-0xF6 are majorly for early SoC samples and validation requirement. This code block to justify all differnet possible ranges that FSP may support for a platform. TEST=Set IgdDvmt50PreAlloc UPD with different ranges between 4MB-60MB and coreboot could able to calculate GFX DSM range accordingly. Change-Id: I99735e9a2ee57626bd9d7258e700f7f39ef02e58 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-10soc/intel/apollolake: fix SPI input clock speedAaron Durbin
On APL and GLK the i2c blocks use 133MHz input clock, but the SPI blocks use a 100MHz input clock. Fix this so that the proper target frequencies can be hit on the SPI controllers. BUG=b:75306520 Change-Id: Iec36579894fa4633ac8d1035e6e7afec01af755f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-10soc/intel/cannonlake: Set Cannonlake I2C clockLijian Zhao
Correct Cannonlake I2C clock frequency to 133Mhz that will match the silicon, Cannonlake have I2C clock force to 133Mhz. BUG=b:75306520 Change-Id: Iaab8851bb00cf27876d4068167a283ed79a28b2d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25610 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10soc/intel/common: prepare for lpss clock splitAaron Durbin
Apparently Intel had decided to use different clock speeds for some of its IP blocks in some of its designs. The i2c designware driver has already been moved into common code allowing for its own Kconfig value. That currently leaves SPI (UART isn't using the clock currently). Therefore, remove SOC_INTEL_COMMON_LPSS_CLOCK_MHZ and add SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ to allow for the different clock speeds present in the system for the various IP blocks. BUG=b:75306520 Change-Id: I6cb8c2de0ff446b6006bc37645fca64f2b70bf17 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25608 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10soc/amd/stoneyridege: Create AP jump structureRichard Spiegel
As part of moving AGESA calls from bootblock to romstage, create infrastructure to pass a pointer to the AP cores, so they can jump directly to romstage. BUG=b:74236170 TEST=Build and boot grunt, actual test will be performed at a later patch. Change-Id: If716d1c1970746f2ad90ef71ae9062c99f219897 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-10soc/amd: Add "halt this AP" callback to romstageRichard Spiegel
As part of moving AGESA calls from bootblock to romstage, callback function AGESA_HALT_THIS_AP must be available at romstage. BUG=b:74236170 TEST=Build and boot grunt, actual test will be performed at a later patch. Change-Id: I0992b2de5856881c19191ec4f637168727686524 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25527 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09soc/intel/apollolake: Fix GPIO group to GPE mapping for GLKHannah Williams
BUG=b:77605178 TEST=Tested EC wake sources Change-Id: Id879b3e91d4c0794662cf3d8204bd077117db23c Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-04-09soc/intel/apollolake: enable MONITOR/MWAIT for GLKCole Nelson
MONITOR/MWAIT had an irremediable hardware bug for Apollolake. This has been fixed for GLK. Therefore, make MONITOR/MWAIT based C-states the default for GLK and disable IO-Redirection based C-states used for Apollolake. Tested on GLK w/kernel 4.14.27 using turbostat to observe C-state residencies with and without load. Tested for S0ix entry and exit using: "echo freeze > /sys/power/state" and "suspend_stress_test -c 500". BUG=b:77639897 Change-Id: If648c25a9b26c04b278dce4af241d439790288ca Signed-off-by: Cole Nelson <colex.nelson@intel.com> Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/19718 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09soc/intel/common: Add funtion to modify PAT & NXE bitNaresh G Solanki
Add function to modify NXE bit & PAT. BUG=None BRANCH=None TEST=Make sure build for Glkrvp is successful. Change-Id: I265d6d5ca538496934a375eb8d99d52879522051 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/25480 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09amd/stoneyridge: Add GNB IOAPIC initMarc Jones
Use standard coreboot function to set virtual wire mode on the GNB IOAPIC. BUG=b:74104946 TEST=Check GNB IOAPIC debug output on serial. Change-Id: I4ff8698419890df1459b1107f0861cf8277a99b0 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-04-09soc/intel/{apl,glk}: Move flush_l1d_to_l2 function to common locationNaresh G Solanki
Move flush_l1d_l2 function to common location within the SoC. BUG=None: BRANCH=None TEST= Build for glkrvp. Change-Id: I4aaaaccc4f343bc4926111258a33e09e79c76141 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/25547 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06fsp_broadwell_de: Provide valid address and size for DCACHE rangeWerner Zeh
On Broadwell-DE the FSP sets up DCACHE in the early call. The address does not match the default FSP 1.0 address defined in src/drivers/intel/fsp1_0/Kconfig which leads to errors when this range is used in pre-ramstage stages. This patch provides the matching DCACHE_RAM_BASE value among with a suitable DCACHE_RAM_SIZE for the FSP based Broadwell-DE implementation. The include order of Kconfig files makes sure that the Kconfig file in the soc directory is sourced first and the defined values will override the ones in src/drivers/intel/fsp1_0/Kconfig. Change-Id: I2a55b576541a3d974ee2714b198095aa24fc46f5 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/25535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-06fsp_broadwell_de: Provide valid ACPI path names for domain and LPCWerner Zeh
Provide ACPI path names for PCI domain and LPC device so that generated ACPI tables have valid device paths. Change-Id: I5a97e45ef50ec5ee9d64c5d2834968a02455cf72 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/25534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-06amd/common/block/pi: Make agesa_heap_base() staticMarshall Dawson
Convert agesa_heap_base() to static since it's unused outside of heapmanager.c. Change-Id: I3ee162985ca1ea36461ea413416d98451a700f8c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-04-06amd/stoneyridge: Use defined value for SPI flash MTRRMarshall Dawson
Replace an absolute value with a #define value in bootblock. This is in preparation for using an additional MTRR in a subsequent patch. Change-Id: I006c7cfa0057b3ed4a21359fc8367caf6ec5baf3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-04-05soc/intel/cannonlake: Add VT-d and VMX programmingLijian Zhao
Add FSP option to enable/disable VT-d (Intel Virtualization Technology for Directed I/O) and VMX (Virtual Machine Extensions), VMX will be disabled once VT-d got disabled. Bug=b:73655383 TEST=Build and flash image on meowth board with debug build FSP, in serial log search for "VMXEnable" and "VtdDiable". Change-Id: I589590450aa4b9302ee2f9bb7b879a332f50b73e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-05soc/intel/cannonlake: Clear EMMC timeout when boot source is not EMMCBora Guvendik
Clear EMMC timeout register to avoid EMMC issue according to cannonlake bios writer guide. _PS0 is not called by kernel when boot source is not EMMC but kernel still initializes emmc. Add _INI to EMMC,SD asl code to cover cases that the system doesn't boot from EMMC. BUG=b:76202699 TEST=Install OS into EMMC Change-Id: I4eef23f637f781b709696951c5bd825530cc1d11 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/25290 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-05mb/amd/gardenia/gpio.c: Convert GPIO to new formatRichard Spiegel
New macros were developed that replace previous way of defining GPIO, with pin and intention very clear while keeping the table mostly identical to previous method (there's no pull up or pull down when a GPIO is set as an output). Change current gardenia table to use the new macros. BUG=b:72875858 TEST=Build Gardenia. Change-Id: I402b95374cc5ba01bb961ebcb34d8e465b443c08 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-05soc/qualcomm/sdm845: Add MMU supportT Michael Turney
Initialize 1st 4GB as Device Memory, except: * 1st page: NULL address * System_IMEM: Cached SRAM * Boot_IMEM: Cached SRAM TEST=build Change-Id: Ic6cf022b08bb2568fdf956cea8bad46da89236c5 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25201 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-05soc/qualcomm/sdm845: remove hole in memlayout.ldT Michael Turney
Removed 33KB hole in SSRAM TEST=build & run Change-Id: I6851860f878d9a0688975fa855980870d657ee1a Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25391 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-05soc/intel/skylake: Generate ACPI DMAR tableNico Huber
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2018-04-05soc/intel/skylake: Enable VT-d and X2APICNico Huber
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX IOMMU and the general IOMMU respectively. These addresses have to be configured in MCHBAR registers (maybe, who knows, the blob is undocu- mented), advertised to FSP and reserved from the OS. The new devicetree option `ignore_vtd` allows to retain the old beha- viour (do whatever pre-set UPD values suggest). We also let FSP set up distinct BDFs for messages originating from the I/O-APIC and the HPET. Change-Id: I77f87c385736615c127143760bbd144f97986b37 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2018-04-03spi: Add helper functions for bit-bangingJulius Werner
Sometimes when bringing up a new board it can take a while until you have all the peripheral drivers ready. For those cases it is nice to be able to bitbang certain protocols so that you can already get further in the boot flow while those drivers are still being worked on. We already have this support for I2C, but it would be nice to have something for SPI as well, since without SPI you're not going to boot very far. This patch adds a couple of helper functions that platforms can use to implement bit-banging SPI with minimal effort. It also adds a proof of concept implementation using the RK3399. Change-Id: Ie3551f51cc9a9f8bf3a47fd5cea6d9c064da8a62 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-03rockchip: Add gpio_set() functionJulius Werner
The <gpio.h> API is supposed to include a gpio_set() function that just toggles the state of a GPIO already configured as an output, even though we rarely need it since gpio_output() can already be used to initialze a GPIO to a default value while configuring it as an output. This function was forgotten on Rockchip, so this patch adds it now. Change-Id: I201288139a2870e71f55a7af0d79d4a460b30a0c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-02src/soc/stoneyridge: Add a check for CMOS failureMartin Roth
BUG=b:77345148 TEST=Pull power from grunt, verify CMOS power failure is detected. Reboot and verify that CMOS power failure is not detected. Change-Id: Idbf0254e197a6d282e618a98bced52ea5a44917f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25468 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-30soc/intel/skylake: Save/restore GMA OpRegion addressMatt DeVillier
Add global/ACPI nvs variables required for IGD OpRegion. Add functions necessary to save the ACPI OpRegion table address in ASLB, and restore table address upon S3 resume. Implementation modeled on existing Baytrail code. Test: boot Windows 10 on google/chell with Tianocore payload and GOP display init, observe display driver loaded and functional, display not black screen when resuming from S3 suspend. Change-Id: Icd6b514e531eec6e49dbb03eb765144f41c1e31b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/25198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-03-30soc/intel/braswell: Save/restore GMA OpRegion addressMatt DeVillier
Add global/ACPI nvs variables required for IGD OpRegion. Add functions necessary to save the ACPI OpRegion table address in ASLB, and restore table address upon S3 resume. Implementation modeled on existing Baytrail code. Test: boot Windows 10 on google/edgar with Tianocore payload and GOP display init, observe display driver loaded and functional, display not black screen when resuming from S3 suspend. Change-Id: I7c1fbf818510949420f70e93ed4780e94e598508 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/25197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>