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2017-01-22soc/intel/skylake: Include I2C code in romstageDuncan Laurie
The lpss_i2c driver is enabled in romstage, so the SOC needs to export the pre-ram compatible I2C controller info, which for skylake is in the bootblock/i2c.c file. This was not causing a compiler error in normal use, but when adding I2C debug code in romstage it failed to compile. With this added, I can now do I2C transactions in romstage. Change-Id: I0778b0497d0b6936df47c29b2ce942c8d90cf39b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18198 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-21soc/intel/apollolake: correct GPIO 13 IRQ numberAaron Durbin
The define for GPIO_13_IRQ had the wrong IRQ number. It should be 0x70 instead of 0x6f. BUG=chrome-os-partner:62085 BRANCH=reef TEST=touch controller doesn't indicate continuous interrupts Change-Id: I3a0726db59fc1eb7736d348aecbf1082719f15b2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18190 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-20soc/intel/skylake: Set FSP-S UPD PchHdaIDispCodecDisconnect to 1Barnali Sarkar
As per Audio PCH team recommendation the iDisplay Audio/SDIN2 should be disabled to bypass InitializeDisplayAudio() function call. Display Audio Codec is HDA-Link Codec, which is not supported in I2S mode BUG=chrome-os-partner:61548 BRANCH=none TEST=Tested to verify that InitializeDisplayAudio() does not get called. Change-Id: Ie0771a8653821e737d10e876313917b4b7c64499 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18091 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-01-19driver/intel/fsp1_1: Fix boot failure for non-verstage caseTeo Boon Tiong
Currently car_stage_entry is defined only in romstage_after_verstage and as a result when SEPARATE_VERSTAGE is not selected, there is no entry point into romstage and romstage will not be started at all. The solution is move out romstage_after_verstage.S from fsp1.1 driver to skylake/romstage. And add CONFIG_PLATFORM_USES_FSP1_1 to fix the build and boot issue with this change. Besides that, rename the romstage_after_verstage to romstage_c_entry in more appropriate naming convention after this fix. Tested on SkyLake Saddle Brook (FSP 1.1) and KabyLake Rvp11 (FSP 2.0), romstage can be started successfully. Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/17976 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-19soc/intel/skylake: Add SATA interrupt for APIC modeSooi, Li Cheng
Add SATA interrupt for APIC mode Change-Id: I9e0682e235715399da2c585174925c89b9116ab3 Signed-off-by: Sooi, Li Cheng <li.cheng.sooi@intel.com> Reviewed-on: https://review.coreboot.org/18130 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-16intel: Fix copy/paste error in license textMarshall Dawson
Change all instances of "wacbmem_entryanty" to "warranty". Change-Id: I113333a85d40a820bd8745efe917181ded2b98bf Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18136 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-14soc/intel/apollolake: Allow USB2 eye pattern configuration in devicetreeKane Chen
This code allows people to override the usb2 eye pattern UPD settings for boards. BUG=chrome-os-partner:61031 BRANCH=None TEST=Usb2 function ok and make sure fsp upd is overridden Change-Id: I5fab620a29aba196edf1f24ffe6a1695de1e523e Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/18060 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13fsp_baytrail: Enable graphic init per defaultWerner Zeh
Baytrail SoC has a bug where in some cases the DisplayPort can hang leading to a non-working display (it just stays black). To avoid this hang, a patch was introduced in 02/2016 (1c3b1112fa - fsp_baytrail: Fix a possible hanging DisplayPort) but per default not switched on so that each mainboard can decide if it wants to use this patch or not. Recently a new case of this bug was reported by Benoit Sansoni (benoit.sansoni@kontron.com) and he requested to enable this fix per default as it costs him a lot of time to find the cause and even the already available fix in coreboot. To avoid this effort for someone else in the future we can enable this fix per default as no negative side effects are known and it is now tested at Siemens and at Kontron on different mainboards with success. As the goal is to enable this code permanently the config switch is not longer needed and is removed. Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/18109 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-13rockchip/rk3288: rtc-rk808: fix rtc time reading issueJeffy Chen
After we set the GET_TIME bit, the rtc time can't be read immediately. We should wait up to 31.25 us, about one cycle of 32khz. Otherwise reading RTC time will return a old time. BUG=chrome-os-partner:61078 BRANCH=veyron TEST=Build and Boot Original-Change-Id: I6ec07fc6c4d6d8b27b12031423b86b8ab15da6f6 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/423272 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Change-Id: I9806b624d6e968e51d52aab8c052ae3fa77f247d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b4b708e29fbae0d8f5a2cece79711aa6b1887727 Original-Change-Id: I8c168c14437bb932a59ac0e91a01062df0cf11dc Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/427522 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18127 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-13soc/intel/skylake: Rename car_stage.S for fsp2_0Teo Boon Tiong
Cosmetic changes to rename car_stage.S to car_stage_fsp20.S, so that it is associated with FSP driver version that is being used. Tested on Kabylake Rvp11. Change-Id: I869df6eb746e3982e5912c272255eab6cb008838 Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/18083 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-12soc/marvell/mvmap2315: Mark mvmap2315_reset() as noreturnMartin Roth
mvmap2315_reset() is called from locations where we're checking for NULL pointers. Because coverity can't tell from the code that the functions are not returning, it's showing errors of accessing pointers after we've determined that they're invalid. Mark it as noreturn, and add a loop in case the reset isn't on the next instruction. This probably isn't needed, but shouldn't hurt. Found-by: Coverity Scan #1362809 Change-Id: If93084629d5c2c8dc232558f2559b78b1ca5de7c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18103 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-123rdparty: update arm-trusted-firmware submoduleMartin Roth
Updated to arm-trusted-firmware TOT: 236c27d2 (Merge pull request #805 from Xilinx/zynqmp/addr_space_size) 183 commits between Sep 20, 2016 and January 10, 2017 - Also add associated change to src/soc/rockship/rk3399 Makefile.inc that is required to build the M0 Firmware. Change-Id: I49695f3287a742cd1fb603b890d124f60788f88f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18024 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-12fsp 1.0 systems: Check for NULL when saving HobListPtrMartin Roth
Die if cbmem_add can't allocate memory for the hob pointer. This shouldn't ever happen, but it's a reasonable check. - fsp_broadwell_de already had a check, but it returned to someplace inside the FSP. Just die instead. Change-Id: Ieef8d6ab81aab0ec3d52b729e34566bb34ee0623 Found-by: Coverity Scan #1291162 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18092 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-01-11skylake: Do not pass VBT to FSP if display init not requiredDuncan Laurie
The FSP 2.0 change broke the logic for determining whether or not to execute the GOP binary. Modify the FSP 2.0 code to do the right thing and check for display_init_required() before passing VBT into FSP and the GOP binary. BUG=chrome-os-partner:61726 TEST=disable developer mode and ensure FSP does not run GOP Change-Id: I7fc8055b6664e0cf231a8de34367406eb049dfe1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18084 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-06nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h>Arthur Heymans
Nothing from that header is used or even declared since CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not selected on Intel hardware. Change-Id: I9101eb6ffa6664a2ab45bc0b247279c916266537 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18044 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2017-01-04soc/intel/quark: Add monotonic timer supportLee Leahy
Add the Kconfig value HAVE_MONOTONIC_TIMER and the routine to read the TSC for the monotonic timer. Simplify the routine to get the TSC frequency. TEST=Build and run on Galileo Gen2 Change-Id: I806fb864b01e39277bf2d6276254b0543930c2f6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18002 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03rockchip/common: Loosen I2C frequency target requirementsJulius Werner
I've recently added an assertion to ensure that the effective I2C frequency on Rockchip SoCs is not too far off the 400KHz target due to divisor rounding errors. A 10KHz margin worked fine for RK3399, but it turns out that RK3288 actually only ever hit 387KHz since its I2C clocks are based off the already pretty low 75MHz PCLKs. While we could probably change the PCLKs to make this closer, that seems like a too intrusive change for something that has already worked just fine for years, so just loosen the restriction a little more instead. BRANCH=None BUG=chromium:675043 TEST=None Change-Id: I7e96a1a75b38f8ad3971dd33046699cceb17b80d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421095 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://review.coreboot.org/18007 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03soc/intel/quark: Add early debugging codeLee Leahy
Add Kconfig values and early debugging code to better segment and debug the early code in bootblock by using the SD LED as an indicator. Update the help text for the debug Kconfig values to point to the various failure locations. TEST=Build and run on Galileo Gen2 Change-Id: I1cd62eba3e9547cb1dd7f547aaec5d4827e14633 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/17985 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03soc/intel/quark: Fix serial port configurationLee Leahy
Fix serial port configuration broken by how PCI configuration space was referenced introduced by change 3d15e10a (MMCONF_SUPPORT: Flip default to enabled). TEST=Build and run on Galileo Gen2 Change-Id: I2ab52cf598795e94f1f16977f8d12b7fdd95e146 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/17984 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-27cpu/intel/common: Add/Use common function to set virtualizationMatt DeVillier
Migrate duplicated enable_vmx() method from multiple CPUs to common folder. Add common virtualization option for CPUs which support it. Note that this changes the default to enable virtualization on CPUs that support it. Change-Id: Ib110bed6c9f5508e3f867dcdc6f341fc50e501d1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17874 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-12-26soc/intel/skylake: set TCC activation by BSP onlySumeet Pawnikar
TCC activation functionality has package scope. It was set for all CPU in the system which is unnecessary. In this patch TCC activation is being set by the BSP only. BUG=chrome-os-partner:59397 BRANCH=None. TEST=Built for skylake platform and verified the TCC activation value before and after S3. Change-Id: Iacf64cbc40871bbec3bede65f196bf292e0149a6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17889 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-23spi: Get rid of SPI_ATOMIC_SEQUENCINGFurquan Shaikh
SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with the ability to perform tx and rx of flash command and response at the same time. Instead of introducing this notion at SPI flash driver layer, clean up the interface to SPI used by flash. Flash uses a command-response kind of communication. Thus, even though SPI is duplex, flash command needs to be sent out on SPI bus and then flash response should be received on the bus. Some specialized x86 flash controllers are capable of handling command and response in a single transaction. In order to support all the varied cases: 1. Add spi_xfer_vector that takes as input a vector of SPI operations and calls back into SPI controller driver to process these operations. 2. In order to accomodate flash command-response model, use two vectors while calling into spi_xfer_vector -- one with dout set to non-NULL(command) and other with din set to non-NULL(response). 3. For specialized SPI flash controllers combine two successive vectors if the transactions look like a command-response pair. 4. Provide helper functions for common cases like supporting only 2 vectors at a time, supporting n vectors at a time, default vector operation to cycle through all SPI op vectors one by one. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17681 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-23soc/intel/skylake: Use the new SPI driver interfaceFurquan Shaikh
1. Define controller for fast SPI. 2. Separate out functions that are specific to SPI and flash controller in different files. BUG=chrome-os-partner:59832 BRANCh=None TEST=Compiles successfully for chell and eve. Change-Id: I2fe0ef937297297339d4ea19dc37d3061caaa80c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR InitBrenton Dong
FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to initialize & tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to ApolloLake SoC when CONFIG_FSP_CAR is enabled. Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without coreboot implementation of CAR init/teardown. Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/17063 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19drivers/spi: fix flash writes at page boundariesAaron Durbin
There was an assumption that all SPI controllers could consume a full page of data to write. However, that assumption doesn't hold when spi_crop_chunk() indicates sizes smaller than page size. If the requested offset isn't page aligned from the start then writes will fail corrupting data since a page boundary isn't honored. The spansion driver needed quite a bit more work to honor the spi_crop_chunk() result. It now mimics the other driver's code. Also, needed to add spi_crop_chunk() to marvell/bg4cd SoC to make google/cosmos build. SPI obviously doesn't work on that platform, but it fixes the build error. Change-Id: I93e24a5a717adcee45a017c164bd960f4592ad50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17910 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-12-16samsung/exynos5420: Fix test for src < 0Patrick Georgi
It was unsigned, not a good place to be for testing < 0. Change-Id: I126fe86422900bbae2c3ca16052be27985cfed53 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1241911 Reviewed-on: https://review.coreboot.org/17888 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-12-16mediatek/mt8173: Check the right set of bits in USB controllerPatrick Georgi
Change-Id: Ic1d1b85a1d7e85b555a93b3a0b55fe310b26e34a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1353362 Reviewed-on: https://review.coreboot.org/17875 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-15soc/intel/common: provide option to invalide MRC cache on recoveryAaron Durbin
Allow a board/platform to invalidate the normal MRC cache when hardware retraining is requested in recovery mode. A small 4 byte payload is used to update the latest data written. It will of course fail on MRC cache retreival on next usage. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: Ic88cd66802664813562d003f50d54e4a4ea375ef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17870 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-15soc/intel/apollolake: don't probe flash manuallyAaron Durbin
Rely on boot_device_spi_flash() to provide the spi_flash object. There's no need to duplicate the probing logic. BUG=chrome-os-partner:56151 BRANCH=reef Change-Id: I91900a3dfad7ba92cbd3b0ace77b08db04cff0b6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17867 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-15soc/intel/common: remove mrc cache assumptionsAaron Durbin
Update the mrc cache implementation to use region_file. Instead of relying on memory-mapped access and pointer arithmetic use the region_devices and region_file to obtain the latest data associated with the region. This removes the need for the nvm wrapper as the region_devices can be used directly. Thus, the library is more generic and can be extended to work on different boot mediums. BUG=chrome-os-partner:56151 Change-Id: Ic14e2d2f7339e50256b4a3a297fc33991861ca44 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17717 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-14soc/intel/broadwell/lpc.c: don't zeroize existing gnvs tableMatt DeVillier
The gnvs table only needs to be zeroized after init; zeroizing an existing/populated table renders all I2C devices completely non-functional. TEST: boot Linux and observe all I2C devices functional Change-Id: Id149ad645dfe5ed999a65d10e786e17585abc477 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17828 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-13rockchip: rk3399: change emmc clk to 148.5MHzZiyuan Xu
Set aclk_emmc and clk_emmc to 148.5MHz under hs400es mode, which could improve stability like kernel. CQ-DEPEND=CL:386527 BUG=chrome-os-partner:54377 BRANCH=none TEST=build and boot on kevin Change-Id: Iaa76d3ec1ab999eb317a9ab6c7e3525594b15b57 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e6eb1f56371aea51f2584a97bf817189d61090b2 Original-Change-Id: If4754d22e83a0f9a029fedca12f26ff5ae8d44e1 Original-Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/386865 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17790 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-13intel MMA: Enable MMA with FSP2.0Pratik Prajapati
- Separate mma code for fsp1.1 and fsp2.0 and restructuring the code - common code is placed in mma.c and mma.h - mma_fsp<ver>.h and fsp<ver>/mma_core.c contains fsp version specific code. - whole MMA feature is guarded by CONFIG_MMA flag. Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/17496 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11x86 SMM: Fix use with RELOCATABLE_RAMSTAGEKyösti Mälkki
The value for _size was not evaluated correctly if ramstage is relocated, make the calculation runtime. While touching it, move symbol declarations to header file. Change-Id: I4402315945771acf1c86a81cac6d43f1fe99a2a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17784 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08soc/intel/apollolake: Move privilege drop to later stageAndrey Petrov
Previously privilege drop was happening "too early" and that caused some PMC IPC programming (performed in FSP) to fail because sideband was already locked out. This change set moves privilege drop to later stage, after last FSP notify call. BRANCH=reef BUG=chrome-os-partner:60657 TEST=iotools rdmsr X 0x121, make sure they can't be read. Also dmesg|grep -i IPC to make sure there are no errors related Change-Id: Ia3a774aee5fbf92805a5c69093bfbd3d7682c3a7 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17769 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08soc/intel/apollolake: Set PL2 in RAPL registerSumeet Pawnikar
This patch sets the package power limit (PL2) value in RAPL register. BUG=chrome-os-partner:60535 TEST=Built, booted on reef and verified PL2 value. Change-Id: I83fe854cf3e9fc92ab87f84b86e64ebb6085065f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17699 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07soc/broadwell: set EM4/EM5 registers based on cdclkMatt DeVillier
The EM4/EM5 registers in the mini-HD audio device must be set based on the GPU cdclk value in order for HDMI audio to function properly. Add variables to save the correct values when initializing the GPU, and accessor functions to retrieve them in order to set the registers when initializing the mini-HD audio device. Change-Id: Icce7d5981f0b2ccb09d3861b28b843a260c8aeba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17718 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-07soc/intel/apollolake: Use the new SPI driver interfaceFurquan Shaikh
1. Define controller for fast SPI. 2. Separate out functions that are specific to SPI and flash controller in different files. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully for reef. Change-Id: If07db9d27bbf4f4eb6024175cb7753c6cf4fb793 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17562 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-07soc/intel/skylake: Remove unwanted spi_release callFurquan Shaikh
Skylake uses a special SPI Flash controller and does not require spi_claim_bus and spi_release_bus functionality. This was a leftover call from earlier cleanup, so remove it. Change-Id: Iea260813cf72b94b7e7c661dbe494a74351dc357 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17729 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07soc/intel/skylake: Remove redundant BootLoaderTolumSize assignmentSubrata Banik
BootLoaderTolumSize FSP-M UPD is already initialized with cbmem_overhead_size() inside driver/fsp2_0/memory_init.c, hence remove the duplicate assignment. Change-Id: I0b1d9769cd2a863bf0547ce5f44928cacc5a63b6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17721 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07soc/mediatek/mt8173: Do not initialize static variables to 0Furquan Shaikh
Change-Id: Ibf0bd772bfdb3bbf6482a0ec9ff90a5c0a8945d2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17765 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Drop redundant loggingKyösti Mälkki
Resource is actually stored even before read_resources, but that's where we currently log this resource. For Intel, use PCI config register offset as the resource index, while AMD side uses MSR address. Change-Id: I6eeef1883c5d1ee5bbcebd1731c0e356af3fd781 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17696 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Consolidate resource registrationKyösti Mälkki
Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17695 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Flip default to enabledKyösti Mälkki
Also remove separate MMCONF_SUPPORT_DEFAULT flag. Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17694 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07PCI ops: MMCONF_SUPPORT_DEFAULT is requiredKyösti Mälkki
Doing PCI config operations via MMIO window by default is a requirement, if supported by the platform. This means chipset or CPU code must enable MMCONF operations early in bootblock already, or before platform-specific romstage entry. Platforms are allowed to have NO_MMCONF_SUPPORT only in the case it is actually not implemented in the silicon. Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06rockchip/rk3399: sdram: use register to calculate sdram sizesLin Huang
We may support different sdram sizes on one board in future, so we need to calculate sdram sizes from sdram drvier. BRANCH=None BUG=None TEST=boot kevin Change-Id: I43e8f164ecdb768c051464b4dbc7d890df8055d0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3c4d8b3cb647b2f9cebc416c298817c16d49330e Original-Change-Id: I95d5ef34de9d79ebca3600dc7a4b9e14449606ff Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/411600 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17629 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06CPU: Declare cpu_phys_address_size() for all archKyösti Mälkki
Resource allocator and 64-bit PCI BARs will need it and PCI use is not really restricted to x86. Change-Id: Ie97f0f73380118f43ec6271aed5617d62a4f5532 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17733 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06PCI ops: Define read-modify-write routines globallyKyösti Mälkki
Change-Id: I7d64f46bb4ec3229879a60159efc8a8408512acd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17690 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: If62537475eb67b7ecf85f2292a2a954a41bc18d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17545 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17529 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06soc/lowrisc: Place CBMEM at top of autodetected RAMJonathan Neuschäfer
Change-Id: I9f169db330d1792128db7a6308ed3afbe5803c03 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17708 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-06soc/marvell/mvmap2315: Fix integer arithmeticJonathan Neuschäfer
Replace logical with bitwise AND operator. Change-Id: I712fab61fbbc833fc2b2575948a875e2f07fd5de Reported-by: Coverity (CID 1362808) Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17401 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-06soc/ucb/riscv: Place CBMEM at top of autodetected RAMJonathan Neuschäfer
Change-Id: Ida016aec11ccdb8da8d2ae1d30ddca16b069be11 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17595 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-06spi_flash: Make a deep copy of spi_slave structureFurquan Shaikh
Commit 36b81af (spi: Pass pointer to spi_slave structure in spi_setup_slave) changes the way spi_setup_slave handles the spi_slave structure. Instead of expecting spi controller drivers to maintain spi_slave structure in CAR_GLOBAL/data section, caller is expected to manage the spi_slave structure. This requires that spi_flash drivers maintain spi_slave structure and flash probe function needs to make a copy of the passed in spi_slave structure. This change fixes the regression on Lenovo X230 and other mainboards. Change-Id: I0ad971eecaf3bfe301e9f95badc043193cc27cab Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17728 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Iru Cai <mytbk920423@gmail.com>
2016-12-05rockchip/rk3399: display: Update edp initialization retryMartin Roth
Follow on patch to clean up the previous retry code. Previous patches: coreboot commit 079b5c65 (rockchip/rk3399: display: Retry edp initialization if it fails) cros commit 28c57a6e (rockchip/rk3399: display: retry edp initialization if edp initial fail) - Reduce the jumping around via goto statements - Break the retry code out into a separate function that also prints the error messages. BRANCH=gru BUG=chrome-os-partner:60150 TEST=Rebuild Kevin and Gru Change-Id: I3b6cf572073e4dcac83da09621bafde179af2613 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17642 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-12-05spi: Define and use spi_ctrlr structureFurquan Shaikh
1. Define a new structure spi_ctrlr that allows platforms to define callbacks for spi operations (claim bus, release bus, transfer). 2. Add a new member (pointer to spi_ctrlr structure) in spi_slave structure which will be initialized by call to spi_setup_slave. 3. Define spi_claim_bus, spi_release_bus and spi_xfer in spi-generic.c which will make appropriate calls to ctrlr functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Icb2326e3aab1e8f4bef53f553f82b3836358c55e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17684 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Pass pointer to spi_slave structure in spi_setup_slaveFurquan Shaikh
For spi_setup_slave, instead of making the platform driver return a pointer to spi_slave structure, pass in a structure pointer that can be filled in by the driver as required. This removes the need for platform drivers to maintain a slave structure in data/CAR section. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ia15a4f88ef4dcfdf616bb1c22261e7cb642a7573 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17683 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Fix parameter types for spi functionsFurquan Shaikh
1. Use size_t instead of unsigned int for bytes_out and bytes_in. 2. Use const attribute for spi_slave structure passed into xfer, claim bus and release bus functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ie70b3520b51c42d750f907892545510c6058f85a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17682 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-04spi_flash: Move spi flash opcodes to spi_flash.hFurquan Shaikh
BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I3b6656923bb312de470da43a23f66f350e1cebc7 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17680 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-03rockchip/rk3399: Fix typoPatrick Georgi
TRAINING, not TARINING. BUG=none BRANCH=none TEST=still builds Change-Id: I8b7ffd0f0544a58865865a8b09d9c153db9c2674 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b1ea846ce1ffd654d7d34c2a1d43b0fddbd4ae32 Original-Change-Id: I4940279ed7217cc20fe29c8b3603d1853acbfc5e Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/411801 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17677 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-02soc/intel/common: Add suppport for Extended VBTAbhay Kumar
With addition of new features in VBT its size got increased more than 6k and was unable to pass using mailbox 4 hence pass using mailbox 3 to kernel. BRANCH=none BUG=chrome-os-partner:60026 TEST=firmware screen and Chrome OS screen should come up. Change-Id: I359cf9bc402881161c9623cada689496716e04a5 Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/17585 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-02soc/intel/apollolake: Drop privilege level to IA_UNTRUSTEDAndrey Petrov
As per guidelines CPU security level should be dropped before OS start, so that certain MSRs are locked out. Drop privilege levels on all logical CPUs. BUG=chrome-os-partner:60454 TEST=iotools rdmsr x 0x120, make sure bit 6 is set, rdmsr x 0x121 results in io error. Change-Id: I67540f6da16f58b822db9160d00b7a5e235188db Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17665 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-02soc/intel/apollolake: Enable ACPI PM timer emulation on all CPUsAndrey Petrov
Currently we enable ACPI PM timer emulation only on BSP. So the timer doesn't work on other cores and that breaks OSes that use it. Also, microcode uses this information to figure out ACPI IO base, and that is used for other features. This patch enables ACPI timer emulation on all the logical CPUs. BUG=chrome-os-partner:60011 TEST=iotools rdmsr x 0x121, x={0..3}, make sure it is set Change-Id: I0d6cb8761c1c25d3a2fcf59a49c1eda9e4ccc70c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17663 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-01lib/nhlt: add support for setting the oem_revisionAaron Durbin
In the ACPI header there's an OEM revision field that was previously just being implicitly set to 0. Allow for a board to provide a non-zero value for this field. Change-Id: Icd40c1c162c2645b3990a6f3361c592706251f82 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17650 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01lib: put romstage_handoff implementation in own compilation unitAaron Durbin
Instead of putting all the functions inline just put the current implementation into a C file. That way all the implementation innards are not exposed. Lastly, fix up the fallout of compilation units not including the headers they actually use. Change-Id: I01fd25d158c0d5016405b73a4d4df3721c281b04 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17648 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01romstage_handoff: add helper to determine resume statusAaron Durbin
Instead of having callers query the romstage handoff resume status by inspecting the object themselves add romstage_handoff_is_resume() so that the same information can be queried easily. Change-Id: I40f3769b7646bf296ee4bc323a9ab1d5e5691e21 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17647 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01romstage_handoff: remove code duplicationAaron Durbin
The same pattern was being used throughout the code base for initializing the romstage handoff structure. Provide a helper function to initialize the structure with the S3 resume state then utilize it at all the existing call sites. Change-Id: I1e9d588ab6b9ace67757387dbb5963ae31ceb252 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17646 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-30soc/intel/skylake: Pass proper CPU flex ratio override to FSPNaresh G Solanki
In bootblock, cpu flex ratio is set to non-turbo max. In FSP UPD, if CpuRatioOverride is zero, then it tries to program cpu ratio to zero. Since it is different than the non-zero value programmed in bootblock, FSP gives reset. To avoid the reset, set FSP UPD for CPU flex ratio override to that value as set in bootblock. Change-Id: I8cae5530ec97cedfbd71771f291db6f55a9fd5c2 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17555 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30soc/intel/skylake: Fix top_of_ram calculationNaresh G Solanki
FSP 2.0 implementation conditionally sets PMRR base based on EnableC6Dram UPD. Therefore, handle the case of the PMRR base not being set since FSP 2.0 changed behavior from FSP 1.1 implementation. If prmrr base is non-zero value, then top_of_ram is prmrr base. If Probeless trace is enabled, then deduct trace memory size from calculated top_of_ram. Change-Id: I2633bf78705e36b241668a313d215d0455fba607 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17554 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30soc/intel/skylake: Use SendVrMbxCmd1 for FSP 2.0Rizwan Qureshi
In FSP 2.0 the UPD to send extra VR Mailbox commands is switched from SendVrMbxCmd to SendVrMbxCmd1. Use the same in silicon initialization. Change-Id: I46bd50c9acc0456e2483f20ccb5e9ec2a0de232a Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/17578 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30soc/skylake: Move IO decode range out from pch_lpc_initTeo Boon Tiong
1. Move existing IO decode range from pch_lpc_init to early stage before SIO init. 2. At the same time, enable SIO decode range (0x2e/0x2f) for platform which use super IO. Change-Id: I72df16d0a784686d8cadfbee09b5aef60576ac43 Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/17337 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30soc/intel/skylake: Remove pad configuration size hardcodingSubrata Banik
Existing GPIO driver inside coreboot use some hardcoded magic number to calculate gpio pad offset. Avoid this kind of hardcoding. Change-Id: I6110435574b141c57f366ccb1fbe9bf49d4dd70a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17571 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30soc/intel/skylake: Disable Legacy PME for Root portsNaresh G Solanki
Legacy PME are enabled by default in FSP UPD region. When Legacy PME is enabled, then an SCI is generated and should be handled by OS and BIOS/Coreboot in collboration. OS requires some ACPI methods (eg _L69) which help to determine the wake source and also to clear some registers. But this infrastructure is not present as of now in coreboot and also linux handles PMEs natively. Hence the SCI was never handled by OS and the status bits were never cleared i.e., PCI_EXP_STS. For this reason the level triggered SCI will remain active and the system will wake up as soon as it enters S3. To fix this, diabled Legacy PME (PmSci for Root ports). Change-Id: I61317eb45305bdb14be3cc1a54fd9961d6ed593e Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17553 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30soc/intel/apollolake: Add save/restore variable MRC cacheAndrey Petrov
Apollolake MRC cache is divided into two regions: constant and variable. Currently they are clubbed together. Since variable data changes across cold reboot it triggers invalidation of the whole cache region. This change declubs the data, adds routines to load/store variable data on flash. BUG=chrome-os-partner:57515 TEST=with patch series applied: cold reboot, make sure MRC is not updated. Do S3 suspend/resume cycle. Change-Id: I374519777abe9b9a1e6cceae5318decd405bb527 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17237 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30soc/intel/common: Add save/restore for variable MRC dataAndrey Petrov
Piggy-back on existing MRC cache infrastructure to store variable MRC data. Only one set of data can be valid at given point of time. Currently this magically happens because region alignment is forced to 0x1000 and region itself is of the same size. This needs to be somehow programmatically enforced. Change-Id: I8a660d356ca760b8ff9907396fb9b34cb16cf1db Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17320 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30driver/intel/fsp2_0: Add version parameter to FSP platform callbackAndrey Petrov
Change-Id: Ibad1ad6bb9eedf2805981623e835db071d54c528 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17497 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-29rockchip/rk3399: display: Retry edp initialization if it failsLin Huang
We found that sometimes the edp doesn't get the edid or that video config fails on kevin after a reboot. Now we will retry 3 times to initialize it if there are errors. BRANCH=gru BUG=chrome-os-partner:60150 TEST=reboot kevin, the edp initialization error is no longer seen. Change-Id: I96e20e526294fbc856fbdffcbd63accdc7371ef6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 28c57a6e5b89c7b3a96204ec19a080067460544a Original-Change-Id: I1382cdf4119fc4eeae5c2b36485030e3a38c2d91 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/412622 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17626 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-29intel/sch: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Forgot to actually "flip the bit" in commit ebc21d1 intel/sch: Switch to MMCONF_SUPPORT_DEFAULT Change-Id: Ic095594acb08bae17a6443bc302eb8bfb1ce2083 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17640 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-28soc/intel/skylake: Add USB Port Over Current (OC) Pin programmingSubrata Banik
Program USB Overcurrent pins as per board schematics definition. BUG=none BRANCH=none TEST=Build and boot kunimitsu from USB device. Change-Id: I6aeb65953c753e09ad639469de7d866a54f42f11 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-28soc/intel/skylake: Initialize UART based on CONFIG_UART_DEBUGTeo Boon Tiong
Current implementation checks for CONFIG_BOOTBLOCK_CONSOLE and then initializes UART. If only CONFIG_BOOTBLOCK_CONSOLE is enabled without enabling CONFIG_UART_DEBUG, there are compilation issues. This is the case when using SIO UART for Skylake DT platform. Hence initialize UART when CONFIG_UART_DEBUG is enabled and not based on CONFIG_BOOTBLOCK_CONSOLE. Also move BOOTBLOCK_CONSOLE out from UART_DEBUG to CPU_SPECIFIC_OPTIONS as part of the fix needed. Change-Id: Id422a55a68d64a06fc874bddca46b0ef5be6d596 Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/17349 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-24soc/mediatek/mt8173/spi.c: Change assert to if statementMartin Roth
Asserts are only fatal if CONFIG_FATAL_ASSERTS is enabled in Kconfig. By default this is disabled, so the assert is generally just a printf. Die if someone decides to pass in an invalid bus number for some reason. Addresses coverity issue 1349858 - Out-of-bounds read Signed-off-by: Martin Roth <martinroth@google.com> Change-Id: I9d79bc336cbbfde31f655cfd271f101e7a90ab1b Reviewed-on: https://review.coreboot.org/17484 Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-24soc/samsung/exynos5420/uart.c: Init new serial struct variablesMartin Roth
The lb_serial structure had some new entries added, which were not being filled in. Fill in the values so they're not undefined. Addresses coverity error 1354778 - Uninitialized scalar variable Change-Id: Ia7ce07f6e4e058c91c2e063f3225497271ef93ff Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17482 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-23soc/intel/skylake: Define early smbus functionsNaresh G Solanki
Define early smbus functions that can be used by mainboard to fetch spd. Change-Id: Id170b2b8e6fb3ebb147f37bf433a27d1162dc11c Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17433 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-22soc/intel: Use correct terminology for SPI flash operationsFurquan Shaikh
FPR is an attribute of the SPI flash component and not of the SPI bus itself. Rename functions, file names and Kconfig option to make sure this is conveyed correctly. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: I9f06f1a8ee28b8c56db64ddd6a19dd9179c54f50 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17560 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22spi: Get rid of flash_programmer_probe in spi_slave structureFurquan Shaikh
flash_programmer_probe is a property of the spi flash driver and does not belong in the spi_slave structure. Thus, make spi_flash_programmer_probe a callback from the spi_flash_probe function. Logic still remains the same as before (order matters): 1. Try spi_flash_programmer_probe without force option 2. Try generic flash probing 3. Try spi_flash_programmer_probe with force option If none of the above steps work, fail probing. Flash controller is expected to honor force option to decide whether to perform specialized probing or to defer to generic probing. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I4163593eea034fa044ec2216e56d0ea3fbc86c7d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17465 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22spi: Get rid of max_transfer_size parameter in spi_slave structureFurquan Shaikh
max_transfer_size is a property of the SPI controller and not of the spi slave. Also, this is used only on one SoC currently. There is no need to handle this at the spi flash layer. This change moves the handling of max_transfer_size to SoC SPI driver and gets rid of the max_transfer_size parameter. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: I19a1d0a83395a58c2bc1614b24518a3220945a60 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17463 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-11-22spi: Clean up SPI flash driver interfaceFurquan Shaikh
RW flag was added to spi_slave structure to get around a requirement on some AMD flash controllers that need to group together all spi volatile operations (write/erase). This rw flag is not a property or attribute of the SPI slave or controller. Thus, instead of saving it in spi_slave structure, clean up the SPI flash driver interface. This allows chipsets/mainboards (that require volatile operations to be grouped) to indicate beginning and end of such grouped operations. New user APIs are added to allow users to perform probe, read, write, erase, volatile group begin and end operations. Callbacks defined in spi_flash structure are expected to be used only by the SPI flash driver. Any chipset that requires grouping of volatile operations can select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and define callbacks for chipset_volatile_group_{begin,end}. spi_claim_bus/spi_release_bus calls have been removed from the SPI flash chip drivers which end up calling do_spi_flash_cmd since it already has required calls for claiming and releasing SPI bus before performing a read/write operation. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17462 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22intel/sch: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Untested, only affected board is iwave/iwRainbowG6. Change-Id: Ie3c40ede85c9f89b54804dd2a411645be93911bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17528 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22Remove explicit select MMCONF_SUPPORTKyösti Mälkki
Make MMCONF_SUPPORT selected with MMCONF_SUPPORT_DEFAULT. Platforms that remain to have explicit MMCONF_SUPPORT are ones that should be converted. Change-Id: Iba8824f46842607fb1508aa7d057f8cbf1cd6397 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17527 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-21fsp2_0: implement stage cache for silicon initBrandon Breitenstein
Stage cache will save ~20ms on S3 resume for apollolake platforms. Implementing the cache in ramstage to save silicon init and reload it on resume. This patch adds passing S3 status to silicon init in order to verify that the wake is from S3 and not for some other reason. This patch also includes changes needed for quark and skylake platforms that require fsp 2.0. BUG=chrome-os-partner:56941 BRANCH=none TEST=built for reef and tested boot and S3 resume path saving 20ms Change-Id: I99dc93c1d7a7d5cf8d8de1aa253a326ec67f05f6 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/17460 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-19soc/intel/common/lpss_i2c: correct bus speed errorAaron Durbin
The wrong value was used for reporting an error when a requested bus speed was made that isn't supported. Use the requested value. Change-Id: I6c92ede3d95590d95a42b40422bab88ea9ae72a1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17474 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-19soc/intel/common/lpss_i2c: fix NULL dereference in error pathAaron Durbin
If the SoC clock speed is not supported there is supposed to be an error printed. However, the value printed was wrong which was dereferencing a NULL struct. Fix that. Change-Id: I5021ad8c1581d1935b39875ffa3aa00b594c537a Found-by: Coverity Scan #1365977 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17468 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-18intel post-car: Increase stacktop alignmentKyösti Mälkki
Align top of stack to 8 bytes, value documented as FSP1.1 requirement. Also fix some cases of uintptr_t casted to unsigned long. Change-Id: I5bbd100eeb673417da205a2c2c3410fef1af61f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17461 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-17rockchip/rk3399: Change 933 DPLL to low jitter rateDerek Basehore
This changes the 933 DPLL rate to 928 which has low jitter. BRANCH=none BUG=chrome-os-partner:57845 TEST=boot kevin and run while true; do sleep 0.1; memtester 500K 1 > /dev/null; done for several hours Change-Id: I4d2a8871aaabe3b0a1a165c788af265c5f9e892c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 54ebf8763bb8193c4b36a5e86f0c625b176d31a6 Original-Change-Id: Iaa12bf67527b6d0e809657c513b8d1c66af25174 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/404550 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17379 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-17rockchip/rk3399: Change PLL configuration to match Linux kernelJulius Werner
The Kevin project has been too smooth and boring for our tastes in the last last few weeks, so we've decided to stir the pot a little bit and reshuffle all our PLL settings at the last minute. The new settings match exactly what the Linux kernel expects on boot, so it doesn't need to reinitialize anything and risk a glitch. Naturally, changing PLL rates will affect child clocks, so this patch changes vop_aclk (192MHz -> 200MHz, 400MHz in the kernel), pmu_pclk (99MHz -> 96.57MHz) and i2c0_src (198MHz -> 338MHz, leading to an effective I2C0 change 399193Hz -> 398584Hz). BRANCH=gru BUG=chrome-os-partner:59139 TEST=Booted Kevin, sanity checking display and beep. Instrumented rockchip_rk3399_pll_set_params() in the kernel and confirmed that GPLL, PPLL and CPLL do not get reinitialized anymore (with additional kernel patch to ignore frac divider when it's not used). Also confirmed that /sys/kernel/debug/clk_summary now shows pclk_pmu_src 96571429 because the kernel doesn't even bother to reinitialize the divisor. Change-Id: Ib44d872a7b7f177fb2e60ccc6992f888835365eb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9b82056037be5a5aebf146784ffb246780013c96 Original-Change-Id: Ie112104035b01166217a8c5b5586972b4d7ca6ec Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/405785 Original-Commit-Ready: Xing Zheng <zhengxing@rock-chips.com> Original-Tested-by: Xing Zheng <zhengxing@rock-chips.com> Original-Reviewed-by: Xing Zheng <zhengxing@rock-chips.com> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/17378 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-17soc/broadcom/cygnus: Update DDR KconfigMartin Roth
The DDR speed Kconfig symbols needed to either be added to the Kconfig tree, or have the code associated with them removed. I chose to add the symbols. - Add symbols for DDR333 - DDR667 to cygnus Kconfig. These should be selected by the mainboard. - Rename symbols from DDRXXX to CYGNUS_DDRXXX to match the existing CYGNUS_DDR800 symbol. - Rename the non Kconfig #define CONFIG_DRAM_FREQ to CYGNUS_DRAM_FREQ because having other #defines look like Kconfig symbols is confusing. - Change #ifdef CONFIG_DDRXXX to use IS_ENABLED Change-Id: I3f5957a595072434c21af0002d57ac49b48b1e43 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17386 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2016-11-17soc/intel/apollolake: Enable and Lock AES feature registerNelson, Cole
Configure MPinit feature register during boot and s3 resume. Enable and Lock Advanced Encryption Standard (AES-NI) feature. BUG=chrome-os-partner:56922 BRANCH=None Change-Id: Id16f62ec4e7463a466c43d67f2b03e07e324fa93 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/17396 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-16intel/fsp_baytrail: Fix assignment of PcdeMMCBootModeDavid Imhoff
Before the PcdeMMCBootMode in the Updatable Product Date was always assigned and didn't take into account the + 1 increment for the default define. Now if the configuration indicates that the device tree should be followed PcdeMMCBootMode is initially disabled. Else if configuration isn't the default, assign the value with the + 1 increment substracted. TEST=Intel/MinnowMax Change-Id: I6755eb585d1afe3a15f83347fba834766eb44ad2 Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl> Reviewed-on: https://review.coreboot.org/10165 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-16intel/fsp_baytrail: Always log PcdEnableLpe and PcdeMMCBootModeDavid Imhoff
Log the values of PcdEnableLpe and PcdeMMCBootMode even if they are outside of the expected range. TEST=Intel/MinnowMax Change-Id: Ie0aea4287234b23d4e9852f3991dcc78ce8103d9 Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl> Reviewed-on: https://review.coreboot.org/10164 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15intel/apollolake: Ensure SPI operations do not cross 256-byte boundaryFurquan Shaikh
BIOS needs to ensure that SPI write does not cross 256-byte boundary. Else, if the write is across 256-byte boundary, then it corrupts the block by wrapping write to start of current block. Thus, ensure nuclear_spi_{read,write} operate within a single 256-byte block only at a time. BUG=chrome-os-partner:59813 BRANCH=None TEST=Verified that elog writes do not corrupt the event log when write is across 256-byte blocks. Change-Id: I854ca2979d65b9f1232f93182cb84d4dee4f4139 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17419 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>