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2017-08-10soc/intel/apollolake: Add file path checkHannah Williams
Fixes Coverity Issue: 1372243 Change-Id: Ib7e43b195357c723e1ae51f609a8b07ad984380a Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/20867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-09intel/common/block/smm: Update smihandler to handle gpiBrandon Breitenstein
Updating the common smihandler to handler gpi events which originally were going to be left to each soc to handle. After some more analysis the gpi handler can also be commonized. Change-Id: I6273fe846587137938bbcffa3a92736b91982574 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/20917 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-09soc/intel/common: smi handler fix comilation errorAaron Durbin
The device_t type is used in smihandler.h, but the header is not including a header which provides that type. Fix that by #includeing <device/device.h> Change-Id: I89af949b088bf569d330f2ea74b1b8ae97e1ed52 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20933 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-09soc/intel/cannonlake: Add ramstage SystemAgent supportLijian Zhao
Revere memory resource within SA, also perform necessary routine for initialization during ramstage. Change-Id: Ibaa7334b0d94fedc87e707a136c9537e2e6f57cb Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20914 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-09common/block/smm: Update SMM common code for io trap handlingBrandon Breitenstein
Add smm common code for io trap handling. This feature is mainly used by big core intel platforms. Commonizing io trap handling will make bring up of big core platforms more seamless. Change-Id: I83bcf22107291ea181b347fac40d57d7ea138de1 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/20848 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-08soc/intel: Remove ACPI notification for fan speed changeSumeet Pawnikar
In _FSL ACPI notification 0x83 was incorrectly being sent to DPTF. When there should be no notification on fan speed change. Change-Id: I66efa7a7feb911a458829a54dbd0afefabd42394 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/20875 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-08soc/intel/apollolake: Use common PMC for apollolakeShaunak Saha
With this patch apollolake uses the common PMC util code.No regression observed on a APL platform. Change-Id: I322a25a8b608d7fe98bec626c6696e723357a9d2 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/19375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-08soc/intel/common: Use common PMC for SMMShaunak Saha
Change-Id: I067b99415e882a24970140280d3b223eb1301e2d Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/20307 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org>
2017-08-08soc/intel/common/block: Add Intel PMC supportShaunak Saha
PMC util code is very similar accross different intel SOC's. This patch is an effort to move those code in common place so that it can be shared accross different intel platforms instead of duplicating for each platform. This patch adds pmclib.c file which contains the pmc utility functions common accross SOC's. The config for common PMC is SOC_INTEL_COMMON_BLOCK_PMC which can be defined in SOC's Kconfig file in order to use the common PMC util code. Change-Id: Ic3d96fc23a98c30e8ea0969a7be09d217eeaa889 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/19349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-08soc/intel/skylake: Log wakes caused by PME on internal bus and PCIE RPNaresh G Solanki
Internal PME is detected when bit PME_B0_STS is set. Following devices causes internal PME. - Integrated LAN - HD Audio/Audio DSP - SATA - XHCI ('USB3') - ME Maskable Host Wake In SPT, PCIEXPWAK_STS bit isn't getting set due to known bug. So scan all PCIe RP for PME status bit & update event log accordingly. BUG=b:36992859 TEST=Build for Soraka, Verify resume due to PME on root port is logged in elog. Change-Id: I879a7c332e62ab598942b29d31bad84619b35ea7 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-07soc/intel/braswell: Fix SPI write after FLOCKDN is setHannah Williams
The SPI controller initialization in finalize_chipset was failing because FSP was setting FLOCKDN before finalize_chipset was called. Hence move finalize_chipset to get called from BS_POST_DEVICE so that it is called before FSP notify function-Ready To Boot state. TEST: run flashrom with -VVV and observe supported opcodes and SPI flash chip are reported correctly, and write/erase operations succeeed. Original-Change-Id: I3c0297f3f2258cf77cf00db367f11ff4d1d9dc77 Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I690fb4bf9e78bb58811c704179ba8b8f25ce95cc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-07soc/intel/cannonlake: Add memory map supportLijian Zhao
Calculate the top of ram from output of Fsp reserved memory range. Change-Id: I0dcc8f737c5811c9010cc4a20ea0126ab3f90f14 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-07usbdebug: Refactor early enableKyösti Mälkki
Always sanity check for EHCI class device and move PCI function power enablement up. Change-Id: I1eebe813fbb420738af2d572178213fc660f392a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-07usbdebug: Consolidate EHCI_BAR setupKyösti Mälkki
There is assumption of static EHCI_BAR_INDEX, try to clean it up by bringing BAR programming at one spot. Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-08-07usbdebug: Remove redundant setupKyösti Mälkki
Taking ownership is handled with DBGP_OWNER within usbdebug driver code. Change-Id: Ia5da10d385cda1b4968f812967ea8a54d7e3c974 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian <david.guckian@intel.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-08-06rockchip: gpio: Correct rk3399 pmu gpio pull settingLin Huang
Starting with RK3399, PMUGPIO pull registers use the same write mask format as normal GRF registers, so they need to use RK_CLRSETBITS() rather than clrsetbits_le32(). BRANCH=None BUG=None TEST=boot from scarlet Change-Id: Ibe391273d58ab35df993e149187d67497fcf2acc Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-06rockchip: gpio: add gpio_pull argument in gpio_input_irq() functionLin Huang
some gpio irq need to set input pull initialization status to guarantee to get the right irq trigger. let's add this argument in gpio_input_irq() function BRANCH=None BUG=None TEST=boot from bob Change-Id: I9b8e6497f07146dafdb447a6ea10d039a2a2fa33 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-04soc/intel/common: Add lpss.c to ramstageFurquan Shaikh
BUG=b:64030366 Change-Id: I7e05d65ebb3b6499451242521ffc61fc4c952830 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-04soc/intel/common: Add Cannonlake pci ids for commonLijian Zhao
Add Cannonlake pci device ids for all the merged intel common code. As of now only have CNL-U and CNL-Y pci ids. Change-Id: Iee5087cdeba53919d83ff665d0c417075279294c Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-08-04soc/amd/stoneyridge: Use generic gpio libraryMarc Jones
Use the genric GPIO library. Add the required functions. Also, update the Kahlee mainboard dependency to match. Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20543 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-03soc/intel/apollolake: Skip disabled IGD deviceSubrata Banik
If IGD PCI device is disabled: 1. BAR for the device will be 0. 2. There is no need to allocate framebuffer for this device. Some early SOCs don't have GFX model fuse by default hence we need to add a check to ensure PCI device is enable. This code to avoid die inside coreboot for missing resources. Change-Id: Ied677e8c77fa7b166b016da458caad0e4702b5d8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03soc/intel/skylake: Skip disabled IGD deviceSubrata Banik
If IGD PCI device is disabled: 1. BAR for the device will be 0. 2. There is no need to allocate framebuffer for this device. Some early SOCs don't have GFX model fuse by default hence we need to add a check to ensure PCI device is enable. This code to avoid die inside coreboot for missing resources. Change-Id: Ic31d3e57ba730f6b569bf2cc3bdc54cb369b8caf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03soc/intel/cannonlake: Sort Kconfig for CannonlakeLijian Zhao
Look and feel update, sort the sequence in Kconfig. Change-Id: I41d99979d9c7d081086aac8bfef27186b37a6e70 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03soc/intel/braswell/Kconfig: select RELOCATABLE_RAMSTAGEMatt DeVillier
Without RELOCATABLE_RAMSTAGE selected, S3 resume will hang under Linux and Windows. All other Intel SoCs have this selected by default, so this change simply corrects an omission on Braswell. TEST: boot Linux on google/cyan with and without RELOCATABLE_RAMSTAGE selected; observe that S3 resume fails without and succeeds with. Change-Id: I9071d9b4e3e3a156281d95fae059947c4c26f744 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02soc/nvidia/tegra*: force using our headers instead of compiler's/system'sPatrick Georgi
The code doesn't include much, but when compiled outside the coreboot build (what the shipped Makefile is made for), we want to make sure that the few files it includes are controlled by us. TEST=`cd src/soc/nvidia/tegra124/lp0; make CC=arm-eabi-gcc` works Change-Id: Ic2f1e4aa4047617b048ef7ef98d71f9d540ccd74 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20860 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-01soc/dmp/vortex86: Fix CMOS read and random RTC resetMartin Roth
The array of CMOS values that was passed into the read routine was never getting updated. GCC 7.1 gives a warning on this: error: may be used uninitialized in this function Change-Id: I2f7c9b6455761a38598467b001efb0603fd14c32 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-31soc/amd/stoneyridge: Add GPIO functions to romstageMarc Jones
A mainboard may access GPIO in romstage. Change-Id: Id380c6570943ce2a0bf6112d62cc91aeae283fcf Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31soc/amd/stoneyridge: Fix GPIO bank1 control definitionMarshall Dawson
Change-Id: Ia6c7357ba0c581dc46d173f462efce181847a4e1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20526 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31soc/amd/stoneyridge: Move ACPI MADT table to socMarc Jones
Move the mainboard MADT tables to generic soc ACPI code. Change-Id: I49fb55b1315da8fe65421b43fc4312ed588d5ecb Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20277 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31soc/amd/stoneyridge: Add GNVSMarc Jones
Add ACPI asl for global non-volatile storage (GNVS). Change-Id: I9ecab92181bfe60e7b6c6e91ffb9fa843345352f Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/20275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28soc/intel/apollolake: Add CNVI and PCIE IRQs for GLKHannah Williams
Change-Id: I0387ccf6970e6169cbebd232ae210731338d0900 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/20755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28soc/intel/skylake: Remove incorrect ME PG-status printBarnali Sarkar
As per discussion with CSME team, ME is NOT using PCI Config Space register HFSTS2 Bit 10 to update ME power-gated status. ME goes to CM0-PG state after ME device becomes idle after Bit 2 of MMIO register offset 0x800 (D0i3 Control - HECI1_D0I3C) is being set. And to retrieve the PG status of ME, one should read from the PWRMBASE+offset 0x590 (which should give the value 0xF9) and PWRMBASE+offset 0x594 (which should give the value 0xFF). But, also it needs some time for the ME FW to go to idle state and reflect these values in PWRMBASE registers after D0i3 bit is being set. This does not happen instantly. So, in coreboot, if we read the ME PG state in finalize.c, which happens just after FSP Notify phase, where actually ME D0i3 bit is set, we do not read the correct PG state values (i.e, 0xF9 and 0xFF). But, once it boots to Kernel, if we read those same registers through iotool mmio_read32 command, we get correct values. So, removing the ME PG state prints from coreboot, since it is actually showing wrong information, although ME Power Gating is successful. Change-Id: Idd31a9803b4c9db7d4bb8bbec5374583a8df0c41 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27soc/amd/stoneyridge: Remove unused SD controllerMarshall Dawson
Remove the unused support code from the old multi-device hudson SD controller. The binaryPI blob contains the correct steps for setting up SD and the public BKDG doesn't completely document the controller. The sd.c file was using device IDs not associated with the Stoney Ridge APU. The hudson_enable() code removed was also looking for incorrect device IDs and the PM_MANUAL_RESET register doesn't behave as the source indicates. The SD default settings may be overridden. Future improvements may include a few Kconfig options and a weak call to the mainboard for overriding additional defaults. BUG=chrome-os-partner:62580062 Change-Id: I7dbd70320740e8a05e6bf16af125d67012f20674 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27soc/amd/stoneyridge: Enable verstage supportMarshall Dawson
Add Kconfig selects for vboot and update the makefile to pick up files to be used in verstage. Change-Id: If5c439a330d687156006aec2ebaea18ff2c96b3e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19756 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCKMarshall Dawson
Add dedicated CAR setup and teardown functions and Kconfig options to force their inclusion into the build. The .S files are mostly duplicated code from the old cache_as_ram.inc file. The .S files use global proc names in anticipation for use with the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE. Move the mainboard romstage functionality into the soc directory and change the function name to be compatible with the call from assembly_entry.S. Drop the BIST check like other devices. Move InitReset and InitEarly to bootblock. These AGESA entry points set some default settings, and release/recapture the AP cores. There are currently some early dependencies on InitReset. Future work should include: * Pull the necessary functionality from InitReset into bootblock * Move InitReset and InitEarly to car_stage_entry() and out of bootblock - Add a mechanism for the BSP to give the APs an address to call and skip most of bootblock and verstage (when available) (1) - Reunify BiosCallOuts.c and OemCustomize.c (1) During the InitReset call, the BSP enables the APs by setting core enable bits in F18F0x1DC and APs begin fetching/executing from the reset vector. The BSP waits for all APs to also reach InitReset, where they enter an endless loop. The BSP sends a command to them to execute a HLT instruction and the BSP eventually returns from InitReset. The goal would be to preserve this process but prevent APs from rerunning early code. Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-27soc/amd/stoneyridge: Convert 48Mhz enable to read/write32Marshall Dawson
Use the appropriate read32() and write32() calls. Remove unnecessary cast. Change-Id: Ib5430bdb30844d3508a09ddb77a969c0628f6c7d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-27soc/amd/stoneyridge: Clarify BAR mask in SPI baseMarshall Dawson
The format of the D14F3xA0 SPI Base_Addr register is different than a traditional BAR. Change the function to preserve any enables already in place. Change the AND mask to remove the reserved field and the enables. Change-Id: I9a43c029a2e1576703ce9cdc787d18658e9190a5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-27soc/intel/cannonlake: Correct gpio definitionLijian Zhao
The following changes have been applied for GPIO: 1. Correct port id using by GPIO community 3 for CNL-LP. 2. Correct number of doubleword for each pad from 2 to 4. Change-Id: I717d1ffba8e6722543f4cf8083fe6145fa85e184 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-27soc/intel/apollolake: Make usage of RAPL selectableMario Scheithauer
Apollo Lake SoC supports configuration of Running Average Power Limits (RAPL) for package domain. This feature is not required for all APL mainboards. According to the APL SoC EDS Vol 4 chapter 18.4 Power Limiting Control it is not necessary to enable the RAPL algorithm per default. For that reason make the RAPL configuration selectable. Change-Id: Ib737b162f72b76c15e5768859f9099e2e7ef6426 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27soc/intel/skylake/igd.c: check return value of init_igd_opregionMartin Kepplinger
init_igd_opregion itself is supposed to return cb_err so this adds error handling, just like other implentations of write_acpi_tables do it. this had been found by coverity: *** CID 1378270: Error handling issues (CHECKED_RETURN) /src/soc/intel/skylake/igd.c: 147 in write_acpi_igd_opregion() 141 /* If IGD is disabled, exit here */ 142 if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF) 143 return current; 144 145 printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); 146 opregion = (igd_opregion_t *)current; CID 1378270: Error handling issues (CHECKED_RETURN) Calling "init_igd_opregion" without checking return value (as is done elsewhere 5 out of 6 times). 147 init_igd_opregion(opregion); 148 update_igd_opregion(opregion); 149 current += sizeof(igd_opregion_t); 150 current = acpi_align_current(current); TEST=Built Change-Id: If6f5d53037f093607d89cfe8faf193d55de7f6c4 Found-by: Coverity (CID 1378270: Error handling issues (CHECKED_RETURN)) Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/20766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-07-26soc/intel/skylake/chip.h: Provide enum values for SataModeNico Huber
The values were verified to be correct with the KabylakeFsp0001 from github. Skylake FSP documentation disagrees so YMMV. Change-Id: I1ee04dbbed48d5376dbc24ae70753b059f2646eb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20765 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-26soc/intel/apollolake: Update memory HOB info save functionRavi Sarawadi
SMBIOS memory HOB produced by glk FSP v52_27 has new structure members, which are not available in current apl FSP. New FSP-m header file in https://review.coreboot.org/#/c/20673/ lists new SMBIOS structure members. Break memory HOB save routine into different functions for glk and apl to accomodate new changes. Change-Id: I33c6e4f2842cebbb326b6a05436fa69e3836ffc6 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20674 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-26intel/common/block/itss: Extend itss_irq_init() to handle IOSF 1.0Werner Zeh
Current implementation of itss_irq_init() uses 8 bit write access to IRQ routing registers which is not supported on Apollo Lake. This commit moves the register access from 8 bit to 32 bit so that this function can be used with every platform. Change-Id: I15c3c33a16329fd57f0ad7f99d720adbf300d094 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-25soc/intel/skylake: Add IGD id for mobile Xeon with GT2Nico Huber
Change-Id: I2cd210dd0443b854294ce7ee8e267594e3ea1780 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20651 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-07-25soc/intel/skylake: soc/intel/skylake: Initialize struct member to 0Subrata Banik
As per GCC 7.1 compiler struct reset_reply is considered as uninitialized inside send_heci_reset_message function. Change-Id: Ide53a9267dfba1a00263ada1d7016a48ecb9aad8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-25soc/intel/skylake: Skip Spi Flash Lockdown from FSPBarnali Sarkar
coreboot was setting SPI FPR register to protect the mrc_cache data range stored in flash. This programming was being done after FSP Notify 1. But, FSP was locking the SPI by setting FLOCKDN Bit during Notify phase 1, due to which coreboot was unable to protect that range. As solution, FSP introduced a new UPD SpiFlashCfgLockDown to skip the lockdown of flash on interest of bootloader. Set that UPD to 0 to skip the lockdown of FAST_SPI flash from FSP. The same is being done from coreboot after end of Post at finalize.c file. BUG=b:63049493 BRANCH=none TEST=FPR can be set properly to protect the mrc_cache range. The issue reported in the bug doesn't come when both software and hardware WP is enabled with this patch. Change-Id: I3ffca2f1b05ab2e4ef631275ef7c3a6e23e393aa Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-25soc/intel/common/block: Modify fast_spi_lock_bar functionBarnali Sarkar
Use 16bit write to avoid touching the upper two bytes that may cause write cycle to fail in case a prior transaction has not completed. This function sets the WRSDIS(Bit 11) and FLOCKDN (Bit 15) of the SPIBAR + BIOS_HSFSTS_CTL. While WRSDIS is lockable with FLOCKDN, writing both in the same cycle is guaranteed to work by design. Avoid read->modify->write operation not to clear the RW1C bits unintentionally. Change-Id: Ia7880aaca0ed64150c994d49786a0a008bbaa98b Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-24soc/intel/common/block: Add max SPI transaction time-out as 5 secBarnali Sarkar
Earlier 15ms time-out was kept for SPI transactions which was not enough for SPI Erase transactions. Increase the max time-out time to 5 secs which was present in SKL before common code. This increase in time-out won't disturb other SPI transactions like Read, Write or Read Status, since, for those it will come out of the loop once FDONE bit or FCERR bit is set. BUG=b:63959637 BRANCH=none TEST=Built and booted poppy and all SPI transactions succeeded. Change-Id: I1c015d80b33677de11755fb2097373631d1fa8c4 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-24soc/intel/skylake: Use common opregion implementationPatrick Rudolph
Enable SOC_INTEL_COMMON_GFX_OPREGION for all FSP versions. Allows to get rid of opregion.c, as it's no longer needed. Change-Id: I39190488e12917a09dbf7ee3947a33940ebc290b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-07-24Update files with no newline at the endMartin Roth
Change-Id: I8febb8d74e2463622cab0313c543ceebec71fdf4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-24Fix files with multiple newlines at the end.Martin Roth
Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20704 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-22soc/intel/cannonlake: Keep variable from going out of scopeMartin Roth
The variable p was going out of scope while still being pointed to by *cpu_name. Fix coverity ID 1378215 (Pointer to local outside scope) Change-Id: I6ad7b1919104b4d97869efe5065e39c2a43de638 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2017-07-21Revert "soc/intel/cannonlake: Add postcar stage support"Martin Roth
This reverts commit 399c022a8c6cba7ad6d75fdf377a690395877611. This was merged too early. I'll repost it. Change-Id: Iabac0aaa0a16404c885875137cf34bf64bf956f7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20686 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-21Revert "soc/intel/cannonlake: Call into FSP siliconinit"Martin Roth
This reverts commit dbe7f893c0e3fffc4e9862d872d65df752feaf9d. This was merged too early. I'll repost it. Change-Id: Ife56f45e91c0b961d0fad0e1872c6df3f9e18973 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20685 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-21soc/intel/apollolake: Add pci device id for GLK IGDHannah Williams
Change-Id: Id2c94afed8976687524a0913ea1c13aeddd98333 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/20654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-21soc/intel/cannonlake: Call into FSP siliconinitLijian Zhao
The following changes can make system call into FSP siliconinit and exit from that until payloads. 1. Add frame to call fspsinit. 2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit. Change-Id: I1c9c35ececf3c28d7a024f10a5d326700cc8ac49 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21soc/intel/cannonlake: Add postcar stage supportLijian Zhao
Initialize postcar frame once finish FSP memoryinit Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21soc/intel/skylake: Perform LPC offset read after lockdown operationSubrata Banik
This patch is to provide an additional read LPC pci offset register BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is successful. Change-Id: I308c0622d348fc96c410a04ab4081bb6af98e874 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21common/block/fast_spi: Perform SPI offset read after lock down operationSubrata Banik
This patch is to provide an additional read SPI pci offset register BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is successful. Change-Id: I3b36c1a51ac059227631a04eb62b9a6807ed37b1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21soc/intel/skylake: Rectify LPC Lock Enable (LE) bit definitionSubrata Banik
LPC pci config register BIOS Control (BC) - offset 0xDC bit 1 is for Lock Down. Change-Id: I838dd946b8cdb7114f58ccc5d02159f241f0bad0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21soc/intel/apollolake: Bring in delta for GLK SOCHannah Williams
Change-Id: I3e76726bb77f0277ab5776ae9d3d42b7eb389fe3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/19603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-20soc/intel/cannonlake: Make ramstage relocatableLijian Zhao
Relocate ramstage into CBMEM. Change-Id: I0543d25d722c5872f4f139a98e5125a41cc40653 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-20soc/intel/common/gpio: add helpers for relative pin calcuationsAaron Durbin
The gpio numbers are global, but they have their respective place within each community and the group within their community. For all the calculations open coding this calculation convert them to use the helpers. Change-Id: I0423490ae1740ef59225a70fea80a7d91ac2a39a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-20soc/intel/common/gpio: fix gpi_status_get()Aaron Durbin
A pad number is passed into gpi_status_get() to determine if its associated bit is set from a generated event. However, the implementation wasn't taking into account the gpi_status_offset which dictates the starting offset for each community. Additionally, the max_pads_per_group field is per community as well -- not global. Fix the code to properly take into account the community's gpi_status_offset as well as the max_pads_per_group. Change-Id: Ia18ac6cbac31e3da3ae0ce3764ac33aa9286ac63 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20652 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2017-07-20soc/intel/skylake: Remove dead `CONFIG_PRE_GRAPHICS_DELAY`Nico Huber
`CONFIG_PRE_GRAPHICS_DELAY` was only applied on a dead code path in `igd.c` that is guarded by always selected `CONFIG_ADD_VBT_DATA_FILE`. Nobody missed it for nearly a year, plus, it's not applied on the GOP path, let's drop it. Change-Id: I0b70cce3a3f2b50cb4e72c4d927b35510ff362a2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-20soc/intel/skylake/igd: Remove dead quirk from dead code pathNico Huber
This quirk was superseded a view lines above. Also the whole path is guarded by `CONFIG_ADD_VBT_DATA_FILE` which is always selected for nearly a year now. Change-Id: I7fc5184d6e81e4588616e0302dee410e74bdab5a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-07-20soc/intel/skylake: Fix broken memory info HOB scanningNico Huber
It looks like this code was written with completely different semantics in mind. Controllers, channels and DIMMs are all presented in their phy- sical order (i.e. gaps are not closed). So we have to look at the whole structure and not only the first n respective entries. Change-Id: I8a9039f73f1befdd09c1fc8e17cd3f6e08e0cd47 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20650 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-20soc/intel/common/smbios: Amend debug messageNico Huber
Change-Id: I6fcee760eb32b797430eb363ce0202557b74a126 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20649 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-20intel/common/block/i2c: Fix clock programming of i2cNaresh G Solanki
When configuring i2c frequency to I2C_SPEED_FAST_PLUS, observed frequency was I2C_SPEED_FAST. This was due to incorrect register programming. TEST= Build for Soraka, I2C frequency during firmware execution was I2C_SPEED_FAST_PLUS when configured for I2C_SPEED_FAST_PLUS. Change-Id: Ib0e08afe0e1b6d8c9961d5e3039b07ada9d30aa3 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-20soc/intel/apollolake: Implement _PIC method into ACPIMario Scheithauer
The _PIC method is called by the OS to choose between interrupt routing via the i8259 interrupt controller or the APIC. Change-Id: I2bc16f9c096c095c02de3692e76c0906cec54cb5 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-19soc/intel/cannonlake: Add minimal changes to call FSP MemoryinitLijian Zhao
The following minimal changes are needed to make system boot until FSP memoryinit got called. 1. Program SA BARs 2. Assume previous power state is S0. Change-Id: Iab96b27d4220acf4089b901bca28018eaba940a1 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-19rockchip/rk3399: Adjust gpio_t format to match ARM TFJulius Werner
Our structure packing for Rockchip's gpio_t was chosen arbitrarily. ARM Trusted Firmware has since become a thing and chosen a slightly different way to represent GPIOs in a 32-bit word. Let's align our format to them so we don't need to remember to convert the values every time we pass them through. CQ-DEPEND=CL:572228 Change-Id: I9ce33da28ee8a34d2d944bee010d8bfc06fe879b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/20586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-19soc/intel/cannonlake: Add microcode supportLijian Zhao
Microcode needs to be loaded prior to FSP initialization. Change-Id: Idd70bd3e6555866d9bb232e8904aed4120c79fe7 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20484 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-18vboot: Remove get_sw_write_protect_state callbackJulius Werner
We've just decided to remove the only known use of the VBSD_SW_WP flag in vboot (https://chromium-review.googlesource.com/c/575389), since it was unused and never reliable on all platforms anyway. Therefore, we can now also remove the coreboot infrastructure that supported it. It doesn't really hurt anyone, but removing it saves a small bit of effort for future platforms. Change-Id: I6706eba2761a73482e03f3bf46343cf1d84f154b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/20628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-18soc/intel/skylake: Enable SMBus based on mainboard configNaresh G Solanki
Enable SMBus controller based on config in mainboard devicetree.cb BUG=None TEST= Build for Soraka, Verify that SMBus is enabled or disabled (run lspci in OS) based on board devicetree.cb config 'SmbusEnable'. Change-Id: I04c8bc30c03fd8dc7cc8ae239885e740b09e9bc1 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-07-18soc/intel: Fix SPI driver compilation with CONFIG_DEBUG_SPIStefan Reinauer
write[8|16|32] wants volatile pointers, not const pointers. Change-Id: I92010516e8e01c870b60107e20a576a75d491e4e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13566 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-18soc/intel/cannonlake: Fix Build breakLijian Zhao
1.Replace outdated defination of TCO_EN to TCO_BASE_EN 2.Remove setmaxfreq() as not needed any more. Change-Id: Id54fdfd14f1abaa592132195e6f9acfa5807626e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-18soc/intel/cannonlake: Use common GPIO driverAndrey Petrov
Change-Id: I0bbdd641244f0c7baaa2146dcfde6431bde387c5 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-18soc/intel/skylake: Remove Heci2 and Heci3 from wake resource listSubrata Banik
HECI2 and HECI3 devices are “function disable” during FSP Silicon Init phase. Device will not be visible over PCI bus hence removing these devices from wake source list. Change-Id: I0de665e039d74e49e5a22db9714bc9fee734e681 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-18soc/intel/cannonlake: Add PMC headersAndrey Petrov
Add register definitions used in PMC block. Change-Id: I963f402a59d49dfc7b76224f719a315e1cc6dc74 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20071 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-17soc/intel/common/gpio: clean up logical to chipset mappingAaron Durbin
1. Explicitly add LOGICAL to the reset macro name to make it explicit that the values are logical. 2. Reword some of the comments and combine them into single comment instead of scattering the comments throughout. 3. Use c99 struct initializers for the reset mapping array. 4. For the chipset specific values use literals that match the hardware. 5. Use 'U' suffixes on the literals so we don't trip up compiler being over zealous on undefined behavior. 6. Use unsigned and fixed-width types for the reset mapping structure since the code is reliant on matching up with a register definition. 7. Fix formatting that can fit < 80 cols. Change-Id: Iaa23a319832c05b8a023f6e45c4ee5ac06dd7066 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-17soc/intel/common/gpio: distingiush single vs multi acpi devicesAaron Durbin
Sadly, small core and big core are not aligned with the OS driver's expectation on the number of ACPI devices used for each community. Big core uses a single device while small cores use one ACPI device per community. Allow for this distinction within the common gpio implementation and ensure apollolake is utilizing the new option to retain the correct behavior. Change-Id: I7c7535c36221139ad6c9adde2df10b80eb5c596a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20588 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-07-17soc/intel/skylake: remove top_of_32bit_ram() declarationAaron Durbin
It should never be globally exposed. Remove the global symbol and make it static. Change-Id: I3b85f3bbf6a73d480cdefdcdec26e137e3a3f75f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-07-17soc/intel/cannonlake: remove top_of_32bit_ram() declarationAaron Durbin
It should never be globally exposed. Remove it. Change-Id: I90e201ddd4df2cda89e7d3e4cb81bdc2a81cac83 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-16soc/amd/stoneyridge:Fix IS_ENABLED() around Kconfig symbol referencesMartin Roth
- Update files that were added since the IS_ENABLED() fix patches - Remove extra XHCI controller. Change-Id: I7028942ce54b06cd048029f7b93f064beba579ad Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-16src/soc: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: I2e7b756296e861e08cea846297f687a880daaf45 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-14soc/intel/skylake: Set PsysPL2 MSRShelley Chen
BUG=b:7473486, b:35775024 BRANCH=None TEST=On bootup make sure PL2 and PsysPL2 values set properly (through debug output) Change-Id: I847a8458382e7db1689b426f32ff2dcbc5a0899c Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/20418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-13soc/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: I3c5f9e0d3d1efdd83442ce724043729c8648ea64 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-13soc/intel/cannonlake: Add reset.cAndrey Petrov
Add reset functionality. This implementation relies on CSE to trigger global reset. Change-Id: I7e6ae07a48f1cdc3d2f4cdb74246627d27253adf Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13soc/intel/cannonlake: Add MakefileAndrey Petrov
This enables building working bootblock and non-functional romstage and ramstage. Change-Id: I580cd2c3279d742f202b2adfbe55c814cfb48f99 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13soc/intel/cannonlake: Add bootblock PCHAndrey Petrov
Add essential initialization needed for PCH in bootblock. Change-Id: I3694e099e78c2989f7192c550cbba098e5df2032 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13soc/intel/cannonlake: Add early CPU initializationAndrey Petrov
Add basic CPU initialization for bootblock, as well as relevant headers. Change-Id: I318b7ea0f3aa5b5d28bf70784ccd20f2fe28cd86 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13soc/intel/skylake: reduce postcar stack usage for fsp 2.0Aaron Durbin
The FSP 2.0 path uses postcar to decompress ramstage. Since postcar is entirely RAM based there's no need to have an excessively large stack for the lzma decompression buffer. Therefore, reduce the stack required to 1 KiB like apollolake. Change-Id: I45e5c283f8ae87e701c94d6a123463dddde3f221 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-12soc/intel/cannonlake: Add PCI dev macros and IDsAndrey Petrov
Change-Id: I287404f1615c6c0b441dd1b98a40e79919920a02 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-12soc/intel/cannonlake: Add report_platform.cAndrey Petrov
Dump basic platform information early in bootblock. Change-Id: I12d1c9dd9f0518c133de465a4db72a0664a94eef Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20068 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-12soc/amd/stoneyridge: Update header guards and includesMarshall Dawson
Rename the guard to better match the new directory structure. Add include files containing typedefs used in the file. Change-Id: I5fe23ce6994603b0ace99fd6ffc5f3eded2880af Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20525 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-12soc/intel/skylake: Remove “disable SaGv” in recovery mode flowSubrata Banik
This reverts commit 5535cead (intel/skylake: Disable SaGv in recovery mode). Commit 5535cead disables SaGv in recovery mode to save few seconds booting time as we were doing memory training on every recovery flow. Now we don't need to perform MRC training on every recovery boot due to RECOVERY_MRC_CACHE implementation in place. Hence we don't need to define different SaGv policy between Normal (developer) mode and recovery mode to save few seconds. Using different SaGv parameters between recovery and all other mode has some significent drawbacks over warm reboot cycle. We are seeing a MRC traning hang in eve/soraka/poppy devices with below use case. Step 1: Boot system in developer mode (first time RW_MRC training) Step 2: Set recovery_request=1 (using crossystem) and issue “reboot” from OS Step 3: System will perform recovery mode MRC training and boot to OS (first time RECOVERY_MRC training) Step 4: Issue “reboot” from OS console. Step 5: System wil boot in developer mode (using RW_MRC cache) Step 6: Set recovery_request=1 (using crossystem) and issue “reboot” from OS Step 7: System will pick RECOVERY_MRC_CACHE and will hang during MRC training. This patch fixes issue mentioned above and ensures system boot to OS without any hang if we change mode (dev<->recovery) over warm reset. BUG=b:63515071 BRANCH=none TEST=manual stress testing of dev<->recovery mode over warm boot. No MRC hang with this fix on eve/soraka/poppy devices. Change-Id: I8d094a8b6d78ea3bf8f929870a4a179495c29c78 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-12Revert "soc/intel/skylake: storage: Add 2ms delay before exiting D3"Subrata Banik
Don't need this additional 2ms delay as PCR read after sideband write help to fix original hard hang issue. This reverts commit d4b6ac19b0a6619ebe645875282643cc50cf7a3e. Change-Id: I4232cba5b92e17f728795f7c282af6161e385e9b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-12soc/intel/skylake: Perform PCR read after all PCR writeSubrata Banik
BIOS must ensure to read same PCR offset after PCR write operation is done. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<->D3 transition on eve failing unit. No hard hang with this fix. Change-Id: Id3d567aab517b16ff99a526fc29c2d71bf4042d0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 05:53:17 +0000