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Add support for UART driver in coreboot.
TEST=build & run
Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f
Signed-off-by: Prudhvi Yarlagadda<pyarlaga@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29964
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The code in cpu/intel/car/romstage.c Does most of the things like
setting up timestamps, stack guards, entering postcar.
A functional difference is that the FSP header is searched for twice
instead of passed from the CAR entry to the C code. When using
C_ENVIRONMENT_BOOTBLOCK this needs to be done anyway (or a special
linker symbol kept across multiple stages is needed, which is likely
not worth the speedup).
Change-Id: I0f03e5a808f00157fdd807b104417a54e4bde7b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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FDT property data should not be const -- sometimes we need to update it,
for example when fixing up phandles in an overlay. On the other hand
it's occasionally desirable to put a string constant in there without
having to strdup() it all the time... let's just live with the tiny
implicit assumption that the data we'd want to modify (phandle
references, mostly) will never be added from string constants, and put a
cast in dt_add_string_prop().
Change-Id: Ifac103fcff0520cc427ab9a2aa141c65e12507ac
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32868
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently DT paths are *not* expected to start with '/'. This is not
what the spec says (see Devicetree Specification v0.2, 2.2.3 Path Names)
and also not what is done by Linux.
Change dt_find_node_by_path() to expect paths to start with '/' and add
a leading '/' to all DT path strings. Besides the compatibility with the
spec this change is also needed to support aliases in the future.
This patch was adapted from depthcharge's http://crosreview.com/1252770
Change-Id: Ibdf59ccbb4ead38c6193b630642fd1f1e847dd89
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32865
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Besides looking up a node with an absolute path dt_find_node_by_path()
currently also supports finding a sub-node of a non-root node. All
callers of the function pass the root node though, so it seems there
is no real need for this functionality. Also it is planned to support
DT path names with aliases, which would become messy in combination with
the lookup from a sub-node.
Change the interface of dt_find_node_by_path() to receive the DT tree
object instead of a parent node and adapt all callers accordingly.
This patch was adapted from depthcharge's http://crosreview.com/1252769
Change-Id: Iff56be4da2461ae73a7301dcaa315758d2a8c999
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32864
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch caches phandles when unflattening the device tree, so we
don't have to look up the phandle property again every time we're trying
to find the phandle of a node. This is especially important when
supporting phandle lookups, which are also added. In addition we keep
track of the highest phandle in the whole tree, which will be important
for applying overlays later.
With this, dt_get_phandle(node) becomes obsolete because the phandle is
already available as a member variable in the node.
This patch was adapted from depthcharge's http://crosreview.com/1536385
Change-Id: I9cbd67d1d13e57c25d068b3db18bb75c709d7ebe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32863
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With the recent refactoring of memory configuration in
CB:32513 ("soc/intel/cannonlake: Support different SPD read type for
each slot"), meminit_cbfs_spd_index ends up reading SPD from CBFS for
each slot. However, for mainboards that use the same SPD index for
each slot this is unneccessary. This change adds a check to see if
spd_data_ptr is not NULL and current spd index is the same as the last
call to decide if SPD read from CBFS should be skipped.
TEST=Verified that SPD gets read only once on hatch.
Change-Id: I91963b55cea534c92207b2cd9f0caa96df8f222b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33137
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Coverity detects pointer mem_info as NULL_RETURNS. Add sanity check
for mem_info to prevent NULL pointer dereference.
BUG=CID 1401394
TEST=Built and boot up to kernel.
Change-Id: I9d78ab38b8b2dd3734e0143acfd88d9093f16ce6
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33152
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Re-add the Kconfig CONSOLE_UART_BASE_ADDRESS. It was lost by accident
on APL at least. It is used outside of soc/intel/ scope, e.g. to con-
figure SeaBIOS.
As we only ever configure a single UART for the coreboot console, we
don't need different addresses for each possible UART. Which saves
us a lot of code.
Change-Id: I28e1d98aa37a6acb57b98b8882fc4fa131d5d309
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Added missing new lines to Debug Output.
Change-Id: I30f208a60661451bc0794c705113e8d19a68b0eb
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33035
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I79e8bc425d5db45abaeb655f86773f3bb1b2f8c4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This is never called: The only calling path is guarded by both
!DRIVERS_UART_8250MEM_32 and INTEL_LPSS_UART_FOR_CONSOLE but the
latter selects the former.
If somebody figures out how this is supposed to be used, we can
easily revive the implementation.
Change-Id: I96e304bdee4eadb52725027d0d662ef75f3d4307
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33093
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We should only provide this implementation when the Intel LPSS UART is
used. Otherwise, no other UART could be used for the console with these
SoCs.
Change-Id: Iebd89edb3f21d4a68587fd02659b4d529f3f4bbe
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
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We only configure the base address for the console UART, the other
addresses are never assigned to the hardware. It seems better to
return 0 for them instead of a spurious value.
Change-Id: I3fa5c99958b56ca5b0b603917c086bdddb677fa2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
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The only path that leads here is guarded by both !DRIVERS_UART_
8250MEM_32 and INTEL_LPSS_UART_FOR_CONSOLE but the latter selects
the former.
Change-Id: I6e0765b028572950991c45b45b2051f4f176a94a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
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Change-Id: I7def72e820ee1a4fa47c34b26dab9e0886ba74e6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
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Change-Id: I99d51176f6d7d6a98a3a3c82aa8e8eee73344496
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33111
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All Baytrail boards have the same GPU PCI ID, so set it
here to avoid having to set it in each board's config.
Move the VGA_BIOS_FILE config from google/rambi into soc/baytrail
since it likewise applies to all Baytrail boards.
Change-Id: Id1e0580b55e3590d868cb839987f06c49bb07cf5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33026
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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gpio_pm_configure clears out all the bits related to PM configuration
in MISCCFG register and sets only the bits requested by mainboard. The
mask as it is set currently results in preserving all PM bits instead
of clearing them. This change updates the mask to ensure that the PM
bits are cleared before setting the ones requested by mainboard.
Change-Id: I5b8c04952775dc1e94fa229328be2f3c1102a468
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Bootblock space is tight on this SoC and recent changes increased it
ever so slightly to make this a problem.
Since the bootblock is well-tested, we can get by without console.
Change-Id: I7496a3e313b2c6ee6fb3c4671eac64376d84e0dc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33068
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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<types.h> is supposed to provide <stdint.h> and <stddef.h>.
When <types.h> is included, <stdint.h> and/or <stddef.h> is removed.
Change-Id: I2db0a647bc657a3626cb5e78f23e9198e290261a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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CONFIG_CBFS_SIZE is only meaningful to generate the default fmap
layout and ought not to be used in the code directly.
Change-Id: Iae72a9fb02d62d7548d34689f5eb371f34cd3d81
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31249
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to add the smbios_slot_desc for the SMBIOS Type9 entries into
the devicetree, and not use numbers but strings like
"SlotTypePciExpressGen3X4", smbios.h needs to be included in the
static.c.
Change-Id: Iace547868b4ce8eb7d3624baf1abd1187c1e5f51
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32965
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Setting up the console and entering postcar can be done in a common
place.
Change-Id: I8a8db0fcb4f0fbbb121a8195a8a8b6644c28db07
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32962
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ASL compiler reports twice warning 'unnecessary/redundant use of Offfset operator'.
Remove redundant offsets.
BUG=N/A
TEST=Facebook FBG-1701 booting Embedded Linux
Change-Id: I16705b9392b17c50d3988012406e03de393cbcd2
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Clang Static Analyzer found version 8.0.0 gnvs is allocated, but
it is never used. Change sizeof(*gnvs) to sizeof(global_nvs_t)
while adding ACPI GNVS to CBMEM.
TEST=Built and boot up to kernel.
Change-Id: Ie9421af4a556d1d88183aa938ee2a124a10ab727
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The file and all of it's functions are unused. Drop the dead code.
Change-Id: Iaddd7a688d431d40f38293939e084d19b286aed4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Clang Static Analyzer version 8.0.0 detects that log2_ceil(bios_size)
and log2_ceil(window_size) are garbage or undefined if the value of
bios_size and window_size is zero. Check bios_size and window_size after
MIN operation to prevent error.
TEST=Built and boot up to kernel.
Change-Id: Ifc3f3da52d129ef5d6063a46b045603a236be759
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Clang Static Analyzer version 8.0.0 detects the division by zero if
gspi_clk_mhz is initialized to 0. gspi_clk_mhz is referred to speed_mhz
in devicetree. Set gspi_clk_mhz to 1 if it is detected as 0 in order to
prevent the division by zero in DIV_ROUND_UP operation. Then the value
of (ref_clk_mhz - 1) will be fed into GSPI's Serial Clock Rate value.
TEST=Built and boot up to kernel.
Change-Id: I6a09474bff114c57d7a9c4c232bb636ff287e4d5
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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All platforms using this code use NO_CAR_GLOBAL_MIGRATION.
Change-Id: I426dee60521045db4711cd253432c65223a64b93
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: If952ad8129e1fa6e45858cb77ec99c9fec55c4a6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I91b6ce3b52d987e2fc0f79e550fda2891502bfe8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: I5dfbc718fd82f0511b0049383e4e93c6f15ee932
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32999
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This soc has NO_CAR_GLOBAL_MIGRATION and does not require CAR_GLOBAL
and car_get/set_x.
Change-Id: I4e2c1c5766e3bcdd4763b42fb925074f7ccd7002
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32998
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These are only used where they are initially declared.
Change-Id: I0a81a945b771b6c29a170c479b9e72c98e8f3c5a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Now that this soc supports NO_CAR_GLOBAL_MIGRATION CAR_GLOBAL and
car_get/set_x are not needed anymore.
Change-Id: Ia7fa97135a4b376ac0bd8b30093a77614cc2cf55
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ib863e23863ba6d7504b6c4d32de2f1fea4e57fec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: I0f393385aa94f18c2e05af3b5a54999575323d18
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Dumping ME status displays wrong information if we disable Heci1 because
it is called after fsp notifies EndOfFirmware and disables Heci1. This patch
moves the ME status dump before fsp notify EndOfFirmware.
TEST=Boot to OS, check ME dump information
Change-Id: Ifd8b18a41c502c4ecfb84698a7669028394589fd
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: Ib11981543575311a32896df385d44cf30aa9387f
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32964
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I496b3a91f765d4fa137c32c9ee1e244803fc25d8
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32850
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to improve boot time with emmc, add ability to send CMD0
and CMD1 early in romstage. This way, by the time system boots to
payload, we are ready to continue with emmc setup and we don't need
to send CMD0 in payload again, and wait for card to reset and be ready.
BUG=b:78106689
TESTS = Boot to OS
Force early_mmc_wake_hw() to return error, recover in payload
Force an error in payload, make sure system can recover/boot
Change-Id: I3488b077bf5100a1e0f2c879fb1436105607d25e
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Change-Id: Ic04cb7c51862bea4d01f853ee2c88cc03c414e35
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32899
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3e304b9b19978c4100ef3486088d809c2a7fe1d7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32898
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic04231525c1aaaf3afc8c11cddc409b1f5b46743
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32913
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a new post code POST_HW_INIT_FAILURE, used when coreboot fails to
detect or initialize a required hardware component.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Add a new post code POST_INVALID_VENDOR_BINARY, used when coreboot fails
to locate or validate a vendor supplied binary.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Add a new post code POST_INVALID_CBFS, used when coreboot fails to
locate or validate a resource that is stored in CBFS.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: If1c8b92889040f9acd6250f847db02626809a987
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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At the end of device enable, print the ME f/w version number.
Before resume or loading payload, dump the ME's Host Firmware
Status registers.
BUG=b:131437724
BRANCH=none
TEST=Prints seemingly sane values on WHL and CML devices.
Change-Id: Ibeb3a2a85cd84c9baa45f90f20a3dcf69f7d5646
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32527
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The entry to AGESA always follows pattern:
amd_create_struct()
amd_dispatch()
amd_release_struct()
Separate the create/release_struct calls from the more
relevant entry point details.
Change-Id: I1037c9daef3365c8672a198ac60f47fc79ffaea1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31488
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Include spi.c in romstage. Since FSP 1.0 can't use
NO_CAR_GLOBAL_MIGRATION, adjust global variables in spi.c
to use CAR_GLOBAL.
Adapted from early versions of CB:21107
Change-Id: I3487fb8ac317ce920bf1c3ef9d89590051932378
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Enabling flashconsole on these platforms fails to build due to
spi.c not being compiled in prior to ramstage. Include in early stages
(bootblock/romstage/postcar) as needed to enable flashconsole support.
Early inclusion of monotonic_timer.c is needed for Broadwell as well.
Change-Id: Idae0578ca92939246021bb85e34b0dcbd41df3b5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This moves FSP1.1 to use postcar stage to tear down CAR.
On platforms with USE_GENERIC_FSP_CAR_INC the FSP header is found
during the postcar stage so there is no need to push to save it
in CAR global variables.
On FSP1.1 platforms with an open source CAR implementation (Skylake,
even though it still runs the FSP-T), the
soc/intel/common/blocks/cpu/car/exit_car.S code tears down CAR.
This also uses common functions to set up the MTRR to use after
CAR is torn down.
Test: build/boot on google/celes (BSW) and google/chell (SKL)
Change-Id: I2330993842aae9c1365230f0c6bd8a2449dc73a5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Change-Id: Iad3982d9db07a1f17ac39e87ff9c37956e40c258
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This patch removes redundant mca_configure() function call
from ramstage to clear machine check exception. First time it's
getting called from soc_core_init() function inside cpu.c file.
TEST=Build and boot SKL/KBL/AML platform without any machine-check
exception.
Change-Id: I7e54fd07816c6317588ab6db06365937c4300ccd
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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AmdCreateStruct() and AmdReleaseStruct() are equally bad
when it comes to lack of correct function declarations
for definitions found in vendorcode binaryPI/AGESA.c.
Replace these with calls that go through the common
module_dispatch() functions.
Change-Id: I611bcbe2a71fb65c8eb759a9dc74cbd9cb74136e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31486
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When FSP UPD parameters are configured, also configure the GSPI CS lines
appropriately. GSPI driver assumes CS0 is the CS signal to use.
BUG=b:130329260
BRANCH=None
TEST=Boot Kohaku, TPM communcation still functional.
Change-Id: Ic816395b7d198a52c704e6cabcb56889150b741c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32791
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Provide option in chip.h to set dynamic local clock gating
setting.
BUG=b:130764684
TEST=Able to build and boot CML.
Change-Id: Iec60076398b745e11d5025e4d7a5c35374d918a4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Provide option in chip.h to set dynamic local clock gating
setting.
BUG=b:130764684
TEST=Able to build and boot ICL.
Change-Id: Ic30a490aadb8cc9c05a19a05533ab0196c69b7f1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch adds new function to perform gpio power management
programming as per EDS.
BUG=b:130764684
TEST=Able to build and boot from fixed media on ICL and CML.
Change-Id: I816a70ad92595f013740a235a9799912ad51665e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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cbmem_find is not available in every stage.
Remove usage of cbmem_find() and use GEN_PMCON1 always.
BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701
Change-Id: Id97d57864b3e241e8f046d9b1caebdce199a46b1
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Fill the DIMM serial number field for SMBIOS from the saved SPD
data that is returned by FSP.
BUG=b:132970635
TEST=This was tested on sarien to ensure that SMBIOS type 17
filled the serial number from the DIMM:
Handle 0x000B, DMI type 17, 40 bytes
Memory Device
Locator: DIMM-A
Serial Number: 41164beb
Change-Id: I85438bd1d581095ea3482dcf077a7f3389f1cd47
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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This fixes the following changes, which made qualcomm Kconfig
appear on all platforms:
bd0b51c0be1ec2c9a5f02de3c13108c13941e2c2
7a3e46d767890f502b09771e19decc5033e27079
Use proper Kconfig logic.
Change-Id: I0195fd186ac39dd4258fe0781dd6d3d1b1d1679f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32805
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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That's how we do it these days.
Change-Id: I1c088d23dff709bcdcb21310059e6a2aab84c0be
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Relocate the I2C bus reset code from gpio.c to i2c.c. When it first
went in, gpio.c was a natural location due to the nature of the
algorithm. This is preparation for moving most of gpio.c to common
code.
Change-Id: I3b2d8e1b54e7c5929220d763bd99fe01b0636aaa
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32650
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the stoneyridge AcpiMmio code into soc/amd/common.
The SB800 southbridge introduced the MMIO hardware blocks at 0xfed80000
commonly known as AcpiMmio. Implementations beginning with Mullins
enable decode in PMx04. Older designs use PMx24 and allow for
configuring the base address. Future work may support the older version.
Comparing the documentation for AMD's RRGs and BKDGs, it is evident that
the block locations have not been reassigned across products. In some
cases, address locations are deprecated and new ones consumed, e.g. the
early GPIO blocks were simpler at offset 0x100 and the newer GPIO banks
are now at 0x1500, 0x1600, and 0x1700.
Note: Do not infer the definitions within the hardware blocks are
consistent across family/model products.
BUG=b:131682806
Change-Id: I083b6339cd29e72289e63c9331a815c46d71600d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32649
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We need to store the acpi_gpio struct, not save its address.
Found-by: Clang Static Analyzer
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I41c8bf10ce72bec736da97ccc33f9ada49804dc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I5a7b53a07fe6fd6121067dcec004e81eb284edbb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Checking BIST is done in the bootblock.
Change-Id: I3ea2eb6a37c038f7348f0abd2056eee5c07bdb9d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32757
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This allows for serial console during the bootblock and enables
bootblock console by default.
Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Previously broadwell used a romcc bootblock and starting verstage in
romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also
possible to have a separate verstage.
This selects using a separate verstage by default but still keeps the
option around to use verstage in romstage.
With a separate verstage the romstage becomes an RW stage.
The mrc.bin however is only added to the RO COREBOOT fmap region as it
requires to be run at a specific offset. This means that coreboot will
have to jump from a RW region to the RO region for that binary and
back to that RW region after that binary is done initializing the
memory.
Change-Id: I900233cadb3c76da329fb98f93917570e633365f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30384
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This puts the cache-as-ram init in the bootblock.
Before setting up cache as ram the microcode updates are applied.
This removes the possibility for a normal/fallback setup although
implementing this should be quite easy.
Setting up LPC in the bootblock to output console on SuperIOs is not
done in this patch, therefore BOOTBLOCK_CONSOLE is not yet selected.
Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The only functional difference is the use of stack guards.
Change-Id: I95645271e0d93a97f544a1cc4e9a4320738e6a20
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As of CL:1605641, vboot2 code should be used for setting and
checking display init state. Remove all vboot1 OPROM-related
code, and use the vboot2 display init code which has already
been added in previous commits.
coreboot should not be reading vboot NVRAM flags directly.
Remove the function vboot_wants_oprom(), and instead rely on
display_init_required(), which uses the
VBOOT_WD_FLAG_DISPLAY_INIT value stored in
vboot_working_data.flags, initialized during verstage.
Note that this means in the case of CONFIG_VBOOT=y, the return
value of display_init_required() can only be trusted after
verstage has been executed. This should not be a problem
assuming that all display initialization occurs in ramstage.
BUG=b:124141368, b:124192753, chromium:948529
TEST=Build locally
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Ic8f9dc5a3c7f1546a8fed82bde02be4d04568f8d
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:1605641, chromium:1605525
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32723
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also clean up cannonlake_memcfg_init.
The major changes include:
(1) Add enum 'mem_info_read_type' to spd_info.
(2) Add per-dimm-slot spd_info to cnl_mb_cfg.
(3) Setup memory config for each slot independently.
(4) Squash meminit_memcfg_spd().
BUG=chromium:960581, b:124990009
BRANCH=none
TEST=boot hatch, hatch_whl, and kohaku
Change-Id: I686a85996858204c20fd05ef24787a0487817c34
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32513
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We need to support entering D3Cold from the OS to work around a bug in
the SDHC where the data lines get stuck always reading zeros.
BUG=b:122749418
TEST=Verified the linux kernel can transition between D3 and D0. Also
verified that the device can suspend and resume and continue to have a
functioning SD controller after.
Change-Id: Ifbf48f20c03a752ce3ff773296b536e92db16a62
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Call the raminit from a common location instead of from the mainboard
specific code.
Change-Id: I65d522237a0bb7b2c032536ede10e2cf93c134d8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32760
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To improve the bootflow, the scope of the pei_data needs to be
extended.
Change-Id: Ic6d91692a7bf9218b81da5bb36b5b26dabac454e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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This also links the gpio configuration instead of including it as a
header.
Change-Id: I9309d2b842495f6cff33fdab18aa139a82c1959c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change-Id: Ib9444f7797289c9b8250cfb16eb1c12dff867ec3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Use BIOS_CNTL defined macro instead of magic number.
Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Add 0x706a8 for GLK Refresh CPU stepping ID.
BUG=b:132414963
BRANCH=None
TEST=Image built successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I4641d9bd4c82211e7200f617cae9043b0f2f38d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Change-Id: Ied645a583f78bc47c8358240acd639132fd499db
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Systems with C_EVIRONMENT_BOOTBLOCK and VBOOT enabled requires functions
tsc_freq_mhz(), vbnv_cmos_failed() and vboot_platform_is_resuming()
in verstage.
Add tsc_freq.c and pmutil.c to verstage.
BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701 + Building Google Banon
Change-Id: Ia509eda6bf415aaa63be71013249493aa472289d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Enable VT-d through fsp upd VtdDisable. Update remapping structure
types in numerical order as all remapping structures of type 0 (DRHD)
enumerated before remapping structures of type 1 (RMRR), and so forth.
BUG=b:130351429
TEST=Booted to kernel and verified the DMAR table contents.
Change-Id: I1d20932e417b9d324edd98c8f2195dc228d2e092
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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Replace locations in the source that explicitely use the CD6/CD7
index/data pair with utility function calls.
Change-Id: I6e7ba472ef2551e363987d18a79408fcd2074de4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Enable early SMBus support compatible with SPD library using Intel SB
common SMBus API.
TEST=boot Protectli FW2B with new FSP, MemoryInit should pass without
errors
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I92a2c5a6d0b38e5658cfdc017041f12717dabdd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Cannonlake PCH LP have total 6 pcie clocks and Cannonlake PCH H have
total 16 pcie clocks. It is different with pcie root port numbers.
BUG=CID 1381814
TEST=Build and boot up fine on sarien platform.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I909b5b584c596e6fe878ffe24d9cabc53c4576ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Zhao <john.zhao@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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The definition of bootblock_systemagent_early_init was guarded by
!ENV_RAMSTAGE. But it's only called in the bootblock. So guard it
with ENV_BOOTBLOCK instead.
Change-Id: I143cf72e4a63b176e4772575e7a60a2a611e4ad9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Use CondRefOf to replace config optios for PTS/WAK acpi method dynamic
loading. Then we can move EC PTS and WAK method to be under mainboard.
BUG=N/A
TEST=Build sarien source code, check build/dsdt.dsl have EC.PTS method
included, build whlrvp soure, check build/dsdt.dsl don't have EC.PTS
method. Both able to build pass.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I9f4bd7240832caf070e65039e4ba2d8656371da8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32371
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add functions to read and write the region in the AcpiMmio block.
Convert gpio.c to use them instead of creating pointers.
Change-Id: I2a0f44b6ec7261648cf0357b44a6c18dd40d1504
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add 16 and 32-bit versions of read / write_misc functions. Find one
access of the MISC block still using read8() and write8(), and convert
it.
Change-Id: I296c521ea7f43210db406013bbe79362545ce6f3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add 8-bit functions to access the AOAC registers and use them in
southbridge.c. At this time, there is no reason to pursue WORD or
DWORD access and it's not known if those transaction sizes are
supported.
Change-Id: I3a8f493625f941fb855c0b8a0eff511a9a5ddfe8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Convert smbus_read8() and smbus_write8() functions to use the same
arguments as the other AcpiMmio blocks, and add 16 and 32 bit versions.
Add matching functions for the ASF controller.
Change-Id: I3b0ecf21f20472245da98ab5e711a54e99dca93a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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In preparation to move code to a common directory, rearrange some of
the functions in sb_util.c. Add various comments. This change should
have no functional differences.
Change-Id: I1ad55a4a14a27e45459dcaf2fcc7449e29da6d4b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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A subsequent patch will move the AcpiMmio support into amd/common.
Take this opportunity to rename the blocks in the 0xfed8xxxx region
with more consistency.
Change-Id: I9a69a6ecfc10f78b4860df05a77a061d2fc8be7d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Fill SMBIOS type 9 fields for both sarien and arcada platform.
BUG=b:129485789
TEST=Boot up into OS and check with dmidecode -t 9 to we do have entry.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Checking the PrimaryDisplay parameter (added by patch with Change
Id Ie3f9362676105e41c69139a094dbb9e8b865689f) isn`t required. The
display connected to PEG works even if IGD is primary for output
image and at the same time this device is disabled
Tested on Asrock H110M-DVS with NVIDIA GTX 1060 GPU
Payload: tianocore edk2-stable201811-216-g51be9d0
Change-Id: I5615597881a151bb004676d914fbf40874ac1f68
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32615
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The DRAM base memory should be calculated even if IGD isn`t defined
in the board device tree
Tested on Asrock H110M-DVS
Change-Id: I3da51473e6c06da803bd969a4a6dff792c18f962
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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`pei_data` was a struct with blob parameters from pre-FSP times.
Somehow, it sneaked into upstream FSP1.1 support (probably because
early board ports were written for a different blob). When added
upstream, its usage was already perverted. It was declared at SoC
level but mostly used to pass mainboard data from mainboard code
to itself and FSP data from FSP code to itself. Now that no board/
SoC code uses it anymore, we can finally drop it.
Change-Id: Ib0bc402703188539cf2254bdc395cca9dd32d863
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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