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AgeCommit message (Expand)Author
2014-12-15tegra124: A couple clock fixes.Gabe Black
2014-12-15tegra124: Add tegra_dc_i2c_aux_read to allow reading EDID.Hung-Te Lin
2014-12-15tegra124: Skip display init when vboot says we don't need it.Gabe Black
2014-12-09spi: Eliminate the spi_cs_activate and spi_cs_deactivate functions.Gabe Black
2014-12-09spi: Remove the spi_set_speed and spi_cs_is_valid functions.Gabe Black
2014-12-09spi: Factor EC protocol details out of the SPI drivers.Gabe Black
2014-12-09UCB RISCV: Switch to DYNAMIC_CBMEMKyösti Mälkki
2014-12-09fsp platfoms: add prototype & consolidate main entry-pointMartin Roth
2014-12-08intel/baytrail: Spelling fixesMartin Roth
2014-12-08intel/fsp_baytrail: Spelling fixesMartin Roth
2014-12-08samsung/exynos5420: Spelling FixesMartin Roth
2014-12-08intel/broadwell: Spelling fixesMartin Roth
2014-12-06soc/qualcomm/ipq806x/Kconfig: Fix indent styleEdward O'Callaghan
2014-12-05fsp_baytrail: Update function disable codeMartin Roth
2014-12-05fsp_baytrail: Kconfig update for Gold 3 FSPMartin Roth
2014-12-05fsp_baytrail: Update microcode for Gold 3 FSP releaseMartin Roth
2014-12-05FSP platform microcode: Update to remove Kconfig variableMartin Roth
2014-12-05ipq8064: Make clock code build in corebootVadim Bendebury
2014-12-05ipq8064: prepare UART driver for use in corebootVadim Bendebury
2014-12-05fsp_baytrail: remove register option for TSEG sizeMartin Roth
2014-12-05fsp_baytrail: update printk to use FSP_INFO_LEVELMartin Roth
2014-12-05fsp_baytrail: update for UPD_DEVICE_CHECK macroMartin Roth
2014-12-05fsp_baytrail: update to add the UPD_MEMDOWN_CHECK macroMartin Roth
2014-12-05fsp_baytrail: update for UPD_SPD_CHECK macroMartin Roth
2014-12-05fsp_baytrail: update to add the UPD_DEFAULT_CHECK macroMartin Roth
2014-12-02Replace hlt with halt()Patrick Georgi
2014-12-01Add UCB RISCV support for architecture, soc, and emulation mainboard..Ronald G. Minnich
2014-12-01Mark non-executable files non-executablePatrick Georgi
2014-11-30Replace hlt() loops with halt()Patrick Georgi
2014-11-28ACPI: Remove CBMEM TOC from GNVSKyösti Mälkki
2014-11-25intel: Remove IRQ1 from possible PIRQ assignemnt.Vladimir Serbinenko
2014-11-24intel/fsp_baytrail: add new CPUID for Baytrail I step D0Herve ELter
2014-11-21intel/fsp_baytrail: add Gold3 FSP supportYork Yang
2014-11-20Replace includes of build.h with version.hKyösti Mälkki
2014-11-19broadwell: move to per-device ACPI.Vladimir Serbinenko
2014-11-19fsp_baytrail: Fix ACPI 'Object is not referenced' warningsMartin Roth
2014-11-19fsp_baytrail: Update chip.h UPD entries to match names in fspvpd.hMartin Roth
2014-11-18tegra124: remove spurious error messagePatrick Georgi
2014-11-18tegra124: actually parse is_lvdsPatrick Georgi
2014-11-18baytrail: fix range checkPatrick Georgi
2014-11-14tegra124: allow tegra124 devices to run vboot rmoduleAaron Durbin
2014-11-14tegra124: i2c: Reset the controller when there's an error.Gabe Black
2014-11-14tegra124: fix the dangerous VPR write orderJoseph Lo
2014-11-14tegra124: Add some functions for resetting peripherals.Gabe Black
2014-11-14t124: Clean up display init functionsJimmy Zhang
2014-11-13intel: use crosscompiler readelf, instead of globalPatrick Georgi
2014-11-13arm: Put assembly functions into separate sectionsJulius Werner
2014-11-13ipq8064: Make timer code compileVadim Bendebury
2014-11-13ipq8064: Configure proper bootblock stack and load addressVadim Bendebury
2014-11-13Use sbl blobs from a private locationVadim Bendebury
2014-11-13ipq806x: Add support for GPIO operationsFurquan Shaikh
2014-11-13tegra124: Add a macro specifically for configuring the I2C controller clocks.Gabe Black
2014-11-13tegra124: Fix some bugs in the clock configuration macros.Gabe Black
2014-11-13t124: Skip PLLP init to 408MHzJimmy Zhang
2014-11-13t124: nyan: Enable lock bit on pllJimmy Zhang
2014-11-13tegra124: fix OSC initialization on LP0 resumeAndrew Bresticker
2014-11-13tegra124: fix PLLU parametersAndrew Bresticker
2014-11-13tegra124: Make the PLLX frequency selectable by model.Gabe Black
2014-11-12ipq806x: Typecast address to void * in read/write operationsFurquan Shaikh
2014-11-12ipq806x: Add an include/ folder to ipq806xFurquan Shaikh
2014-11-12Copy u-boot sources as is and modify the tree to still buildVadim Bendebury
2014-11-12Include IPQ8064 SBLs code in the coreboot bootblockVadim Bendebury
2014-11-12tegra124: enable JTAG in Security ModeJimmy Zhang
2014-11-12tegra124: Program PWM1 to drive panel backlightAndrew Chew
2014-11-12tegra124: Add pwm_controller registersAndrew Chew
2014-11-12tegra124: Fix PWM pinmux functionsAndrew Chew
2014-11-12tegra124: Add PWM base addressAndrew Chew
2014-11-12tegra124: nyan: Keep in memory structures below 4GB.Gabe Black
2014-11-10arm: Redesign, clarify and clean up cache related codeJulius Werner
2014-11-09src: Too many terminators ';;' at end of stmts, stop SkynetEdward O'Callaghan
2014-11-09Provide ability to integrate with QComm SBLsVadim Bendebury
2014-11-09arm: Thumb ALL the things!Julius Werner
2014-11-08intel: Use 'FORCEWAKE_ACK_HSW' define over '0x130044'Edward O'Callaghan
2014-11-04Redundant addr '&' operator on func ptr's in struct initiatorEdward O'Callaghan
2014-11-01{cpu,soc}: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
2014-10-28baytrail: Remove unused devicetree fieldsShawn Nematbakhsh
2014-10-28baytrail: gfx: Don't configure hotplug + backlight registersShawn Nematbakhsh
2014-10-28Baytrail/dptf: Always return 0 in TCPU._PPCKein Yuan
2014-10-28baytrail: handle MRC being an ELF fileAaron Durbin
2014-10-28baytrail: Configure MSR for 2-core and 4-core P-state configutationDuncan Laurie
2014-10-28baytrail: move cache-as-ram base address to 0xfe000000Aaron Durbin
2014-10-28baytrail: romstage: Add function to check SW WP status for vbootShawn Nematbakhsh
2014-10-22reg_script: default to n for ARCH_X86Isaac Christensen
2014-10-22tegra/nyan*: sdram updatesTom Warren
2014-10-22cmos: Rename the CMOS related functions.Gabe Black
2014-10-22broadwell: Update Haswell and Broadwell E0 microcodeDuncan Laurie
2014-10-22broadwell: Update microcodeDuncan Laurie
2014-10-22broadwell: ACPI, romstage, and other updatesDuncan Laurie
2014-10-22broadwell: Update D0 microcode to FFFF000EDuncan Laurie
2014-10-22broadwell: Update microcode for supported CPUsDuncan Laurie
2014-10-22broadwell: add new intel SOCDuncan Laurie
2014-10-22baytrail: Move HDA verb table to Intel SOC common directoryDuncan Laurie
2014-10-22baytrail: Move MRC cache code to a common directoryDuncan Laurie
2014-10-22baytrail/rambi: S3 support and other updatesKein Yuan
2014-10-19x86 romstage: Move stack just below RAMTOPKyösti Mälkki
2014-10-19haswell baytrail: Enable RELOCATABLE_RAMSTAGEKyösti Mälkki
2014-10-16uarts: 32/64 cleanupRonald G. Minnich
2014-10-14intel/fsp_baytrail: Add padding so device_nvs location matches ACPIScott Radcliffe
2014-10-14baytrail: Add padding to the end of device_nvs to match ACPIScott Radcliffe
2014-10-14intel/fsp_baytrail: Clear the GNVS area prior to fillingScott Radcliffe
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