coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-12-05	mb/emulation/spike-riscv: Implement mtime_init	Jonathan Neuschäfer
2018-11-05	riscv: add support smp_pause / smp_resume	Xiang Wang
2018-09-14	arch/riscv: provide a monotonic timer	Philipp Hug
2018-09-10	soc/sifive/fu540: Makefile: include mtime_init in ramstage	Philipp Hug
2018-09-10	riscv: update mtime initialization	Xiang Wang
2018-07-17	riscv: add support for modifying compiler options	Xiang Wang
2017-12-02	riscv: Remove config string support	Jonathan Neuschäfer
2017-11-07	RISC-V boards: Stop using the config string	Jonathan Neuschäfer
2016-12-06	soc/ucb/riscv: Place CBMEM at top of autodetected RAM	Jonathan Neuschäfer
2016-08-15	soc/ucb/riscv: select BOOTBLOCK_CONSOLE	Jonathan Neuschäfer
2016-07-15	arch/riscv: Move CBMEM into RAM	Jonathan Neuschäfer
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-29	kbuild: automatically include SOCs	Stefan Reinauer
2015-01-27	CBMEM: Always use DYNAMIC_CBMEM	Kyösti Mälkki
2015-01-27	vboot2: add verstage	Stefan Reinauer
2014-12-09	UCB RISCV: Switch to DYNAMIC_CBMEM	Kyösti Mälkki
2014-12-01	Add UCB RISCV support for architecture, soc, and emulation mainboard..	Ronald G. Minnich