| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-09-10 | riscv: update mtime initialization | Xiang Wang | |
| Add a interface, which is implemented by SoC. Change-Id: I5524732f6eb3841e43afd176644119b03b5e5e27 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> | |||
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