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Change-Id: I0b9bd00a5de4c2c8d91fa9d595d3ee313356048a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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There is a lot of going back-and-forth with the KiB arguments, start
the work to migrate away from this.
Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that the console system itself will clearly differentiate loglevels,
it is no longer necessary to explicitly add "ERROR: " in front of every
BIOS_ERR message to help it stand out more (and allow automated tooling
to grep for it). Removing all these extra .rodata characters should save
us a nice little amount of binary size.
This patch was created by running
find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';'
and doing some cursory review/cleanup on the result. Then doing the same
thing for BIOS_WARN with
's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi'
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Lance Zhao
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
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The sizeof() operator was being applied to a pointer-to-struct type.
Correct this, so that the entire struct space gets cleared.
Change-Id: Ieab3aaa2d07a928f27004b94132377d5dae935c0
Found-by: Coverity CID 1451732
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52054
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Sam Lewis <sam.vr.lewis@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Maps the useable RAM so that it can be used for booting a payload.
TEST: Booted a simple ELF payload (that just flashes LEDs) on the
Beaglebone Black.
Change-Id: I7f657c97e4753071c90ba8ca800a96108807e6b9
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44388
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adds code taken and (barely) adapted from U-Boot (release 2020.04,
commit 36fec02b1f90b92cf51ec531564f9284eae27ab4) for SDRAM initialization.
This should in theory work for other configurations than the Beaglebone
Black's DRAM configuration, but hasn't been tested.
Change-Id: Ib1bc2fa606f7010c8c789aa7a5c37cd41bc484b9
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44386
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adds a "sd_media" boot_device to allow booting from the SD card. This
assumes that the generated "MLO" file is placed at a 128KB offset from
the start of the SD card, to allow for the MBR etc. to be at the start
of the SD card. Placing the MLO file here allows the AM335x boot ROM to
load and execute the bootblock stage as well, as 128KB is one of the
offsets the boot ROM checks when looking for the next stage to execute.
As part of this, a FMD for the Beaglebone has also been defined. It's
sized at 32M somewhat arbitrarily, as SD cards could allow for much
bigger payloads.
TEST: Beaglebone boots from bootblock into romstage. Romstage to
ramstage still doesn't work as it needs RAM initialization first.
Change-Id: I5f6901217fb974808e84aeb679af2f47eeae30fd
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44385
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adds a driver for the am335x MMC peripheral. This has only been tested
with SD cards and probably needs some modification to use eMMC or MMC
cards.
It's also currently a little slow as it only supports reading a block at
a time.
Change-Id: I5c2b250782cddca17aa46cc8222b9aebef505fb2
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Use of 'offsetof' needs <commonlib/bsd/helpers.h>.
Change-Id: Ie250b20f464909649b2bd038dbb757d5df637486
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44738
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is
enabled by default. Some older chipsets with insufficient SRAM/CAR space
still have it explicitly disabled. All others get the new section added
to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Implements the monotonic timer using the am335x dmtimer peripheral.
Change-Id: I4736b6d3b6e26370be9e8f369fc02285ad519223
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44383
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enables the MMU primarily to allow the unaligned word reads that the
FMAP code requires. Without enabling this, the chip gets data access
exceptions.
Enabling the MMU also gives some advantages in allowing the icache and
dcache to be enabled, so is probably worth doing regardless.
Change-Id: Ic571570cc44b0696ea61cc76e3bce7167a3256cf
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The UART index is never negative, so make it unsigned and drop the
checks for the index to be non-negative.
Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Allows the AM335X to boot from the coreboot generated MLO by:
- Fixing the load address in the MLO header to be the start of SRAM
- Fixing the way that the bootblock size is calculated (which is
embedded into the MLO so that the MLO knows how much to load into
SRAM). The previous method relied on parsing cbfstool output - the
output has changed format since this was originally written so this no
longer works. Directly using the filesize of the built binary is
probably a more stable way of doing this.
As part of this, the start addresses of SRAM and DRAM were fixed to be
consistent with the AM335x Technical Reference Manual (spruh73, rev Q).
TEST: Booted Beaglebone Black from MLO placed at offset 0x00 on an SD card
Change-Id: I514d7cda65ddcbf27e78286dc6857c9e81ce6f9e
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44381
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The AM335X is a SoC, so should be in the soc tree.
This moves all the existing am335x code to soc/ and updates any
references. It also adds a soc.c file as required for the ramstage.
Change-Id: Ic1ccb0e9b9c24a8b211b723b5f4cc26cdd0eaaab
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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