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path: root/src/soc/sifive
AgeCommit message (Expand)Author
2018-12-03soc/sifive/fu540: Simplify UART refclk calculationJonathan Neuschäfer
2018-11-05riscv: add support smp_pause / smp_resumeXiang Wang
2018-10-30sifive/fu540: correct cbmem supportPhilipp Hug
2018-09-26soc/sifive/fu540: Document #if ENV_ROMSTAGE lineJonathan Neuschäfer
2018-09-26soc/sifive/fu540: Remove PLL parameters from sdram.cJonathan Neuschäfer
2018-09-15sifive/hifive-unleashed: enable CBMEM supportPhilipp Hug
2018-09-15soc/sifive: move ram_resource to mainboardPhilipp Hug
2018-09-14soc/sifive/fu540: Implement uart_platform_refclk for UART divisor calculationPhilipp Hug
2018-09-14soc/sifive/fu540: Initialize SDRAMPhilipp Hug
2018-09-14soc/sifive/fu540: Switch clock to 1GHz in romstagePhilipp Hug
2018-09-14soc/sifive/fu540: create ram_resource with actual memory sizePhilipp Hug
2018-09-14arch/riscv: provide a monotonic timerPhilipp Hug
2018-09-14soc/sifive/fu540: add SiFive supplied header files for SDRAM initializationPhilipp Hug
2018-09-13soc/sifive/fu540: Get SDRAM controller out of resetPhilipp Hug
2018-09-13soc/sifive/fu540: Update clock settings according SiFive bootloaderPhilipp Hug
2018-09-13uart/sifive: make divisor configurablePhilipp Hug
2018-09-12soc/sifive/fu540: Initialize PLL and clockPhilipp Hug
2018-09-10soc/sifive: fix compiler warningPhilipp Hug
2018-09-10soc/sifive/fu540: Makefile: include mtime_init in ramstagePhilipp Hug
2018-09-10soc/sifive/fu540: Add driver for OTP memoryPhilipp Hug
2018-09-10soc/sifive/fu540: add CLINT supportXiang Wang
2018-09-10riscv: update mtime initializationXiang Wang
2018-09-02riscv: separately define stack locations at different stagesXiang Wang
2018-07-18sifive/fu540: add empty sdram init and size functionsPhilipp Hug
2018-07-17riscv: add support for modifying compiler optionsXiang Wang
2018-04-26src/sifive: Add the SiFive Freedom Unleashed 540 SoCJonathan Neuschäfer