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path: root/src/soc/sifive/fu540
AgeCommit message (Expand)Author
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
2020-05-08{security,soc}/*/Kconfig: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS
2020-04-05soc/sifive: Use SPDX for GPL-2.0-only filesAngel Pons
2020-03-18soc: Remove copyright noticesPatrick Georgi
2020-02-24soc/{samsung,sifive}: Fix typosElyes HAOUAS
2019-12-20src: Replace min/max() with MIN/MAX()Elyes HAOUAS
2019-12-19soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h>Elyes HAOUAS
2019-12-11fmap: Make FMAP_CACHE mandatory if it is configured inJulius Werner
2019-12-04Change all clrsetbits_leXX() to clrsetbitsXX()Julius Werner
2019-11-14soc/sifive/fu540: Support booting from SD cardXiang Wang
2019-11-01lib/cbmem_top: Add a common cbmem_top implementationArthur Heymans
2019-11-01soc/{mediatek,sifive}: Remove unused 'include <arch/barrier.h>'Elyes HAOUAS
2019-10-16soc/sifive/fu540: test and fix code of fu540 spiXiang Wang
2019-08-12soc/sifive/fu540: add code for spi and map flash to memory spacesXiang Wang
2019-08-05soc/sifive/fu540: Add opensbi supportPatrick Rudolph
2019-07-09arch/non-x86: Flip HAVE_MONOTONIC_TIMER defaultKyösti Mälkki
2019-03-18src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet ControllerXiang Wang
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
2019-01-24riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCVRonald G. Minnich
2019-01-17riscv: create Kconfig architecture features for new partsRonald G. Minnich
2019-01-14console: Change BOOTBLOCK_CONSOLE default to `y`Nico Huber
2018-12-07riscv: fix non-SMP supportPhilipp Hug
2018-12-05soc/sifive/fu540: Add helper function to get tlclk frequencyJonathan Neuschäfer
2018-12-04soc/sifive/fu540: Load PLL settings from a structJonathan Neuschäfer
2018-12-03soc/sifive/fu540: Simplify UART refclk calculationJonathan Neuschäfer
2018-11-05riscv: add support smp_pause / smp_resumeXiang Wang
2018-10-30sifive/fu540: correct cbmem supportPhilipp Hug
2018-09-26soc/sifive/fu540: Document #if ENV_ROMSTAGE lineJonathan Neuschäfer
2018-09-26soc/sifive/fu540: Remove PLL parameters from sdram.cJonathan Neuschäfer
2018-09-15sifive/hifive-unleashed: enable CBMEM supportPhilipp Hug
2018-09-15soc/sifive: move ram_resource to mainboardPhilipp Hug
2018-09-14soc/sifive/fu540: Implement uart_platform_refclk for UART divisor calculationPhilipp Hug
2018-09-14soc/sifive/fu540: Initialize SDRAMPhilipp Hug
2018-09-14soc/sifive/fu540: Switch clock to 1GHz in romstagePhilipp Hug
2018-09-14soc/sifive/fu540: create ram_resource with actual memory sizePhilipp Hug
2018-09-14arch/riscv: provide a monotonic timerPhilipp Hug
2018-09-14soc/sifive/fu540: add SiFive supplied header files for SDRAM initializationPhilipp Hug
2018-09-13soc/sifive/fu540: Get SDRAM controller out of resetPhilipp Hug
2018-09-13soc/sifive/fu540: Update clock settings according SiFive bootloaderPhilipp Hug
2018-09-13uart/sifive: make divisor configurablePhilipp Hug
2018-09-12soc/sifive/fu540: Initialize PLL and clockPhilipp Hug
2018-09-10soc/sifive: fix compiler warningPhilipp Hug
2018-09-10soc/sifive/fu540: Makefile: include mtime_init in ramstagePhilipp Hug
2018-09-10soc/sifive/fu540: Add driver for OTP memoryPhilipp Hug
2018-09-10soc/sifive/fu540: add CLINT supportXiang Wang
2018-09-10riscv: update mtime initializationXiang Wang
2018-09-02riscv: separately define stack locations at different stagesXiang Wang
2018-07-18sifive/fu540: add empty sdram init and size functionsPhilipp Hug
2018-07-17riscv: add support for modifying compiler optionsXiang Wang
2018-04-26src/sifive: Add the SiFive Freedom Unleashed 540 SoCJonathan Neuschäfer