coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2018-12-05	soc/sifive/fu540: Add helper function to get tlclk frequency	Jonathan Neuschäfer
	tlclk is not specific to the UART block in the FU540, so let's calculate its frequency in clock.c. Change-Id: I270920027f1132253e413a1bf9feb4fe279b651a Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/29335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-12-04	soc/sifive/fu540: Load PLL settings from a struct	Jonathan Neuschäfer
	The different PLLs in the fu540 use the same register layout, so use one function (configure_pll) to program a PLL and wait for it to lock. This also makes it possible to dynamically calculate the PLL settings later. TEST=Boot until "Payload not loaded" on HiFive Unleashed Change-Id: I5c0cee886bad5758c70f967d2bb998c1e1a736ab Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/29356 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03	soc/sifive/fu540: Simplify UART refclk calculation	Jonathan Neuschäfer
	clock_get_coreclk_khz() already detects whether the PLL or the input clock (hfclk) is used. Tested on HiFive Unleashed. Change-Id: I264977b0de0b81ef74a014984b6d33638ab33f4b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/29334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-09-26	soc/sifive/fu540: Document #if ENV_ROMSTAGE line	Jonathan Neuschäfer
	Change-Id: Idcd72c558e46637b1b99e9613963436fedd4a8b9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28699 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-14	soc/sifive/fu540: Switch clock to 1GHz in romstage	Philipp Hug
	Invoke clock_init in romstage for SiFive Unleashed. Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-13	soc/sifive/fu540: Get SDRAM controller out of reset	Philipp Hug
	Change-Id: Ifa6faffbaf353379f57e0f80c1c4ca2fc380f874 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-13	soc/sifive/fu540: Update clock settings according SiFive bootloader	Philipp Hug
	The documentation unfortunately doesn't match what SiFive uses in their FSBL. Use the same values as in FSBL to make DDR RAM work. Change-Id: I844cc41ed197333adeae495e71ea70b4a9603650 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28582 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-12	soc/sifive/fu540: Initialize PLL and clock	Philipp Hug
	Change-Id: Iba0669e08940e373aaf42cbba3a1ceffd68a4f52 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>