| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-09-14 | soc/sifive/fu540: Switch clock to 1GHz in romstage | Philipp Hug |
| 2018-09-13 | soc/sifive/fu540: Get SDRAM controller out of reset | Philipp Hug |
| 2018-09-13 | soc/sifive/fu540: Update clock settings according SiFive bootloader | Philipp Hug |
| 2018-09-12 | soc/sifive/fu540: Initialize PLL and clock | Philipp Hug |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |